 A_ALTCHARSET |
|
| A_ATTRIBUTES |
|
| A_BLINK |
|
| A_BOLD |
|
| A_CHARTEXT |
|
| A_CNF_10B_2 |
|
| A_CNF_10B_2 |
|
| A_CNF_10B_T |
|
| A_CNF_10B_T |
|
| A_CNF_AUI |
|
| A_CNF_AUI |
|
| A_CNF_DC_DC_POLARITY |
|
| A_CNF_DC_DC_POLARITY |
|
| A_CNF_EXTND_10B_2 |
|
| A_CNF_EXTND_10B_2 |
|
| A_CNF_LOW_RX_SQUELCH |
|
| A_CNF_LOW_RX_SQUELCH |
|
| A_CNF_MEDIA_10B_2 |
|
| A_CNF_MEDIA_10B_2 |
|
| A_CNF_MEDIA_10B_T |
|
| A_CNF_MEDIA_10B_T |
|
| A_CNF_MEDIA_AUI |
|
| A_CNF_MEDIA_AUI |
|
| A_CNF_MEDIA_AUTO |
|
| A_CNF_MEDIA_AUTO |
|
| A_CNF_MEDIA_TYPE |
|
| A_CNF_MEDIA_TYPE |
|
| A_CNF_NO_AUTO_POLARITY |
|
| A_CNF_NO_AUTO_POLARITY |
|
| A_COLOR |
|
| A_COLOUR |
|
| A_DEFAULT |
|
| A_DIM |
|
| A_INVIS |
|
| A_N_ENABLE |
|
| A_N_ENABLE |
|
| A_PROTECT |
|
| A_REVERSE |
|
| A_STANDOUT |
|
| A_UNDERLINE |
|
| A20_INT15_RETRIES |
|
| A20_KBC_RETRIES |
|
| A20_MAX_RETRIES |
|
 a20_methods |
|
| A20_SCPA_RETRIES |
|
 a3c90x_close |
a3c90x_close - free()s TX and RX ring, disablex RX/TX, resets NIC |
| a3c90x_close |
a3c90x_close - free()s TX and RX ring, disablex RX/TX, resets NIC |
| a3c90x_free_resources |
|
| a3c90x_free_resources |
|
| a3c90x_free_rx_iobuf |
|
| a3c90x_free_rx_iobuf |
|
| a3c90x_free_rx_ring |
|
| a3c90x_free_rx_ring |
|
| a3c90x_free_tx_ring |
|
| a3c90x_free_tx_ring |
|
| a3c90x_hw_start |
a3c90x_hw_start - Initialize hardware, copy MAC address |
| a3c90x_hw_start |
a3c90x_hw_start - Initialize hardware, copy MAC address |
| a3c90x_internal_IssueCommand |
|
| a3c90x_internal_IssueCommand |
|
| a3c90x_internal_ReadEeprom |
a3c90x_internal_ReadEeprom - nvs routine to read eeprom data |
| a3c90x_internal_ReadEeprom |
a3c90x_internal_ReadEeprom - nvs routine to read eeprom data |
| a3c90x_internal_ReadEepromContents |
|
| a3c90x_internal_ReadEepromContents |
|
| a3c90x_internal_SetWindow |
|
| a3c90x_internal_SetWindow |
|
| a3c90x_internal_WaitForEeprom |
|
| a3c90x_internal_WaitForEeprom |
|
| a3c90x_internal_WriteEeprom |
a3c90x_internal_WriteEeprom - nvs routine to write eeprom data |
| a3c90x_internal_WriteEeprom |
a3c90x_internal_WriteEeprom - nvs routine to write eeprom data |
| a3c90x_irq |
|
| a3c90x_irq |
|
| a3c90x_open |
a3c90x_open - Routine to initialize the card. Initialize hardware, |
| a3c90x_open |
a3c90x_open - Routine to initialize the card. Initialize hardware, |
| a3c90x_poll |
a3c90x_poll - Routine that gets called periodically. |
| a3c90x_poll |
a3c90x_poll - Routine that gets called periodically. |
| a3c90x_prepare_rx_desc |
a3c90x_prepare_rx_desc - fills the rx desc with initial data |
| a3c90x_prepare_rx_desc |
a3c90x_prepare_rx_desc - fills the rx desc with initial data |
| a3c90x_probe |
|
| a3c90x_probe |
|
| a3c90x_process_rx_packets |
a3c90x_process_rx_packets - Checks for received packets, |
| a3c90x_process_rx_packets |
a3c90x_process_rx_packets - Checks for received packets, |
| a3c90x_process_tx_packets |
a3c90x_process_tx_packets - Checks for successfully sent packets, |
| a3c90x_process_tx_packets |
a3c90x_process_tx_packets - Checks for successfully sent packets, |
| a3c90x_refill_rx_ring |
a3c90x_refill_rx_ring -checks every entry in the rx ring and reallocates |
| a3c90x_refill_rx_ring |
a3c90x_refill_rx_ring -checks every entry in the rx ring and reallocates |
| a3c90x_remove |
a3c90x_remove - Routine to remove the card. Unregisters |
| a3c90x_remove |
a3c90x_remove - Routine to remove the card. Unregisters |
| a3c90x_reset |
|
| a3c90x_reset |
|
| a3c90x_setup_rx_ring |
a3c90x_setup_rx_ring - Allocates RX ring, initialize rx_desc values |
| a3c90x_setup_rx_ring |
a3c90x_setup_rx_ring - Allocates RX ring, initialize rx_desc values |
| a3c90x_setup_tx_ring |
a3c90x_setup_tx_ring - Allocates TX ring, initialize tx_desc values |
| a3c90x_setup_tx_ring |
a3c90x_setup_tx_ring - Allocates TX ring, initialize tx_desc values |
| a3c90x_transmit |
a3c90x_transmit - Transmits a packet. |
| a3c90x_transmit |
a3c90x_transmit - Transmits a packet. |
| AAC |
Address ROM Address Counter (1->enable) |
| AAC |
Address ROM Address Counter (1->enable) |
 abft.c |
|
 abft.h |
|
| abft_fill_data |
Fill in all variable portions of aBFT |
| ABFT_SIG |
|
 abft_table |
|
| abftab |
|
 abort() |
|
| abort() |
|
| ACF_CONNECTOR_AUI |
|
| ACF_CONNECTOR_AUI |
|
| ACF_CONNECTOR_BITS |
|
| ACF_CONNECTOR_BITS |
|
| ACF_CONNECTOR_BNC |
|
| ACF_CONNECTOR_BNC |
|
| ACF_CONNECTOR_UTP |
|
| ACF_CONNECTOR_UTP |
|
| ACK |
|
| ACK_INTR |
|
| ACK_INTR |
|
| ACK_INTR |
|
| ACK_INTR |
|
| ACON |
ALE control |
| ACON |
ALE control |
| acpi.c |
|
| acpi.c |
|
| acpi.h |
|
| ACPI_ADR_DEVICE_PATH |
|
| ACPI_ADR_DISPLAY_TYPE_EXTERNAL_ |
|
| ACPI_ADR_DISPLAY_TYPE_INTERNAL_ |
|
| ACPI_ADR_DISPLAY_TYPE_OTHER |
|
| ACPI_ADR_DISPLAY_TYPE_TV |
|
| ACPI_ADR_DISPLAY_TYPE_VGA |
|
| ACPI_ADR_DP |
|
| acpi_description_header |
|
| ACPI_DEVICE_PATH |
|
| ACPI_DISPLAY_ADR(_DeviceIdScheme, _HeadId, _NonVgaOutput, _BiosCanDetect, _VendorInfo, _Type, _Port, _Index) |
|
| ACPI_DP |
|
| ACPI_EXTENDED_DP |
|
| ACPI_EXTENDED_HID_DEVICE_PATH |
|
| acpi_fix_checksum |
@file |
| acpi_fix_checksum |
@file |
| ACPI_HID_DEVICE_PATH |
|
| ACPI_LENOFF_LEN_MASK |
|
| ACPI_LENOFF_LEN_MASK |
|
| ACPI_LENOFF_LEN_SHIFT |
|
| ACPI_LENOFF_LEN_SHIFT |
|
| ACPI_LENOFF_OFF_MASK |
|
| ACPI_LENOFF_OFF_MASK |
|
| ACPI_LENOFF_OFF_SHIFT |
|
| ACPI_LENOFF_OFF_SHIFT |
|
| ACS_BLOCK |
|
| ACS_BOARD |
|
| ACS_BTEE |
|
| ACS_BULLET |
|
| ACS_CKBOARD |
|
| ACS_DARROW |
|
| ACS_DEGREE |
|
| ACS_DIAMOND |
|
| ACS_HLINE |
|
| ACS_LANTERN |
|
| ACS_LARROW |
|
| ACS_LLCORNER |
|
| ACS_LRCORNER |
|
| ACS_LTEE |
|
| ACS_PLMINUS |
|
| ACS_PLUS |
|
| ACS_RARROW |
|
| ACS_RTEE |
|
| ACS_S1 |
|
| ACS_S9 |
|
| ACS_TTEE |
|
| ACS_UARROW |
|
| ACS_ULCORNER |
|
| ACS_URCORNER |
|
| ACS_VLINE |
|
| ActionCommands |
|
| ACTIVATE_ADAPTER_TO_CONFIG |
|
| ACTIVATE_ADAPTER_TO_CONFIG |
|
| activate_t509_device |
|
| activate_t509_device |
|
| ACTIVE_33V |
|
| ACTIVE_33V |
|
| adapter |
|
| adapter |
|
| ADAPTER_CNF_OFFSET |
|
| ADAPTER_CNF_OFFSET |
|
| add_ipv4_miniroute |
Add IPv4 minirouting table entry |
| add_ipv6_address |
Add IPv6 interface |
| add_ipv6_miniroute |
Add IPv6 minirouting table entry |
| ADD_MASK |
Mask it use of the ADD_PORT register |
| ADD_MASK |
Mask it use of the ADD_PORT register |
| add_ndp_entry |
Add NDP entry |
| ADD_PORT |
|
| ADD_PORT |
|
| ADD_SIG |
Expected ID signature |
| ADD_SIG |
Expected ID signature |
| add_socket_i365 |
|
| add_socket_i365 |
|
| add_tls |
Instantiator |
| ADDR0 |
|
| ADDR0 |
|
| ADDR1 |
|
| ADDR1 |
|
| ADDR2 |
|
| ADDR2 |
|
| adjust_pci_device |
Enable PCI device |
| adjust_pci_device |
Enable PCI device |
| ADVERTISE_10_FULL |
|
| ADVERTISE_10_FULL |
|
| ADVERTISE_10_HALF |
|
| ADVERTISE_10_HALF |
|
| ADVERTISE_100_FULL |
|
| ADVERTISE_100_FULL |
|
| ADVERTISE_100_HALF |
|
| ADVERTISE_100_HALF |
|
| ADVERTISE_1000_FULL |
|
| ADVERTISE_1000_FULL |
|
| ADVERTISE_1000_HALF |
|
| ADVERTISE_1000_HALF |
|
| ADVERTISE_1000FULL |
Advertise 1000BASE-T full duplex |
| ADVERTISE_1000HALF |
Advertise 1000BASE-T half duplex |
| ADVERTISE_1000XFULL |
Try for 1000BASE-X full-duplex |
| ADVERTISE_1000XHALF |
Try for 1000BASE-X half-duplex |
| ADVERTISE_1000XPAUSE |
Try for 1000BASE-X pause |
| ADVERTISE_1000XPSE_ASYM |
Try for 1000BASE-X asym pause |
| ADVERTISE_100BASE4 |
Try for 100mbps 4k packets |
| ADVERTISE_100FULL |
Try for 100mbps full-duplex |
| ADVERTISE_100HALF |
Try for 100mbps half-duplex |
| ADVERTISE_10FULL |
Try for 10mbps full-duplex |
| ADVERTISE_10HALF |
Try for 10mbps half-duplex |
| ADVERTISE_ALL |
|
| ADVERTISE_CSMA |
Only selector supported |
| ADVERTISE_FULL |
|
| ADVERTISE_LPACK |
Ack link partners response |
| ADVERTISE_NPAGE |
Next page bit |
| ADVERTISE_PAUSE_ASYM |
Try for asymetric pause |
| ADVERTISE_PAUSE_CAP |
Try for pause |
| ADVERTISE_RESV |
Unused... |
| ADVERTISE_RFAULT |
Say we can detect faults |
| ADVERTISE_SLCT |
Selector bits |
| ADVERTISED_1000baseT_Full |
|
| ADVERTISED_1000baseT_Full |
|
| ADVERTISED_1000baseT_Full |
|
| ADVERTISED_1000baseT_Full |
|
| ADVERTISED_1000baseT_Full |
|
| ADVERTISED_1000baseT_Full |
|
| ADVERTISED_1000baseT_Full |
|
| ADVERTISED_1000baseT_Half |
|
| ADVERTISED_1000baseT_Half |
|
| ADVERTISED_1000baseT_Half |
|
| ADVERTISED_1000baseT_Half |
|
| ADVERTISED_1000baseT_Half |
|
| ADVERTISED_1000baseT_Half |
|
| ADVERTISED_1000baseT_Half |
|
| ADVERTISED_100baseT_Full |
|
| ADVERTISED_100baseT_Full |
|
| ADVERTISED_100baseT_Full |
|
| ADVERTISED_100baseT_Full |
|
| ADVERTISED_100baseT_Full |
|
| ADVERTISED_100baseT_Full |
|
| ADVERTISED_100baseT_Full |
|
| ADVERTISED_100baseT_Half |
|
| ADVERTISED_100baseT_Half |
|
| ADVERTISED_100baseT_Half |
|
| ADVERTISED_100baseT_Half |
|
| ADVERTISED_100baseT_Half |
|
| ADVERTISED_100baseT_Half |
|
| ADVERTISED_100baseT_Half |
|
| ADVERTISED_10baseT_Full |
|
| ADVERTISED_10baseT_Full |
|
| ADVERTISED_10baseT_Full |
|
| ADVERTISED_10baseT_Full |
|
| ADVERTISED_10baseT_Full |
|
| ADVERTISED_10baseT_Full |
|
| ADVERTISED_10baseT_Full |
|
| ADVERTISED_10baseT_Half |
|
| ADVERTISED_10baseT_Half |
|
| ADVERTISED_10baseT_Half |
|
| ADVERTISED_10baseT_Half |
|
| ADVERTISED_10baseT_Half |
|
| ADVERTISED_10baseT_Half |
|
| ADVERTISED_10baseT_Half |
|
| ADVERTISED_AUI |
|
| ADVERTISED_AUI |
|
| ADVERTISED_AUI |
|
| ADVERTISED_AUI |
|
| ADVERTISED_Autoneg |
|
| ADVERTISED_Autoneg |
|
| ADVERTISED_Autoneg |
|
| ADVERTISED_Autoneg |
|
| ADVERTISED_BNC |
|
| ADVERTISED_BNC |
|
| ADVERTISED_BNC |
|
| ADVERTISED_BNC |
|
| ADVERTISED_FIBRE |
|
| ADVERTISED_FIBRE |
|
| ADVERTISED_FIBRE |
|
| ADVERTISED_FIBRE |
|
| ADVERTISED_MII |
|
| ADVERTISED_MII |
|
| ADVERTISED_MII |
|
| ADVERTISED_MII |
|
| ADVERTISED_TP |
|
| ADVERTISED_TP |
|
| ADVERTISED_TP |
|
| ADVERTISED_TP |
|
| aes.c |
|
| aes.c |
|
| aes.h |
|
| AES_BLOCKSIZE |
|
| aes_call_axtls |
Call AXTLS' AES_encrypt() or AES_decrypt() functions |
| aes_call_axtls |
Call AXTLS' AES_encrypt() or AES_decrypt() functions |
| AES_cbc_decrypt |
Decrypt a byte sequence (with a block size 16) using the AES cipher. |
| AES_cbc_decrypt |
Decrypt a byte sequence (with a block size 16) using the AES cipher. |
| AES_cbc_encrypt |
Encrypt a byte sequence (with a block size 16) using the AES cipher. |
| AES_cbc_encrypt |
Encrypt a byte sequence (with a block size 16) using the AES cipher. |
| aes_context |
|
| AES_convert_key |
Change a key for decryption. |
| AES_convert_key |
Change a key for decryption. |
| aes_decrypt |
Decrypt data |
| aes_decrypt |
Decrypt data |
| AES_decrypt |
Decrypt a single block (16 bytes) of data |
| AES_decrypt |
Decrypt a single block (16 bytes) of data |
| aes_encrypt |
Encrypt data |
| aes_encrypt |
Encrypt data |
| AES_encrypt |
Encrypt a single block (16 bytes) of data |
| AES_encrypt |
Encrypt a single block (16 bytes) of data |
| AES_set_key |
Set up AES with the key/iv and cipher size. |
| AES_set_key |
Set up AES with the key/iv and cipher size. |
| aes_setiv |
Set initialisation vector |
| aes_setiv |
Set initialisation vector |
| aes_setkey |
Set key |
| aes_setkey |
@file |
| aes_unwrap |
Unwrap a key or other data using AES Key Wrap (RFC 3394) |
| aes_wrap |
Wrap a key or other data using AES Key Wrap (RFC 3394) |
| aes_wrap.c |
|
| AES_xtime |
|
| AES_xtime |
|
| AF |
|
| AF_INET |
*< IPv4 Internet addresses |
| AF_INET6 |
*< IPv6 Internet addresses |
| AGGREGATE_WAIT_TIME |
|
| AGGREGATE_WAIT_TIME |
|
| AhdocPHYID0 |
|
| AhdocPHYID0 |
|
| alaska_init |
Alaska PHY |
| alaska_init |
Alaska PHY |
| alert |
Print alert message |
| alert.c |
|
| alert.c |
|
| ALERT_ROW |
|
| align |
|
| ALIGN |
Keep the LANCE happy... |
| ALIGN |
Keep the LANCE happy... |
| ALIGN_HIDDEN |
4kB page alignment should be enough |
| ALIGN_POINTER(Pointer, Alignment) |
|
| ALIGN_VALUE(Value, Alignment) |
|
| ALIGN_VARIABLE(Value) |
|
| ALIGN4 |
1 longword align |
| ALIGN4 |
1 longword align |
| ALIGN8 |
2 longword (quadword) align |
| ALIGN8 |
2 longword (quadword) align |
| ALL_MASK |
|
| ALL_MASK |
|
| alloc |
|
| alloc |
|
| alloc_etherdev |
Allocate Ethernet device |
| alloc_ibdev |
Infiniband device creation/destruction |
| alloc_image |
Allocate executable/loadable image |
| alloc_image |
Allocate executable/loadable image |
| alloc_iob |
@file |
| alloc_iob |
@file |
| alloc_ipoibdev |
Allocate IPoIB device |
| alloc_ipoibdev |
Allocate IPoIB device |
| alloc_memblock |
Allocate a memory block |
| alloc_memblock |
Allocate a memory block |
| alloc_netdev |
Allocate network device |
| alloc_output_file |
|
| alloc_rx |
|
| alloc_rx |
|
| alloca(size) |
|
| alloca.h |
|
| ALLOW_FDX |
|
| ALLOW_FDX |
|
| ALT_FORM |
|
| ALT_FORM |
|
| alta_offsets |
|
| alta_offsets |
|
| amd_mii_registers |
|
| amd_mii_registers |
|
| amd79c901_read_mode |
|
| amd79c901_read_mode |
|
| amd8111e.c |
|
| amd8111e.c |
|
| amd8111e.h |
|
| amd8111e.h |
|
| amd8111e_disable |
|
| amd8111e_disable |
|
| amd8111e_disable_interrupt |
|
| amd8111e_disable_interrupt |
|
| amd8111e_enable_interrupt |
|
| amd8111e_enable_interrupt |
|
| amd8111e_force_interrupt |
|
| amd8111e_force_interrupt |
|
| amd8111e_get_mac_address |
|
| amd8111e_get_mac_address |
|
| amd8111e_init_hw_default |
|
| amd8111e_init_hw_default |
|
| amd8111e_init_rx_ring |
|
| amd8111e_init_rx_ring |
|
| amd8111e_init_tx_ring |
|
| amd8111e_init_tx_ring |
|
| amd8111e_irq |
|
| amd8111e_irq |
|
| amd8111e_poll |
|
| amd8111e_poll |
|
| amd8111e_poll_link |
|
| amd8111e_poll_link |
|
| amd8111e_priv |
|
| amd8111e_priv |
|
| amd8111e_probe |
|
| amd8111e_probe |
|
| amd8111e_probe_ext_phy |
|
| amd8111e_probe_ext_phy |
|
| amd8111e_read_phy |
|
| amd8111e_read_phy |
|
| AMD8111E_REG_DUMP_LEN |
|
| AMD8111E_REG_DUMP_LEN |
|
| amd8111e_restart |
|
| amd8111e_restart |
|
| amd8111e_rx_desc |
|
| amd8111e_rx_desc |
|
| amd8111e_start |
|
| amd8111e_start |
|
| amd8111e_transmit |
Interface Functions * |
| amd8111e_transmit |
Interface Functions * |
| amd8111e_tx_desc |
|
| amd8111e_tx_desc |
|
| amd8111e_wait_link |
|
| amd8111e_wait_link |
|
| amd8111e_wait_tx_ring |
|
| amd8111e_wait_tx_ring |
|
| amd8111e_write_phy |
|
| amd8111e_write_phy |
|
| amd8111e_writeq(_UlData,_memMap) |
|
| amd8111e_writeq(_UlData,_memMap) |
|
| ANAPARAM_PWR0_MASK |
|
| ANAPARAM_PWR0_MASK |
|
| ANAPARAM_PWR0_SHIFT |
|
| ANAPARAM_PWR0_SHIFT |
|
| ANAPARAM_PWR1_MASK |
|
| ANAPARAM_PWR1_MASK |
|
| ANAPARAM_PWR1_SHIFT |
|
| ANAPARAM_PWR1_SHIFT |
|
| ANAPARAM_TXDACOFF_SHIFT |
|
| ANAPARAM_TXDACOFF_SHIFT |
|
| ANAR_10 |
|
| ANAR_10 |
|
| ANAR_10FD |
|
| ANAR_10FD |
|
| ANAR_ASMDIR |
Asymmetric PAUSE support |
| ANAR_ASMDIR |
Asymmetric PAUSE support |
| ANAR_PAUSE |
Symmetric PAUSE Support |
| ANAR_PAUSE |
Symmetric PAUSE Support |
| ANAR_T4 |
|
| ANAR_T4 |
|
| ANAR_TX |
|
| ANAR_TX |
|
| ANAR_TXFD |
|
| ANAR_TXFD |
|
| ANEG_DONE |
|
| ANEG_DONE |
|
| ANEG_FAILED |
|
| ANEG_FAILED |
|
| ANEG_OK |
|
| ANEG_OK |
|
| ANEG_STATE_SETTLE_TIME |
|
| ANEG_STATE_SETTLE_TIME |
|
| ANEG_TIMER_ENAB |
|
| ANEG_TIMER_ENAB |
|
| ANLPAR_10 |
|
| ANLPAR_10 |
|
| ANLPAR_10FD |
|
| ANLPAR_10FD |
|
| ANLPAR_ASMDIR |
Asymmetric PAUSE support |
| ANLPAR_ASMDIR |
Asymmetric PAUSE support |
| ANLPAR_PAUSE |
Symmetric PAUSE Support |
| ANLPAR_PAUSE |
Symmetric PAUSE Support |
| ANLPAR_T4 |
|
| ANLPAR_T4 |
|
| ANLPAR_TX |
|
| ANLPAR_TX |
|
| ANLPAR_TXFD |
|
| ANLPAR_TXFD |
|
| ansi_screen.c |
|
| ansiesc.c |
|
| ansiesc.c |
|
| ansiesc.h |
|
| ansiesc_call_handler |
@file |
| ansiesc_call_handler |
@file |
| ansiesc_context |
|
| ANSIESC_CUP |
|
| ANSIESC_ED |
|
| ANSIESC_ED_ALL |
|
| ANSIESC_ED_FROM_START |
|
| ANSIESC_ED_TO_END |
|
| ansiesc_handler |
|
| ANSIESC_MAX_PARAMS |
|
| ansiesc_process |
Process character that may be part of ANSI escape sequence |
| ansiesc_process |
Process character that may be part of ANSI escape sequence |
| ANSIESC_SGR |
|
| ansiscr_getc |
|
| ansiscr_movetoyx |
|
| ansiscr_peek |
|
| ansiscr_putc |
|
| ansiscr_reset |
|
| ANY_ISA_DMA |
|
| ANY_ISA_DMA |
|
| aoe.c |
|
| aoe.h |
|
| aoe_attach |
|
| AOE_CMD_ATA |
*< Issue ATA command |
| AOE_CMD_CONFIG |
*< Query Config Information |
| aoe_command |
Issue ATA command via an open AoE session |
| aoe_detach |
|
| aoe_detached_command |
|
| aoe_discover |
Issue AoE config query for AoE target discovery |
| aoe_done |
Mark current AoE command complete |
| AOE_ERR_BAD_COMMAND |
*< Unrecognised command code |
| AOE_ERR_BAD_PARAMETER |
*< Bad argument parameter |
| AOE_ERR_BAD_VERSION |
*< Unsupported version |
| AOE_ERR_CONFIG_EXISTS |
*< Config string present |
| AOE_ERR_UNAVAILABLE |
*< Device unavailable |
| AOE_FL_ASYNC |
*< Asynchronous write |
| AOE_FL_DEV_HEAD |
*< Device/head flag |
| AOE_FL_ERROR |
*< Command generated an error |
| AOE_FL_EXTENDED |
*< LBA48 extended addressing |
| AOE_FL_RESPONSE |
*< Message is a response |
| AOE_FL_WRITE |
*< Write command |
| aoe_free |
|
| AOE_MAJOR_BROADCAST |
|
| AOE_MAX_COUNT |
|
| AOE_MINOR_BROADCAST |
|
| aoe_parse_root_path |
|
| aoe_rx |
Process incoming AoE packets |
| aoe_rx_ata |
Handle AoE ATA command response |
| aoe_rx_cfg |
Handle AoE configuration command response |
| aoe_send_command |
Send AoE command |
| aoe_session |
|
| AOE_STATUS_ERR_MASK |
*< Error portion of status code |
| AOE_STATUS_PENDING |
*< Command pending |
| AOE_TAG_MAGIC |
|
| aoe_timer_expired |
Handle AoE retry timer expiry |
| AOE_VERSION |
*< Version 1 |
| AOE_VERSION_MASK |
*< Version part of ver_flags field |
| aoeata |
|
| aoeboot |
|
| aoeboot.c |
|
| aoecfg |
|
 aoecmd |
|
| aoehdr |
|
| aout_download |
|
| aout_freebsd_boot |
|
| aout_freebsd_probe |
|
| aout_loader.c |
|
| aout_probe |
|
| aout_state |
|
| AP_VALUE |
Auto-poll value register |
| AP_VALUE |
Auto-poll value register |
| AP_VALUE_BITS |
|
| AP_VALUE_BITS |
|
| api.h |
|
| apply_dns_settings |
Apply DNS settings |
| apply_iscsi_settings |
Apply iSCSI settings |
| apply_iscsi_string_setting |
Apply iSCSI setting |
| apply_settings |
Apply all settings |
| apply_settings |
Apply all settings |
| AR5K_2W_TX_DESC_CTL0_ANT_MODE_X |
|
| AR5K_2W_TX_DESC_CTL0_ANT_MODE_X |
|
| AR5K_2W_TX_DESC_CTL0_ANT_MODE_X |
|
| AR5K_2W_TX_DESC_CTL0_ANT_MODE_X |
|
| AR5K_2W_TX_DESC_CTL0_ANT_MODE_X |
|
| AR5K_2W_TX_DESC_CTL0_ANT_MODE_X |
|
| AR5K_2W_TX_DESC_CTL0_ANT_MODE_X |
|
| AR5K_2W_TX_DESC_CTL0_ANT_MODE_X |
|
| AR5K_2W_TX_DESC_CTL0_CLRDMASK |
|
| AR5K_2W_TX_DESC_CTL0_CLRDMASK |
|
| AR5K_2W_TX_DESC_CTL0_ENCRYPT_KE |
|
| AR5K_2W_TX_DESC_CTL0_ENCRYPT_KE |
|
| AR5K_2W_TX_DESC_CTL0_FRAME_LEN |
|
| AR5K_2W_TX_DESC_CTL0_FRAME_LEN |
|
| AR5K_2W_TX_DESC_CTL0_FRAME_TYPE |
[5210] |
| AR5K_2W_TX_DESC_CTL0_FRAME_TYPE |
|
| AR5K_2W_TX_DESC_CTL0_FRAME_TYPE |
[5210] |
| AR5K_2W_TX_DESC_CTL0_FRAME_TYPE |
|
| AR5K_2W_TX_DESC_CTL0_HEADER_LEN |
[5210 ?] |
| AR5K_2W_TX_DESC_CTL0_HEADER_LEN |
|
| AR5K_2W_TX_DESC_CTL0_HEADER_LEN |
[5210 ?] |
| AR5K_2W_TX_DESC_CTL0_HEADER_LEN |
|
| AR5K_2W_TX_DESC_CTL0_INTREQ |
|
| AR5K_2W_TX_DESC_CTL0_INTREQ |
|
| AR5K_2W_TX_DESC_CTL0_LONG_PACKE |
[5210] |
| AR5K_2W_TX_DESC_CTL0_LONG_PACKE |
[5210] |
| AR5K_2W_TX_DESC_CTL0_RTSENA |
|
| AR5K_2W_TX_DESC_CTL0_RTSENA |
|
| AR5K_2W_TX_DESC_CTL0_VEOL |
[5211] |
| AR5K_2W_TX_DESC_CTL0_VEOL |
[5211] |
| AR5K_2W_TX_DESC_CTL0_XMIT_RATE |
|
| AR5K_2W_TX_DESC_CTL0_XMIT_RATE |
|
| AR5K_2W_TX_DESC_CTL0_XMIT_RATE_ |
|
| AR5K_2W_TX_DESC_CTL0_XMIT_RATE_ |
|
| AR5K_2W_TX_DESC_CTL1_BUF_LEN |
|
| AR5K_2W_TX_DESC_CTL1_BUF_LEN |
|
| AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE |
|
| AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE |
|
| AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE |
|
| AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE |
|
| AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE |
|
| AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE |
|
| AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE |
|
| AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE |
|
| AR5K_2W_TX_DESC_CTL1_FRAME_TYPE |
[5211] |
| AR5K_2W_TX_DESC_CTL1_FRAME_TYPE |
|
| AR5K_2W_TX_DESC_CTL1_FRAME_TYPE |
[5211] |
| AR5K_2W_TX_DESC_CTL1_FRAME_TYPE |
|
| AR5K_2W_TX_DESC_CTL1_MORE |
|
| AR5K_2W_TX_DESC_CTL1_MORE |
|
| AR5K_2W_TX_DESC_CTL1_NOACK |
[5211] |
| AR5K_2W_TX_DESC_CTL1_NOACK |
[5211] |
| AR5K_2W_TX_DESC_CTL1_RTS_DURATI |
[5210 ?] |
| AR5K_2W_TX_DESC_CTL1_RTS_DURATI |
[5210 ?] |
| AR5K_5210_RX_DESC_STATUS0_DATA_ |
|
| AR5K_5210_RX_DESC_STATUS0_DATA_ |
|
| AR5K_5210_RX_DESC_STATUS0_MORE |
|
| AR5K_5210_RX_DESC_STATUS0_MORE |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS0_RECEI |
|
| AR5K_5210_RX_DESC_STATUS1_CRC_E |
|
| AR5K_5210_RX_DESC_STATUS1_CRC_E |
|
| AR5K_5210_RX_DESC_STATUS1_DECRY |
|
| AR5K_5210_RX_DESC_STATUS1_DECRY |
|
| AR5K_5210_RX_DESC_STATUS1_DONE |
|
| AR5K_5210_RX_DESC_STATUS1_DONE |
|
| AR5K_5210_RX_DESC_STATUS1_FIFO_ |
|
| AR5K_5210_RX_DESC_STATUS1_FIFO_ |
|
| AR5K_5210_RX_DESC_STATUS1_FRAME |
|
| AR5K_5210_RX_DESC_STATUS1_FRAME |
|
| AR5K_5210_RX_DESC_STATUS1_KEY_C |
|
| AR5K_5210_RX_DESC_STATUS1_KEY_C |
|
| AR5K_5210_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5210_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5210_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5210_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5210_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5210_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5210_RX_DESC_STATUS1_PHY_E |
|
| AR5K_5210_RX_DESC_STATUS1_PHY_E |
|
| AR5K_5210_RX_DESC_STATUS1_PHY_E |
|
| AR5K_5210_RX_DESC_STATUS1_PHY_E |
|
| AR5K_5210_RX_DESC_STATUS1_RECEI |
|
| AR5K_5210_RX_DESC_STATUS1_RECEI |
|
| AR5K_5210_RX_DESC_STATUS1_RECEI |
|
| AR5K_5210_RX_DESC_STATUS1_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_DATA_ |
|
| AR5K_5212_RX_DESC_STATUS0_DATA_ |
|
| AR5K_5212_RX_DESC_STATUS0_DECOM |
|
| AR5K_5212_RX_DESC_STATUS0_DECOM |
|
| AR5K_5212_RX_DESC_STATUS0_MORE |
|
| AR5K_5212_RX_DESC_STATUS0_MORE |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS0_RECEI |
|
| AR5K_5212_RX_DESC_STATUS1_CRC_E |
|
| AR5K_5212_RX_DESC_STATUS1_CRC_E |
|
| AR5K_5212_RX_DESC_STATUS1_DECRY |
|
| AR5K_5212_RX_DESC_STATUS1_DECRY |
|
| AR5K_5212_RX_DESC_STATUS1_DONE |
|
| AR5K_5212_RX_DESC_STATUS1_DONE |
|
| AR5K_5212_RX_DESC_STATUS1_FRAME |
|
| AR5K_5212_RX_DESC_STATUS1_FRAME |
|
| AR5K_5212_RX_DESC_STATUS1_KEY_C |
|
| AR5K_5212_RX_DESC_STATUS1_KEY_C |
|
| AR5K_5212_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5212_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5212_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5212_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5212_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5212_RX_DESC_STATUS1_KEY_I |
|
| AR5K_5212_RX_DESC_STATUS1_MIC_E |
|
| AR5K_5212_RX_DESC_STATUS1_MIC_E |
|
| AR5K_5212_RX_DESC_STATUS1_PHY_E |
|
| AR5K_5212_RX_DESC_STATUS1_PHY_E |
|
| AR5K_5212_RX_DESC_STATUS1_RECEI |
|
| AR5K_5212_RX_DESC_STATUS1_RECEI |
|
| AR5K_5212_RX_DESC_STATUS1_RECEI |
|
| AR5K_5212_RX_DESC_STATUS1_RECEI |
|
| AR5K_5414_CBCFG |
|
| AR5K_5414_CBCFG |
|
| AR5K_5414_CBCFG_BUF_DIS |
Disable buffer |
| AR5K_5414_CBCFG_BUF_DIS |
Disable buffer |
| AR5K_ACK_FAIL |
|
| AR5K_ACK_FAIL |
|
| AR5K_ACK_FAIL_5210 |
|
| AR5K_ACK_FAIL_5210 |
|
| AR5K_ACK_FAIL_5211 |
|
| AR5K_ACK_FAIL_5211 |
|
| AR5K_ACKSIFS |
Register Address |
| AR5K_ACKSIFS |
Register Address |
| AR5K_ACKSIFS_INC |
ACK SIFS Increment (field) |
| AR5K_ACKSIFS_INC |
ACK SIFS Increment (field) |
| AR5K_ADDAC_TEST |
Register Address |
| AR5K_ADDAC_TEST |
Register Address |
| AR5K_ADDAC_TEST_CAPTURE |
Begin capture |
| AR5K_ADDAC_TEST_CAPTURE |
Begin capture |
| AR5K_ADDAC_TEST_LOOP_EN |
Enable loop |
| AR5K_ADDAC_TEST_LOOP_EN |
Enable loop |
| AR5K_ADDAC_TEST_LOOP_LEN |
Loop length (field) |
| AR5K_ADDAC_TEST_LOOP_LEN |
Loop length (field) |
| AR5K_ADDAC_TEST_MSB |
State of MSB |
| AR5K_ADDAC_TEST_MSB |
State of MSB |
| AR5K_ADDAC_TEST_RXCONT |
Continuous capture |
| AR5K_ADDAC_TEST_RXCONT |
Continuous capture |
| AR5K_ADDAC_TEST_TRIG_PTY |
Trigger polarity |
| AR5K_ADDAC_TEST_TRIG_PTY |
Trigger polarity |
| AR5K_ADDAC_TEST_TRIG_SEL |
Trigger select |
| AR5K_ADDAC_TEST_TRIG_SEL |
Trigger select |
| AR5K_ADDAC_TEST_TST_ARM |
ARM rx buffer for capture |
| AR5K_ADDAC_TEST_TST_ARM |
ARM rx buffer for capture |
| AR5K_ADDAC_TEST_TST_MODE |
Test mode |
| AR5K_ADDAC_TEST_TST_MODE |
Test mode |
| AR5K_ADDAC_TEST_TXCONT |
Test continuous tx |
| AR5K_ADDAC_TEST_TXCONT |
Test continuous tx |
| AR5K_ADDAC_TEST_USE_U8 |
Use upper 8 bits |
| AR5K_ADDAC_TEST_USE_U8 |
Use upper 8 bits |
| AR5K_AR5210_TX_DESC_FRAME_TYPE_ |
|
| AR5K_AR5210_TX_DESC_FRAME_TYPE_ |
|
| AR5K_AR5210_TX_DESC_FRAME_TYPE_ |
|
| AR5K_AR5210_TX_DESC_FRAME_TYPE_ |
|
| AR5K_AR5210_TX_DESC_FRAME_TYPE_ |
|
| AR5K_AR5210_TX_DESC_FRAME_TYPE_ |
|
| AR5K_AR5210_TX_DESC_FRAME_TYPE_ |
|
| AR5K_AR5210_TX_DESC_FRAME_TYPE_ |
|
| AR5K_AR5210_TX_DESC_FRAME_TYPE_ |
|
| AR5K_AR5210_TX_DESC_FRAME_TYPE_ |
|
| AR5K_ASSERT_ENTRY(_e, _s) |
|
| AR5K_ASSERT_ENTRY(_e, _s) |
|
| AR5K_BACKOFF |
Register Address [5210] |
| AR5K_BACKOFF |
Register Address [5210] |
| AR5K_BACKOFF_CNT |
Backoff count (?) |
| AR5K_BACKOFF_CNT |
Backoff count (?) |
| AR5K_BACKOFF_CW |
Backoff Contention Window (?) |
| AR5K_BACKOFF_CW |
Backoff Contention Window (?) |
| AR5K_BB_GAIN(_n) |
|
| AR5K_BB_GAIN(_n) |
|
| AR5K_BB_GAIN_BASE |
BaseBand Amplifier Gain table base address |
| AR5K_BB_GAIN_BASE |
BaseBand Amplifier Gain table base address |
| AR5K_BCR |
Register Address |
| AR5K_BCR |
Register Address |
| AR5K_BCR_ADHOC |
Ad-Hoc mode |
| AR5K_BCR_ADHOC |
Ad-Hoc mode |
| AR5K_BCR_AP |
AP mode |
| AR5K_BCR_AP |
AP mode |
| AR5K_BCR_BCGET |
|
| AR5K_BCR_BCGET |
|
| AR5K_BCR_BDMAE |
DMA enable |
| AR5K_BCR_BDMAE |
DMA enable |
| AR5K_BCR_TQ1FV |
Use Queue1 for CAB traffic |
| AR5K_BCR_TQ1FV |
Use Queue1 for CAB traffic |
| AR5K_BCR_TQ1V |
Use Queue1 for Beacon traffic |
| AR5K_BCR_TQ1V |
Use Queue1 for Beacon traffic |
| AR5K_BEACON |
|
| AR5K_BEACON |
|
| AR5K_BEACON_5210 |
Register Address [5210] |
| AR5K_BEACON_5210 |
Register Address [5210] |
| AR5K_BEACON_5211 |
Register Address [5211+] |
| AR5K_BEACON_5211 |
Register Address [5211+] |
| AR5K_BEACON_CNT |
|
| AR5K_BEACON_CNT |
|
| AR5K_BEACON_CNT_5210 |
|
| AR5K_BEACON_CNT_5210 |
|
| AR5K_BEACON_CNT_5211 |
|
| AR5K_BEACON_CNT_5211 |
|
| AR5K_BEACON_ENABLE |
Enable beacons |
| AR5K_BEACON_ENABLE |
Enable beacons |
| AR5K_BEACON_PERIOD |
Mask for beacon period |
| AR5K_BEACON_PERIOD |
Mask for beacon period |
| AR5K_BEACON_PERIOD_S |
|
| AR5K_BEACON_PERIOD_S |
|
| AR5K_BEACON_RESET_TSF |
Force TSF reset |
| AR5K_BEACON_RESET_TSF |
Force TSF reset |
| AR5K_BEACON_TIM |
Mask for TIM offset |
| AR5K_BEACON_TIM |
Mask for TIM offset |
| AR5K_BEACON_TIM_S |
|
| AR5K_BEACON_TIM_S |
|
| AR5K_BSR |
Register Address |
| AR5K_BSR |
Register Address |
| AR5K_BSR_ATIMDLY |
ATIM delay (?) |
| AR5K_BSR_ATIMDLY |
ATIM delay (?) |
| AR5K_BSR_BDLYDMA |
DMA Beacon delay (?) |
| AR5K_BSR_BDLYDMA |
DMA Beacon delay (?) |
| AR5K_BSR_BDLYSW |
SW Beacon delay (?) |
| AR5K_BSR_BDLYSW |
SW Beacon delay (?) |
| AR5K_BSR_SNAPSHOTSVALID |
BCR snapshots are valid (?) |
| AR5K_BSR_SNAPSHOTSVALID |
BCR snapshots are valid (?) |
| AR5K_BSR_SNPADHOC |
Ad-hoc mode set (?) |
| AR5K_BSR_SNPADHOC |
Ad-hoc mode set (?) |
| AR5K_BSR_SNPBDMAE |
Beacon DMA enabled (?) |
| AR5K_BSR_SNPBDMAE |
Beacon DMA enabled (?) |
| AR5K_BSR_SNPTQ1FV |
Queue1 is used for CAB traffic (?) |
| AR5K_BSR_SNPTQ1FV |
Queue1 is used for CAB traffic (?) |
| AR5K_BSR_SNPTQ1V |
Queue1 is used for Beacon traffic (?) |
| AR5K_BSR_SNPTQ1V |
Queue1 is used for Beacon traffic (?) |
| AR5K_BSR_SWBA_CNT |
|
| AR5K_BSR_SWBA_CNT |
|
| AR5K_BSR_TXQ1F |
Beacon queue (1) finished |
| AR5K_BSR_TXQ1F |
Beacon queue (1) finished |
| AR5K_BSS_ID0 |
|
| AR5K_BSS_ID0 |
|
| AR5K_BSS_ID1 |
|
| AR5K_BSS_ID1 |
|
| AR5K_BSS_ID1_AID |
|
| AR5K_BSS_ID1_AID |
|
| AR5K_BSS_ID1_AID_S |
|
| AR5K_BSS_ID1_AID_S |
|
| AR5K_BSS_IDM0 |
Upper bits |
| AR5K_BSS_IDM0 |
Upper bits |
| AR5K_BSS_IDM1 |
Lower bits |
| AR5K_BSS_IDM1 |
Lower bits |
| AR5K_CCFG |
Register Address |
| AR5K_CCFG |
Register Address |
| AR5K_CCFG_CCU |
Register Address |
| AR5K_CCFG_CCU |
Register Address |
| AR5K_CCFG_CCU_CD_THRES |
CCU Cyc(lic?) debt threshold (field) |
| AR5K_CCFG_CCU_CD_THRES |
CCU Cyc(lic?) debt threshold (field) |
| AR5K_CCFG_CCU_CREDIT |
CCU Credit (field) |
| AR5K_CCFG_CCU_CREDIT |
CCU Credit (field) |
| AR5K_CCFG_CCU_CUP_EN |
CCU Catchup enable |
| AR5K_CCFG_CCU_CUP_EN |
CCU Catchup enable |
| AR5K_CCFG_CCU_CUP_LCNT |
CCU Catchup lit(?) count |
| AR5K_CCFG_CCU_CUP_LCNT |
CCU Catchup lit(?) count |
| AR5K_CCFG_CCU_INIT |
Initial value during reset |
| AR5K_CCFG_CCU_INIT |
Initial value during reset |
| AR5K_CCFG_CPC_EN |
Enable performance counters |
| AR5K_CCFG_CPC_EN |
Enable performance counters |
| AR5K_CCFG_WINDOW_SIZE |
Compression window size |
| AR5K_CCFG_WINDOW_SIZE |
Compression window size |
| AR5K_CCK_FIL_CNT |
|
| AR5K_CCK_FIL_CNT |
|
| AR5K_CFG |
Register Address |
| AR5K_CFG |
Register Address |
| AR5K_CFG_CLKGD |
Clock gated (Disable dynamic clock) |
| AR5K_CFG_CLKGD |
Clock gated (Disable dynamic clock) |
| AR5K_CFG_EEBS |
EEPROM is busy |
| AR5K_CFG_EEBS |
EEPROM is busy |
| AR5K_CFG_IBSS |
0-BSS, 1-IBSS [5211+] |
| AR5K_CFG_IBSS |
0-BSS, 1-IBSS [5211+] |
| AR5K_CFG_PCI_THRES |
PCI Master req q threshold [5211+] |
| AR5K_CFG_PCI_THRES |
PCI Master req q threshold [5211+] |
| AR5K_CFG_PCI_THRES_S |
|
| AR5K_CFG_PCI_THRES_S |
|
| AR5K_CFG_PHY_OK |
[5211+] |
| AR5K_CFG_PHY_OK |
[5211+] |
| AR5K_CFG_SWRB |
Byte-swap RX buffer |
| AR5K_CFG_SWRB |
Byte-swap RX buffer |
| AR5K_CFG_SWRD |
Byte-swap RX descriptor |
| AR5K_CFG_SWRD |
Byte-swap RX descriptor |
| AR5K_CFG_SWRG |
Byte-swap Register access |
| AR5K_CFG_SWRG |
Byte-swap Register access |
| AR5K_CFG_SWTB |
Byte-swap TX buffer |
| AR5K_CFG_SWTB |
Byte-swap TX buffer |
| AR5K_CFG_SWTD |
Byte-swap TX descriptor (for big endian archs) |
| AR5K_CFG_SWTD |
Byte-swap TX descriptor (for big endian archs) |
| AR5K_CFG_TXCNT |
Tx frame count (?) [5210] |
| AR5K_CFG_TXCNT |
Tx frame count (?) [5210] |
| AR5K_CFG_TXCNT_S |
|
| AR5K_CFG_TXCNT_S |
|
| AR5K_CFG_TXFSTAT |
Tx frame status (?) [5210] |
| AR5K_CFG_TXFSTAT |
Tx frame status (?) [5210] |
| AR5K_CFG_TXFSTRT |
[5210] |
| AR5K_CFG_TXFSTRT |
[5210] |
| AR5K_CFP_DUR |
|
| AR5K_CFP_DUR |
|
| AR5K_CFP_DUR_5210 |
|
| AR5K_CFP_DUR_5210 |
|
| AR5K_CFP_DUR_5211 |
|
| AR5K_CFP_DUR_5211 |
|
| AR5K_CFP_PERIOD |
|
| AR5K_CFP_PERIOD |
|
| AR5K_CFP_PERIOD_5210 |
|
| AR5K_CFP_PERIOD_5210 |
|
| AR5K_CFP_PERIOD_5211 |
|
| AR5K_CFP_PERIOD_5211 |
|
| AR5K_CLR_TMASK |
|
| AR5K_CLR_TMASK |
|
| AR5K_CPC0 |
Compression performance counter 0 |
| AR5K_CPC0 |
Compression performance counter 0 |
| AR5K_CPC1 |
Compression performance counter 1 |
| AR5K_CPC1 |
Compression performance counter 1 |
| AR5K_CPC2 |
Compression performance counter 2 |
| AR5K_CPC2 |
Compression performance counter 2 |
| AR5K_CPC3 |
Compression performance counter 3 |
| AR5K_CPC3 |
Compression performance counter 3 |
| AR5K_CPCOVF |
Compression performance overflow |
| AR5K_CPCOVF |
Compression performance overflow |
| AR5K_CR |
Register Address |
| AR5K_CR |
Register Address |
| AR5K_CR_RXD |
RX Disable |
| AR5K_CR_RXD |
RX Disable |
| AR5K_CR_RXE |
RX Enable |
| AR5K_CR_RXE |
RX Enable |
| AR5K_CR_SWI |
Software Interrupt |
| AR5K_CR_SWI |
Software Interrupt |
| AR5K_CR_TXD0 |
TX Disable for queue 0 on 5210 |
| AR5K_CR_TXD0 |
TX Disable for queue 0 on 5210 |
| AR5K_CR_TXD1 |
TX Disable for queue 1 on 5210 |
| AR5K_CR_TXD1 |
TX Disable for queue 1 on 5210 |
| AR5K_CR_TXE0 |
TX Enable for queue 0 on 5210 |
| AR5K_CR_TXE0 |
TX Enable for queue 0 on 5210 |
| AR5K_CR_TXE1 |
TX Enable for queue 1 on 5210 |
| AR5K_CR_TXE1 |
TX Enable for queue 1 on 5210 |
| AR5K_CTL_CUSTOM |
|
| AR5K_CTL_CUSTOM |
|
| AR5K_CTL_ETSI |
|
| AR5K_CTL_ETSI |
|
| AR5K_CTL_FCC |
|
| AR5K_CTL_FCC |
|
| AR5K_CTL_MKK |
|
| AR5K_CTL_MKK |
|
| AR5K_CTL_NO_CTL |
|
| AR5K_CTL_NO_CTL |
|
| AR5K_CTL_NO_REGDOMAIN |
|
| AR5K_CTL_NO_REGDOMAIN |
|
| AR5K_DB2RATE(_n) |
|
| AR5K_DB2RATE(_n) |
|
| AR5K_DB2RATE_BASE |
|
| AR5K_DB2RATE_BASE |
|
| AR5K_DCCFG |
Register Address |
| AR5K_DCCFG |
Register Address |
| AR5K_DCCFG_BCAST_EN |
Enable decompression for bcast frames |
| AR5K_DCCFG_BCAST_EN |
Enable decompression for bcast frames |
| AR5K_DCCFG_BYPASS_EN |
Bypass decompression |
| AR5K_DCCFG_BYPASS_EN |
Bypass decompression |
| AR5K_DCCFG_GLOBAL_EN |
Enable decompression on all queues |
| AR5K_DCCFG_GLOBAL_EN |
Enable decompression on all queues |
| AR5K_DCCFG_MCAST_EN |
Enable decompression for mcast frames |
| AR5K_DCCFG_MCAST_EN |
Enable decompression for mcast frames |
| AR5K_DCM_ADDR |
Decompression mask address (index) |
| AR5K_DCM_ADDR |
Decompression mask address (index) |
| AR5K_DCM_DATA |
Decompression mask data |
| AR5K_DCM_DATA |
Decompression mask data |
| AR5K_DCU_CHAN_TIME_BASE |
Register Address -Queue0 DCU_CHAN_TIME |
| AR5K_DCU_CHAN_TIME_BASE |
Register Address -Queue0 DCU_CHAN_TIME |
| AR5K_DCU_CHAN_TIME_DUR |
Channel time duration |
| AR5K_DCU_CHAN_TIME_DUR |
Channel time duration |
| AR5K_DCU_CHAN_TIME_DUR_S |
|
| AR5K_DCU_CHAN_TIME_DUR_S |
|
| AR5K_DCU_CHAN_TIME_ENABLE |
Enable channel time |
| AR5K_DCU_CHAN_TIME_ENABLE |
Enable channel time |
| AR5K_DCU_FP |
Register Address |
| AR5K_DCU_FP |
Register Address |
| AR5K_DCU_FP_BURST_DCU_EN |
Enable burst prefetch on DCU (?) |
| AR5K_DCU_FP_BURST_DCU_EN |
Enable burst prefetch on DCU (?) |
| AR5K_DCU_FP_NOBURST_DCU_EN |
Enable non-burst prefetch on DCU (?) |
| AR5K_DCU_FP_NOBURST_DCU_EN |
Enable non-burst prefetch on DCU (?) |
| AR5K_DCU_FP_NOBURST_EN |
Enable non-burst prefetch (?) |
| AR5K_DCU_FP_NOBURST_EN |
Enable non-burst prefetch (?) |
| AR5K_DCU_GBL_IFS_EIFS |
|
| AR5K_DCU_GBL_IFS_EIFS |
|
| AR5K_DCU_GBL_IFS_EIFS_M |
|
| AR5K_DCU_GBL_IFS_EIFS_M |
|
| AR5K_DCU_GBL_IFS_MISC |
Register Address |
| AR5K_DCU_GBL_IFS_MISC |
Register Address |
| AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_ |
AIFS cnt reset policy (?) |
| AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_ |
AIFS cnt reset policy (?) |
| AR5K_DCU_GBL_IFS_MISC_DCU_ARB_D |
DCU Arbiter delay mask |
| AR5K_DCU_GBL_IFS_MISC_DCU_ARB_D |
DCU Arbiter delay mask |
| AR5K_DCU_GBL_IFS_MISC_LFSR_SLIC |
LFSR Slice Select |
| AR5K_DCU_GBL_IFS_MISC_LFSR_SLIC |
LFSR Slice Select |
| AR5K_DCU_GBL_IFS_MISC_RND_LFSR_ |
Disable random LFSR slice |
| AR5K_DCU_GBL_IFS_MISC_RND_LFSR_ |
Disable random LFSR slice |
| AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_ |
SIFS cnt reset policy (?) |
| AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_ |
SIFS cnt reset policy (?) |
| AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_ |
SIFS Duration mask |
| AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_ |
SIFS Duration mask |
| AR5K_DCU_GBL_IFS_MISC_TURBO_MOD |
Turbo mode |
| AR5K_DCU_GBL_IFS_MISC_TURBO_MOD |
Turbo mode |
| AR5K_DCU_GBL_IFS_MISC_USEC_DUR |
USEC Duration mask |
| AR5K_DCU_GBL_IFS_MISC_USEC_DUR |
USEC Duration mask |
| AR5K_DCU_GBL_IFS_MISC_USEC_DUR_ |
|
| AR5K_DCU_GBL_IFS_MISC_USEC_DUR_ |
|
| AR5K_DCU_GBL_IFS_SIFS |
|
| AR5K_DCU_GBL_IFS_SIFS |
|
| AR5K_DCU_GBL_IFS_SIFS_M |
|
| AR5K_DCU_GBL_IFS_SIFS_M |
|
| AR5K_DCU_GBL_IFS_SLOT |
|
| AR5K_DCU_GBL_IFS_SLOT |
|
| AR5K_DCU_GBL_IFS_SLOT_M |
|
| AR5K_DCU_GBL_IFS_SLOT_M |
|
| AR5K_DCU_LCL_IFS_AIFS |
Arbitrated Interframe Space |
| AR5K_DCU_LCL_IFS_AIFS |
Arbitrated Interframe Space |
| AR5K_DCU_LCL_IFS_AIFS_MAX |
Anything above that can cause DCU to hang |
| AR5K_DCU_LCL_IFS_AIFS_MAX |
Anything above that can cause DCU to hang |
| AR5K_DCU_LCL_IFS_AIFS_S |
|
| AR5K_DCU_LCL_IFS_AIFS_S |
|
| AR5K_DCU_LCL_IFS_BASE |
Register Address -Queue0 DCU_LCL_IFS |
| AR5K_DCU_LCL_IFS_BASE |
Register Address -Queue0 DCU_LCL_IFS |
| AR5K_DCU_LCL_IFS_CW_MAX |
Maximum Contention Window |
| AR5K_DCU_LCL_IFS_CW_MAX |
Maximum Contention Window |
| AR5K_DCU_LCL_IFS_CW_MAX_S |
|
| AR5K_DCU_LCL_IFS_CW_MAX_S |
|
| AR5K_DCU_LCL_IFS_CW_MIN |
Minimum Contention Window |
| AR5K_DCU_LCL_IFS_CW_MIN |
Minimum Contention Window |
| AR5K_DCU_LCL_IFS_CW_MIN_S |
|
| AR5K_DCU_LCL_IFS_CW_MIN_S |
|
| AR5K_DCU_MISC_ARBLOCK_CTL |
Arbiter lockout control mask |
| AR5K_DCU_MISC_ARBLOCK_CTL |
Arbiter lockout control mask |
| AR5K_DCU_MISC_ARBLOCK_CTL_GLOBA |
Global lockout |
| AR5K_DCU_MISC_ARBLOCK_CTL_GLOBA |
Global lockout |
| AR5K_DCU_MISC_ARBLOCK_CTL_INTFR |
Intra-frame lockout |
| AR5K_DCU_MISC_ARBLOCK_CTL_INTFR |
Intra-frame lockout |
| AR5K_DCU_MISC_ARBLOCK_CTL_NONE |
No arbiter lockout |
| AR5K_DCU_MISC_ARBLOCK_CTL_NONE |
No arbiter lockout |
| AR5K_DCU_MISC_ARBLOCK_CTL_S |
|
| AR5K_DCU_MISC_ARBLOCK_CTL_S |
|
| AR5K_DCU_MISC_ARBLOCK_IGNORE |
Ignore Arbiter lockout |
| AR5K_DCU_MISC_ARBLOCK_IGNORE |
Ignore Arbiter lockout |
| AR5K_DCU_MISC_BACKOFF |
Mask for backoff threshold |
| AR5K_DCU_MISC_BACKOFF |
Mask for backoff threshold |
| AR5K_DCU_MISC_BACKOFF_FRAG |
Enable backoff while bursting |
| AR5K_DCU_MISC_BACKOFF_FRAG |
Enable backoff while bursting |
| AR5K_DCU_MISC_BACKOFF_PERSIST |
Persistent backoff |
| AR5K_DCU_MISC_BACKOFF_PERSIST |
Persistent backoff |
| AR5K_DCU_MISC_BASE |
Register Address -Queue0 DCU_MISC |
| AR5K_DCU_MISC_BASE |
Register Address -Queue0 DCU_MISC |
| AR5K_DCU_MISC_BCN_ENABLE |
Enable Beacon use |
| AR5K_DCU_MISC_BCN_ENABLE |
Enable Beacon use |
| AR5K_DCU_MISC_BLOWN_IFS_POLICY |
Blown IFS policy (?) |
| AR5K_DCU_MISC_BLOWN_IFS_POLICY |
Blown IFS policy (?) |
| AR5K_DCU_MISC_ETS_CW_POL |
End of transmission series |
| AR5K_DCU_MISC_ETS_CW_POL |
End of transmission series |
| AR5K_DCU_MISC_ETS_RTS_POL |
End of transmission series |
| AR5K_DCU_MISC_ETS_RTS_POL |
End of transmission series |
| AR5K_DCU_MISC_FRAG_WAIT |
Wait for next fragment |
| AR5K_DCU_MISC_FRAG_WAIT |
Wait for next fragment |
| AR5K_DCU_MISC_FRMPRFTCH_ENABLE |
Enable frame pre-fetch |
| AR5K_DCU_MISC_FRMPRFTCH_ENABLE |
Enable frame pre-fetch |
| AR5K_DCU_MISC_HCFPOLL_ENABLE |
CF - Poll enable |
| AR5K_DCU_MISC_HCFPOLL_ENABLE |
CF - Poll enable |
| AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
Disable post-frame backoff |
| AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
Disable post-frame backoff |
| AR5K_DCU_MISC_SEQ_NUM_INCR_DIS |
Disable sequence number increment |
| AR5K_DCU_MISC_SEQ_NUM_INCR_DIS |
Disable sequence number increment |
| AR5K_DCU_MISC_SEQNUM_CTL |
Sequence number control (?) |
| AR5K_DCU_MISC_SEQNUM_CTL |
Sequence number control (?) |
| AR5K_DCU_MISC_VIRT_COLL_POLICY |
Virtual Collision cw policy |
| AR5K_DCU_MISC_VIRT_COLL_POLICY |
Virtual Collision cw policy |
| AR5K_DCU_MISC_VIRTCOL |
Mask for Virtual Collision (?) |
| AR5K_DCU_MISC_VIRTCOL |
Mask for Virtual Collision (?) |
| AR5K_DCU_MISC_VIRTCOL_IGNORE |
|
| AR5K_DCU_MISC_VIRTCOL_IGNORE |
|
| AR5K_DCU_MISC_VIRTCOL_NORMAL |
|
| AR5K_DCU_MISC_VIRTCOL_NORMAL |
|
| AR5K_DCU_QCUMASK_BASE |
Register Address -Queue0 DCU_QCUMASK |
| AR5K_DCU_QCUMASK_BASE |
Register Address -Queue0 DCU_QCUMASK |
| AR5K_DCU_QCUMASK_M |
|
| AR5K_DCU_QCUMASK_M |
|
| AR5K_DCU_RETRY_LMT_BASE |
Register Address -Queue0 DCU_RETRY_LMT |
| AR5K_DCU_RETRY_LMT_BASE |
Register Address -Queue0 DCU_RETRY_LMT |
| AR5K_DCU_RETRY_LMT_LG_RETRY |
Long retry limit mask |
| AR5K_DCU_RETRY_LMT_LG_RETRY |
Long retry limit mask |
| AR5K_DCU_RETRY_LMT_LG_RETRY_S |
|
| AR5K_DCU_RETRY_LMT_LG_RETRY_S |
|
| AR5K_DCU_RETRY_LMT_SH_RETRY |
Short retry limit mask |
| AR5K_DCU_RETRY_LMT_SH_RETRY |
Short retry limit mask |
| AR5K_DCU_RETRY_LMT_SH_RETRY_S |
|
| AR5K_DCU_RETRY_LMT_SH_RETRY_S |
|
| AR5K_DCU_RETRY_LMT_SLG_RETRY |
Station long retry limit mask (?) |
| AR5K_DCU_RETRY_LMT_SLG_RETRY |
Station long retry limit mask (?) |
| AR5K_DCU_RETRY_LMT_SLG_RETRY_S |
|
| AR5K_DCU_RETRY_LMT_SLG_RETRY_S |
|
| AR5K_DCU_RETRY_LMT_SSH_RETRY |
Station short retry limit mask (?) |
| AR5K_DCU_RETRY_LMT_SSH_RETRY |
Station short retry limit mask (?) |
| AR5K_DCU_RETRY_LMT_SSH_RETRY_S |
|
| AR5K_DCU_RETRY_LMT_SSH_RETRY_S |
|
| AR5K_DCU_SEQNUM_BASE |
|
| AR5K_DCU_SEQNUM_BASE |
|
| AR5K_DCU_SEQNUM_M |
|
| AR5K_DCU_SEQNUM_M |
|
| AR5K_DCU_TX_FILTER_0(_n) |
|
| AR5K_DCU_TX_FILTER_0(_n) |
|
| AR5K_DCU_TX_FILTER_0_BASE |
|
| AR5K_DCU_TX_FILTER_0_BASE |
|
| AR5K_DCU_TX_FILTER_1(_n) |
|
| AR5K_DCU_TX_FILTER_1(_n) |
|
| AR5K_DCU_TX_FILTER_1_BASE |
|
| AR5K_DCU_TX_FILTER_1_BASE |
|
| AR5K_DCU_TX_FILTER_CLR |
|
| AR5K_DCU_TX_FILTER_CLR |
|
| AR5K_DCU_TX_FILTER_SET |
|
| AR5K_DCU_TX_FILTER_SET |
|
| AR5K_DCU_TXP |
Register Address |
| AR5K_DCU_TXP |
Register Address |
| AR5K_DCU_TXP_M |
Tx pause mask |
| AR5K_DCU_TXP_M |
Tx pause mask |
| AR5K_DCU_TXP_STATUS |
Tx pause status |
| AR5K_DCU_TXP_STATUS |
Tx pause status |
| AR5K_DEFAULT_ANTENNA |
|
| AR5K_DEFAULT_ANTENNA |
|
| AR5K_DESC_RX_CTL0 |
|
| AR5K_DESC_RX_CTL0 |
|
| AR5K_DESC_RX_CTL1_BUF_LEN |
|
| AR5K_DESC_RX_CTL1_BUF_LEN |
|
| AR5K_DESC_RX_CTL1_INTREQ |
|
| AR5K_DESC_RX_CTL1_INTREQ |
|
| AR5K_DESC_RX_PHY_ERROR_64QAM |
|
| AR5K_DESC_RX_PHY_ERROR_64QAM |
|
| AR5K_DESC_RX_PHY_ERROR_LENGTH |
|
| AR5K_DESC_RX_PHY_ERROR_LENGTH |
|
| AR5K_DESC_RX_PHY_ERROR_NONE |
|
| AR5K_DESC_RX_PHY_ERROR_NONE |
|
| AR5K_DESC_RX_PHY_ERROR_PARITY |
|
| AR5K_DESC_RX_PHY_ERROR_PARITY |
|
| AR5K_DESC_RX_PHY_ERROR_RATE |
|
| AR5K_DESC_RX_PHY_ERROR_RATE |
|
| AR5K_DESC_RX_PHY_ERROR_SERVICE |
|
| AR5K_DESC_RX_PHY_ERROR_SERVICE |
|
| AR5K_DESC_RX_PHY_ERROR_TIMING |
|
| AR5K_DESC_RX_PHY_ERROR_TIMING |
|
| AR5K_DESC_RX_PHY_ERROR_TRANSMIT |
|
| AR5K_DESC_RX_PHY_ERROR_TRANSMIT |
|
| AR5K_DESC_TX_STATUS0_EXCESSIVE_ |
|
| AR5K_DESC_TX_STATUS0_EXCESSIVE_ |
|
| AR5K_DESC_TX_STATUS0_FIFO_UNDER |
|
| AR5K_DESC_TX_STATUS0_FIFO_UNDER |
|
| AR5K_DESC_TX_STATUS0_FILTERED |
|
| AR5K_DESC_TX_STATUS0_FILTERED |
|
| AR5K_DESC_TX_STATUS0_FRAME_XMIT |
|
| AR5K_DESC_TX_STATUS0_FRAME_XMIT |
|
| AR5K_DESC_TX_STATUS0_LONG_RETRY |
|
| AR5K_DESC_TX_STATUS0_LONG_RETRY |
|
| AR5K_DESC_TX_STATUS0_LONG_RETRY |
|
| AR5K_DESC_TX_STATUS0_LONG_RETRY |
|
| AR5K_DESC_TX_STATUS0_SEND_TIMES |
|
| AR5K_DESC_TX_STATUS0_SEND_TIMES |
|
| AR5K_DESC_TX_STATUS0_SEND_TIMES |
|
| AR5K_DESC_TX_STATUS0_SEND_TIMES |
|
| AR5K_DESC_TX_STATUS0_SHORT_RETR |
|
| AR5K_DESC_TX_STATUS0_SHORT_RETR |
|
| AR5K_DESC_TX_STATUS0_SHORT_RETR |
|
| AR5K_DESC_TX_STATUS0_SHORT_RETR |
|
| AR5K_DESC_TX_STATUS0_VIRT_COLL_ |
|
| AR5K_DESC_TX_STATUS0_VIRT_COLL_ |
|
| AR5K_DESC_TX_STATUS0_VIRT_COLL_ |
|
| AR5K_DESC_TX_STATUS0_VIRT_COLL_ |
|
| AR5K_DESC_TX_STATUS1_ACK_SIG_ST |
|
| AR5K_DESC_TX_STATUS1_ACK_SIG_ST |
|
| AR5K_DESC_TX_STATUS1_ACK_SIG_ST |
|
| AR5K_DESC_TX_STATUS1_ACK_SIG_ST |
|
| AR5K_DESC_TX_STATUS1_COMP_SUCCE |
|
| AR5K_DESC_TX_STATUS1_COMP_SUCCE |
|
| AR5K_DESC_TX_STATUS1_DONE |
|
| AR5K_DESC_TX_STATUS1_DONE |
|
| AR5K_DESC_TX_STATUS1_FINAL_TS_I |
|
| AR5K_DESC_TX_STATUS1_FINAL_TS_I |
|
| AR5K_DESC_TX_STATUS1_FINAL_TS_I |
|
| AR5K_DESC_TX_STATUS1_FINAL_TS_I |
|
| AR5K_DESC_TX_STATUS1_SEQ_NUM |
|
| AR5K_DESC_TX_STATUS1_SEQ_NUM |
|
| AR5K_DESC_TX_STATUS1_SEQ_NUM_S |
|
| AR5K_DESC_TX_STATUS1_SEQ_NUM_S |
|
| AR5K_DESC_TX_STATUS1_XMIT_ANTEN |
|
| AR5K_DESC_TX_STATUS1_XMIT_ANTEN |
|
| AR5K_DIAG_SW |
|
| AR5K_DIAG_SW |
|
| AR5K_DIAG_SW_5210 |
Register Address [5210] |
| AR5K_DIAG_SW_5210 |
Register Address [5210] |
| AR5K_DIAG_SW_5211 |
Register Address [5211+] |
| AR5K_DIAG_SW_5211 |
Register Address [5211+] |
| AR5K_DIAG_SW_CHAN_INFO |
|
| AR5K_DIAG_SW_CHAN_INFO |
|
| AR5K_DIAG_SW_CHAN_INFO_5210 |
Dump channel info |
| AR5K_DIAG_SW_CHAN_INFO_5210 |
Dump channel info |
| AR5K_DIAG_SW_CHAN_INFO_5211 |
|
| AR5K_DIAG_SW_CHAN_INFO_5211 |
|
| AR5K_DIAG_SW_CHANEL_IDLE_HIGH |
Force channel idle high |
| AR5K_DIAG_SW_CHANEL_IDLE_HIGH |
Force channel idle high |
| AR5K_DIAG_SW_CORR_FCS |
|
| AR5K_DIAG_SW_CORR_FCS |
|
| AR5K_DIAG_SW_CORR_FCS_5210 |
Corrupted FCS |
| AR5K_DIAG_SW_CORR_FCS_5210 |
Corrupted FCS |
| AR5K_DIAG_SW_CORR_FCS_5211 |
|
| AR5K_DIAG_SW_CORR_FCS_5211 |
|
| AR5K_DIAG_SW_DIS_ACK |
Disable ACKs |
| AR5K_DIAG_SW_DIS_ACK |
Disable ACKs |
| AR5K_DIAG_SW_DIS_CTS |
Disable CTSs |
| AR5K_DIAG_SW_DIS_CTS |
Disable CTSs |
| AR5K_DIAG_SW_DIS_DEC |
Disable decryption |
| AR5K_DIAG_SW_DIS_DEC |
Disable decryption |
| AR5K_DIAG_SW_DIS_ENC |
Disable encryption |
| AR5K_DIAG_SW_DIS_ENC |
Disable encryption |
| AR5K_DIAG_SW_DIS_RX |
|
| AR5K_DIAG_SW_DIS_RX |
|
| AR5K_DIAG_SW_DIS_RX_5210 |
Disable recieve |
| AR5K_DIAG_SW_DIS_RX_5210 |
Disable recieve |
| AR5K_DIAG_SW_DIS_RX_5211 |
|
| AR5K_DIAG_SW_DIS_RX_5211 |
|
| AR5K_DIAG_SW_DIS_SEQ_INC |
Disable seqnum increment (?)[5210] |
| AR5K_DIAG_SW_DIS_SEQ_INC |
Disable seqnum increment (?)[5210] |
| AR5K_DIAG_SW_DIS_TX |
Disable transmit [5210] |
| AR5K_DIAG_SW_DIS_TX |
Disable transmit [5210] |
| AR5K_DIAG_SW_DIS_WEP_ACK |
Disable ACKs if WEP key is invalid |
| AR5K_DIAG_SW_DIS_WEP_ACK |
Disable ACKs if WEP key is invalid |
| AR5K_DIAG_SW_ECO_ENABLE |
[5211+] |
| AR5K_DIAG_SW_ECO_ENABLE |
[5211+] |
| AR5K_DIAG_SW_EN_SCRAM_SEED |
|
| AR5K_DIAG_SW_EN_SCRAM_SEED |
|
| AR5K_DIAG_SW_EN_SCRAM_SEED_5210 |
Enable fixed scrambler seed |
| AR5K_DIAG_SW_EN_SCRAM_SEED_5210 |
Enable fixed scrambler seed |
| AR5K_DIAG_SW_EN_SCRAM_SEED_5211 |
|
| AR5K_DIAG_SW_EN_SCRAM_SEED_5211 |
|
| AR5K_DIAG_SW_FRAME_NV0 |
|
| AR5K_DIAG_SW_FRAME_NV0 |
|
| AR5K_DIAG_SW_FRAME_NV0_5210 |
|
| AR5K_DIAG_SW_FRAME_NV0_5210 |
|
| AR5K_DIAG_SW_FRAME_NV0_5211 |
Accept frames of non-zero protocol number |
| AR5K_DIAG_SW_FRAME_NV0_5211 |
Accept frames of non-zero protocol number |
| AR5K_DIAG_SW_IGNORE_CARR_SENSE |
Ignore virtual carrier sense |
| AR5K_DIAG_SW_IGNORE_CARR_SENSE |
Ignore virtual carrier sense |
| AR5K_DIAG_SW_LOOP_BACK |
|
| AR5K_DIAG_SW_LOOP_BACK |
|
| AR5K_DIAG_SW_LOOP_BACK_5210 |
Loopback (i guess it goes with DIS_TX) [5210] |
| AR5K_DIAG_SW_LOOP_BACK_5210 |
Loopback (i guess it goes with DIS_TX) [5210] |
| AR5K_DIAG_SW_LOOP_BACK_5211 |
|
| AR5K_DIAG_SW_LOOP_BACK_5211 |
|
| AR5K_DIAG_SW_OBSPT_M |
Observation point select (?) |
| AR5K_DIAG_SW_OBSPT_M |
Observation point select (?) |
| AR5K_DIAG_SW_OBSPT_S |
|
| AR5K_DIAG_SW_OBSPT_S |
|
| AR5K_DIAG_SW_PHEAR_ME |
??? |
| AR5K_DIAG_SW_PHEAR_ME |
??? |
| AR5K_DIAG_SW_RX_CLEAR_HIGH |
Force RX Clear high |
| AR5K_DIAG_SW_RX_CLEAR_HIGH |
Force RX Clear high |
| AR5K_DIAG_SW_SCRAM_SEED_M |
Scrambler seed mask |
| AR5K_DIAG_SW_SCRAM_SEED_M |
Scrambler seed mask |
| AR5K_DIAG_SW_SCRAM_SEED_S |
|
| AR5K_DIAG_SW_SCRAM_SEED_S |
|
| AR5K_DIAG_SW_SCVRAM_SEED |
[5210] |
| AR5K_DIAG_SW_SCVRAM_SEED |
[5210] |
| AR5K_DISABLE_QUEUE(_q) |
|
| AR5K_DISABLE_QUEUE(_q) |
|
| AR5K_EEPROM_AES_DIS(_v) |
|
| AR5K_EEPROM_AES_DIS(_v) |
|
| AR5K_EEPROM_ANT_GAIN(_v) |
|
| AR5K_EEPROM_ANT_GAIN(_v) |
|
| AR5K_EEPROM_ANT_GAIN_2GHZ(_v) |
|
| AR5K_EEPROM_ANT_GAIN_2GHZ(_v) |
|
| AR5K_EEPROM_ANT_GAIN_5GHZ(_v) |
|
| AR5K_EEPROM_ANT_GAIN_5GHZ(_v) |
|
| AR5K_EEPROM_ART_BUILD_NUM(_v) |
|
| AR5K_EEPROM_ART_BUILD_NUM(_v) |
|
| AR5K_EEPROM_BASE |
|
| AR5K_EEPROM_BASE |
|
| AR5K_EEPROM_BURST_DIS(_v) |
|
| AR5K_EEPROM_BURST_DIS(_v) |
|
| AR5K_EEPROM_CAL_DATA_START(_v) |
|
| AR5K_EEPROM_CAL_DATA_START(_v) |
|
| AR5K_EEPROM_CCK_OFDM_DELTA |
|
| AR5K_EEPROM_CCK_OFDM_DELTA |
|
| AR5K_EEPROM_CFG |
Register Addres |
| AR5K_EEPROM_CFG |
Register Addres |
| AR5K_EEPROM_CFG_CLK_RATE |
Clock rate |
| AR5K_EEPROM_CFG_CLK_RATE |
Clock rate |
| AR5K_EEPROM_CFG_CLK_RATE_156KHZ |
|
| AR5K_EEPROM_CFG_CLK_RATE_156KHZ |
|
| AR5K_EEPROM_CFG_CLK_RATE_312KHZ |
|
| AR5K_EEPROM_CFG_CLK_RATE_312KHZ |
|
| AR5K_EEPROM_CFG_CLK_RATE_625KHZ |
|
| AR5K_EEPROM_CFG_CLK_RATE_625KHZ |
|
| AR5K_EEPROM_CFG_CLK_RATE_S |
|
| AR5K_EEPROM_CFG_CLK_RATE_S |
|
| AR5K_EEPROM_CFG_LIND_EN |
Enable length indicator (?) |
| AR5K_EEPROM_CFG_LIND_EN |
Enable length indicator (?) |
| AR5K_EEPROM_CFG_PROT_KEY |
Protection key |
| AR5K_EEPROM_CFG_PROT_KEY |
Protection key |
| AR5K_EEPROM_CFG_PROT_KEY_S |
|
| AR5K_EEPROM_CFG_PROT_KEY_S |
|
| AR5K_EEPROM_CFG_SIZE |
Size determination override |
| AR5K_EEPROM_CFG_SIZE |
Size determination override |
| AR5K_EEPROM_CFG_SIZE_16KBIT |
|
| AR5K_EEPROM_CFG_SIZE_16KBIT |
|
| AR5K_EEPROM_CFG_SIZE_4KBIT |
|
| AR5K_EEPROM_CFG_SIZE_4KBIT |
|
| AR5K_EEPROM_CFG_SIZE_8KBIT |
|
| AR5K_EEPROM_CFG_SIZE_8KBIT |
|
| AR5K_EEPROM_CFG_SIZE_AUTO |
|
| AR5K_EEPROM_CFG_SIZE_AUTO |
|
| AR5K_EEPROM_CFG_WR_WAIT_DIS |
Disable write wait |
| AR5K_EEPROM_CFG_WR_WAIT_DIS |
Disable write wait |
| AR5K_EEPROM_CHANNEL_DIS |
|
| AR5K_EEPROM_CHANNEL_DIS |
|
| AR5K_EEPROM_CHANNEL_POWER |
|
| AR5K_EEPROM_CHANNEL_POWER |
|
| AR5K_EEPROM_CHECKSUM |
EEPROM checksum |
| AR5K_EEPROM_CHECKSUM |
EEPROM checksum |
| AR5K_EEPROM_CMD |
Register Addres |
| AR5K_EEPROM_CMD |
Register Addres |
| AR5K_EEPROM_CMD_READ |
EEPROM read |
| AR5K_EEPROM_CMD_READ |
EEPROM read |
| AR5K_EEPROM_CMD_RESET |
EEPROM reset |
| AR5K_EEPROM_CMD_RESET |
EEPROM reset |
| AR5K_EEPROM_CMD_WRITE |
EEPROM write |
| AR5K_EEPROM_CMD_WRITE |
EEPROM write |
| AR5K_EEPROM_COMP_DIS(_v) |
|
| AR5K_EEPROM_COMP_DIS(_v) |
|
| AR5K_EEPROM_CTL(_v) |
Conformance test limits |
| AR5K_EEPROM_CTL(_v) |
Conformance test limits |
| AR5K_EEPROM_DATA |
|
| AR5K_EEPROM_DATA |
|
| AR5K_EEPROM_DATA_5210 |
|
| AR5K_EEPROM_DATA_5210 |
|
| AR5K_EEPROM_DATA_5211 |
|
| AR5K_EEPROM_DATA_5211 |
|
| AR5K_EEPROM_EAR_FILE_ID(_v) |
|
| AR5K_EEPROM_EAR_FILE_ID(_v) |
|
| AR5K_EEPROM_EAR_FILE_VERSION(_v) |
|
| AR5K_EEPROM_EAR_FILE_VERSION(_v) |
|
| AR5K_EEPROM_EARSTART(_v) |
|
| AR5K_EEPROM_EARSTART(_v) |
|
| AR5K_EEPROM_EEMAP(_v) |
|
| AR5K_EEPROM_EEMAP(_v) |
|
| AR5K_EEPROM_EEP_DELTA |
|
| AR5K_EEPROM_EEP_DELTA |
|
| AR5K_EEPROM_EEP_FILE_VERSION(_v) |
|
| AR5K_EEPROM_EEP_FILE_VERSION(_v) |
|
| AR5K_EEPROM_EEP_SCALE |
|
| AR5K_EEPROM_EEP_SCALE |
|
| AR5K_EEPROM_FCC_MID_EN |
|
| AR5K_EEPROM_FCC_MID_EN |
|
| AR5K_EEPROM_FF_DIS(_v) |
|
| AR5K_EEPROM_FF_DIS(_v) |
|
| AR5K_EEPROM_FREQ_M(_v) |
|
| AR5K_EEPROM_FREQ_M(_v) |
|
| AR5K_EEPROM_GROUP1_OFFSET |
|
| AR5K_EEPROM_GROUP1_OFFSET |
|
| AR5K_EEPROM_GROUP2_OFFSET |
|
| AR5K_EEPROM_GROUP2_OFFSET |
|
| AR5K_EEPROM_GROUP3_OFFSET |
|
| AR5K_EEPROM_GROUP3_OFFSET |
|
| AR5K_EEPROM_GROUP4_OFFSET |
|
| AR5K_EEPROM_GROUP4_OFFSET |
|
| AR5K_EEPROM_GROUP5_OFFSET |
|
| AR5K_EEPROM_GROUP5_OFFSET |
|
| AR5K_EEPROM_GROUP6_OFFSET |
|
| AR5K_EEPROM_GROUP6_OFFSET |
|
| AR5K_EEPROM_GROUP7_OFFSET |
|
| AR5K_EEPROM_GROUP7_OFFSET |
|
| AR5K_EEPROM_GROUP8_OFFSET |
|
| AR5K_EEPROM_GROUP8_OFFSET |
|
| AR5K_EEPROM_GROUPS_START(_v) |
Start of Groups |
| AR5K_EEPROM_GROUPS_START(_v) |
Start of Groups |
| AR5K_EEPROM_HAS32KHZCRYSTAL(_v) |
|
| AR5K_EEPROM_HAS32KHZCRYSTAL(_v) |
|
| AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) |
|
| AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) |
|
| AR5K_EEPROM_HDR |
Header that contains the device caps |
| AR5K_EEPROM_HDR |
Header that contains the device caps |
| AR5K_EEPROM_HDR_11A(_v) |
|
| AR5K_EEPROM_HDR_11A(_v) |
|
| AR5K_EEPROM_HDR_11B(_v) |
|
| AR5K_EEPROM_HDR_11B(_v) |
|
| AR5K_EEPROM_HDR_11G(_v) |
|
| AR5K_EEPROM_HDR_11G(_v) |
|
| AR5K_EEPROM_HDR_DEVICE(_v) |
|
| AR5K_EEPROM_HDR_DEVICE(_v) |
|
| AR5K_EEPROM_HDR_RFKILL(_v) |
Device has RFKill support |
| AR5K_EEPROM_HDR_RFKILL(_v) |
Device has RFKill support |
| AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) |
Disable turbo for 2Ghz (?) |
| AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) |
Disable turbo for 2Ghz (?) |
| AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) |
Max turbo power for a/XR mode (eeprom_init) |
| AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) |
Max turbo power for a/XR mode (eeprom_init) |
| AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) |
Disable turbo for 5Ghz |
| AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) |
Disable turbo for 5Ghz |
| AR5K_EEPROM_HDR_XR2_DIS(_v) |
|
| AR5K_EEPROM_HDR_XR2_DIS(_v) |
|
| AR5K_EEPROM_HDR_XR5_DIS(_v) |
|
| AR5K_EEPROM_HDR_XR5_DIS(_v) |
|
| AR5K_EEPROM_HEAVY_CLIP_EN(_v) |
|
| AR5K_EEPROM_HEAVY_CLIP_EN(_v) |
|
| AR5K_EEPROM_I_GAIN |
|
| AR5K_EEPROM_I_GAIN |
|
| AR5K_EEPROM_INFO(_n) |
|
| AR5K_EEPROM_INFO(_n) |
|
| AR5K_EEPROM_INFO_BASE |
EEPROM header |
| AR5K_EEPROM_INFO_BASE |
EEPROM header |
| AR5K_EEPROM_INFO_CKSUM |
|
| AR5K_EEPROM_INFO_CKSUM |
|
| AR5K_EEPROM_INFO_MAX |
|
| AR5K_EEPROM_INFO_MAX |
|
| AR5K_EEPROM_IS_HB63 |
Talon detect |
| AR5K_EEPROM_IS_HB63 |
Talon detect |
| AR5K_EEPROM_JAP_11A_NEW_EN |
|
| AR5K_EEPROM_JAP_11A_NEW_EN |
|
| AR5K_EEPROM_JAP_U1EVEN_EN |
|
| AR5K_EEPROM_JAP_U1EVEN_EN |
|
| AR5K_EEPROM_JAP_U1ODD_EN |
|
| AR5K_EEPROM_JAP_U1ODD_EN |
|
| AR5K_EEPROM_JAP_U2_EN |
|
| AR5K_EEPROM_JAP_U2_EN |
|
| AR5K_EEPROM_KEY_CACHE_SIZE(_v) |
|
| AR5K_EEPROM_KEY_CACHE_SIZE(_v) |
|
| AR5K_EEPROM_MAGIC |
EEPROM Magic number |
| AR5K_EEPROM_MAGIC |
EEPROM Magic number |
| AR5K_EEPROM_MAGIC_5210 |
5210 |
| AR5K_EEPROM_MAGIC_5210 |
5210 |
| AR5K_EEPROM_MAGIC_5211 |
5211 |
| AR5K_EEPROM_MAGIC_5211 |
5211 |
| AR5K_EEPROM_MAGIC_5212 |
5212 |
| AR5K_EEPROM_MAGIC_5212 |
5212 |
| AR5K_EEPROM_MAGIC_VALUE |
Default - found on EEPROM |
| AR5K_EEPROM_MAGIC_VALUE |
Default - found on EEPROM |
| AR5K_EEPROM_MASK_R0(_v) |
|
| AR5K_EEPROM_MASK_R0(_v) |
|
| AR5K_EEPROM_MASK_R1(_v) |
|
| AR5K_EEPROM_MASK_R1(_v) |
|
| AR5K_EEPROM_MAX_CHAN |
|
| AR5K_EEPROM_MAX_CHAN |
|
| AR5K_EEPROM_MAX_CTLS |
|
| AR5K_EEPROM_MAX_CTLS |
|
| AR5K_EEPROM_MAX_QCU(_v) |
|
| AR5K_EEPROM_MAX_QCU(_v) |
|
| AR5K_EEPROM_MISC0 |
|
| AR5K_EEPROM_MISC0 |
|
| AR5K_EEPROM_MISC1 |
|
| AR5K_EEPROM_MISC1 |
|
| AR5K_EEPROM_MISC2 |
|
| AR5K_EEPROM_MISC2 |
|
| AR5K_EEPROM_MISC3 |
|
| AR5K_EEPROM_MISC3 |
|
| AR5K_EEPROM_MISC4 |
|
| AR5K_EEPROM_MISC4 |
|
| AR5K_EEPROM_MISC5 |
|
| AR5K_EEPROM_MISC5 |
|
| AR5K_EEPROM_MISC6 |
|
| AR5K_EEPROM_MISC6 |
|
| AR5K_EEPROM_MODE_11A |
|
| AR5K_EEPROM_MODE_11A |
|
| AR5K_EEPROM_MODE_11B |
|
| AR5K_EEPROM_MODE_11B |
|
| AR5K_EEPROM_MODE_11G |
|
| AR5K_EEPROM_MODE_11G |
|
| AR5K_EEPROM_MODES_11A(_v) |
|
| AR5K_EEPROM_MODES_11A(_v) |
|
| AR5K_EEPROM_MODES_11B(_v) |
|
| AR5K_EEPROM_MODES_11B(_v) |
|
| AR5K_EEPROM_MODES_11G(_v) |
|
| AR5K_EEPROM_MODES_11G(_v) |
|
| AR5K_EEPROM_N_2GHZ_CHAN |
|
| AR5K_EEPROM_N_2GHZ_CHAN |
|
| AR5K_EEPROM_N_2GHZ_CHAN_2413 |
|
| AR5K_EEPROM_N_2GHZ_CHAN_2413 |
|
| AR5K_EEPROM_N_2GHZ_CHAN_MAX |
|
| AR5K_EEPROM_N_2GHZ_CHAN_MAX |
|
| AR5K_EEPROM_N_5GHZ_CHAN |
|
| AR5K_EEPROM_N_5GHZ_CHAN |
|
| AR5K_EEPROM_N_CTLS(_v) |
|
| AR5K_EEPROM_N_CTLS(_v) |
|
| AR5K_EEPROM_N_EDGES |
|
| AR5K_EEPROM_N_EDGES |
|
| AR5K_EEPROM_N_INTERCEPT_10_2GHZ |
|
| AR5K_EEPROM_N_INTERCEPT_10_2GHZ |
|
| AR5K_EEPROM_N_INTERCEPT_10_5GHZ |
|
| AR5K_EEPROM_N_INTERCEPT_10_5GHZ |
|
| AR5K_EEPROM_N_INTERCEPTS |
|
| AR5K_EEPROM_N_INTERCEPTS |
|
| AR5K_EEPROM_N_IQ_CAL |
|
| AR5K_EEPROM_N_IQ_CAL |
|
| AR5K_EEPROM_N_MODES |
|
| AR5K_EEPROM_N_MODES |
|
| AR5K_EEPROM_N_OBDB |
|
| AR5K_EEPROM_N_OBDB |
|
| AR5K_EEPROM_N_PCDAC |
|
| AR5K_EEPROM_N_PCDAC |
|
| AR5K_EEPROM_N_PD_CURVES |
|
| AR5K_EEPROM_N_PD_CURVES |
|
| AR5K_EEPROM_N_PD_GAINS |
|
| AR5K_EEPROM_N_PD_GAINS |
|
| AR5K_EEPROM_N_PD_POINTS |
|
| AR5K_EEPROM_N_PD_POINTS |
|
| AR5K_EEPROM_N_PHASE_CAL |
|
| AR5K_EEPROM_N_PHASE_CAL |
|
| AR5K_EEPROM_N_POWER_LOC_11B |
|
| AR5K_EEPROM_N_POWER_LOC_11B |
|
| AR5K_EEPROM_N_POWER_LOC_11G |
|
| AR5K_EEPROM_N_POWER_LOC_11G |
|
| AR5K_EEPROM_N_PWR_POINTS_5111 |
|
| AR5K_EEPROM_N_PWR_POINTS_5111 |
|
| AR5K_EEPROM_N_TEST_FREQ |
|
| AR5K_EEPROM_N_TEST_FREQ |
|
| AR5K_EEPROM_N_XPD0_POINTS |
|
| AR5K_EEPROM_N_XPD0_POINTS |
|
| AR5K_EEPROM_N_XPD3_POINTS |
|
| AR5K_EEPROM_N_XPD3_POINTS |
|
| AR5K_EEPROM_NON_EDGE_M |
|
| AR5K_EEPROM_NON_EDGE_M |
|
| AR5K_EEPROM_OBDB_DIS |
|
| AR5K_EEPROM_OBDB_DIS |
|
| AR5K_EEPROM_OBDB0_2GHZ |
|
| AR5K_EEPROM_OBDB0_2GHZ |
|
| AR5K_EEPROM_OBDB1_2GHZ |
|
| AR5K_EEPROM_OBDB1_2GHZ |
|
| AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) |
|
| AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) |
|
| AR5K_EEPROM_PCDAC_M |
|
| AR5K_EEPROM_PCDAC_M |
|
| AR5K_EEPROM_PCDAC_START |
|
| AR5K_EEPROM_PCDAC_START |
|
| AR5K_EEPROM_PCDAC_STEP |
|
| AR5K_EEPROM_PCDAC_STEP |
|
| AR5K_EEPROM_PCDAC_STOP |
|
| AR5K_EEPROM_PCDAC_STOP |
|
| AR5K_EEPROM_POWER_M |
|
| AR5K_EEPROM_POWER_M |
|
| AR5K_EEPROM_POWER_MAX |
|
| AR5K_EEPROM_POWER_MAX |
|
| AR5K_EEPROM_POWER_MIN |
|
| AR5K_EEPROM_POWER_MIN |
|
| AR5K_EEPROM_POWER_STEP |
|
| AR5K_EEPROM_POWER_STEP |
|
| AR5K_EEPROM_POWER_TABLE_SIZE |
|
| AR5K_EEPROM_POWER_TABLE_SIZE |
|
| AR5K_EEPROM_PROTECT |
EEPROM protect status |
| AR5K_EEPROM_PROTECT |
EEPROM protect status |
| AR5K_EEPROM_PROTECT_RD_0_31 |
Read protection bit for offsets 0x0 - 0x1f |
| AR5K_EEPROM_PROTECT_RD_0_31 |
Read protection bit for offsets 0x0 - 0x1f |
| AR5K_EEPROM_PROTECT_RD_128_191 |
0x80 - 0xbf (regdom) |
| AR5K_EEPROM_PROTECT_RD_128_191 |
0x80 - 0xbf (regdom) |
| AR5K_EEPROM_PROTECT_RD_192_207 |
0xc0 - 0xcf |
| AR5K_EEPROM_PROTECT_RD_192_207 |
0xc0 - 0xcf |
| AR5K_EEPROM_PROTECT_RD_208_223 |
0xd0 - 0xdf |
| AR5K_EEPROM_PROTECT_RD_208_223 |
0xd0 - 0xdf |
| AR5K_EEPROM_PROTECT_RD_224_239 |
0xe0 - 0xef |
| AR5K_EEPROM_PROTECT_RD_224_239 |
0xe0 - 0xef |
| AR5K_EEPROM_PROTECT_RD_240_255 |
0xf0 - 0xff |
| AR5K_EEPROM_PROTECT_RD_240_255 |
0xf0 - 0xff |
| AR5K_EEPROM_PROTECT_RD_32_63 |
0x20 - 0x3f |
| AR5K_EEPROM_PROTECT_RD_32_63 |
0x20 - 0x3f |
| AR5K_EEPROM_PROTECT_RD_64_127 |
0x40 - 0x7f |
| AR5K_EEPROM_PROTECT_RD_64_127 |
0x40 - 0x7f |
| AR5K_EEPROM_PROTECT_WR_0_31 |
Write protection bit for offsets 0x0 - 0x1f |
| AR5K_EEPROM_PROTECT_WR_0_31 |
Write protection bit for offsets 0x0 - 0x1f |
| AR5K_EEPROM_PROTECT_WR_128_191 |
|
| AR5K_EEPROM_PROTECT_WR_128_191 |
|
| AR5K_EEPROM_PROTECT_WR_192_207 |
|
| AR5K_EEPROM_PROTECT_WR_192_207 |
|
| AR5K_EEPROM_PROTECT_WR_208_223 |
|
| AR5K_EEPROM_PROTECT_WR_208_223 |
|
| AR5K_EEPROM_PROTECT_WR_224_239 |
|
| AR5K_EEPROM_PROTECT_WR_224_239 |
|
| AR5K_EEPROM_PROTECT_WR_240_255 |
|
| AR5K_EEPROM_PROTECT_WR_240_255 |
|
| AR5K_EEPROM_PROTECT_WR_32_63 |
|
| AR5K_EEPROM_PROTECT_WR_32_63 |
|
| AR5K_EEPROM_PROTECT_WR_64_127 |
|
| AR5K_EEPROM_PROTECT_WR_64_127 |
|
| AR5K_EEPROM_READ(_o, _v) |
|
| AR5K_EEPROM_READ(_o, _v) |
|
| AR5K_EEPROM_READ_HDR(_o, _v) |
|
| AR5K_EEPROM_READ_HDR(_o, _v) |
|
| AR5K_EEPROM_REG_DOMAIN |
EEPROM regdom |
| AR5K_EEPROM_REG_DOMAIN |
EEPROM regdom |
| AR5K_EEPROM_RFKILL |
|
| AR5K_EEPROM_RFKILL |
|
| AR5K_EEPROM_RFKILL_GPIO_SEL |
|
| AR5K_EEPROM_RFKILL_GPIO_SEL |
|
| AR5K_EEPROM_RFKILL_GPIO_SEL |
|
| AR5K_EEPROM_RFKILL_GPIO_SEL |
|
| AR5K_EEPROM_RFKILL_GPIO_SEL_S |
|
| AR5K_EEPROM_RFKILL_GPIO_SEL_S |
|
| AR5K_EEPROM_RFKILL_GPIO_SEL_S |
|
| AR5K_EEPROM_RFKILL_GPIO_SEL_S |
|
| AR5K_EEPROM_RFKILL_POLARITY |
|
| AR5K_EEPROM_RFKILL_POLARITY |
|
| AR5K_EEPROM_RFKILL_POLARITY |
|
| AR5K_EEPROM_RFKILL_POLARITY |
|
| AR5K_EEPROM_RFKILL_POLARITY_S |
|
| AR5K_EEPROM_RFKILL_POLARITY_S |
|
| AR5K_EEPROM_RFKILL_POLARITY_S |
|
| AR5K_EEPROM_RFKILL_POLARITY_S |
|
| AR5K_EEPROM_RX_CHAIN_DIS |
|
| AR5K_EEPROM_RX_CHAIN_DIS |
|
| AR5K_EEPROM_SCALE_OC_DELTA(_x) |
|
| AR5K_EEPROM_SCALE_OC_DELTA(_x) |
|
| AR5K_EEPROM_STAT_5210 |
Register Address [5210] |
| AR5K_EEPROM_STAT_5210 |
Register Address [5210] |
| AR5K_EEPROM_STAT_5211 |
Register Address [5211+] |
| AR5K_EEPROM_STAT_5211 |
Register Address [5211+] |
| AR5K_EEPROM_STAT_RDDONE |
EEPROM read successful |
| AR5K_EEPROM_STAT_RDDONE |
EEPROM read successful |
| AR5K_EEPROM_STAT_RDERR |
EEPROM read failed |
| AR5K_EEPROM_STAT_RDERR |
EEPROM read failed |
| AR5K_EEPROM_STAT_WRDONE |
EEPROM write successful |
| AR5K_EEPROM_STAT_WRDONE |
EEPROM write successful |
| AR5K_EEPROM_STAT_WRERR |
EEPROM write failed |
| AR5K_EEPROM_STAT_WRERR |
EEPROM write failed |
| AR5K_EEPROM_STATUS |
|
| AR5K_EEPROM_STATUS |
|
| AR5K_EEPROM_TARGET_PWR_OFF_11A(_v) |
|
| AR5K_EEPROM_TARGET_PWR_OFF_11A(_v) |
|
| AR5K_EEPROM_TARGET_PWR_OFF_11B(_v) |
|
| AR5K_EEPROM_TARGET_PWR_OFF_11B(_v) |
|
| AR5K_EEPROM_TARGET_PWR_OFF_11G(_v) |
|
| AR5K_EEPROM_TARGET_PWR_OFF_11G(_v) |
|
| AR5K_EEPROM_TARGET_PWRSTART(_v) |
|
| AR5K_EEPROM_TARGET_PWRSTART(_v) |
|
| AR5K_EEPROM_TX_CHAIN_DIS |
|
| AR5K_EEPROM_TX_CHAIN_DIS |
|
| AR5K_EEPROM_VERSION |
EEPROM Version |
| AR5K_EEPROM_VERSION |
EEPROM Version |
| AR5K_EEPROM_VERSION_3_0 |
No idea what's going on before this version |
| AR5K_EEPROM_VERSION_3_0 |
No idea what's going on before this version |
| AR5K_EEPROM_VERSION_3_1 |
ob/db values for 2Ghz (ar5211_rfregs) |
| AR5K_EEPROM_VERSION_3_1 |
ob/db values for 2Ghz (ar5211_rfregs) |
| AR5K_EEPROM_VERSION_3_2 |
different frequency representation (eeprom_bin2freq) |
| AR5K_EEPROM_VERSION_3_2 |
different frequency representation (eeprom_bin2freq) |
| AR5K_EEPROM_VERSION_3_3 |
offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) |
| AR5K_EEPROM_VERSION_3_3 |
offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) |
| AR5K_EEPROM_VERSION_3_4 |
has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) |
| AR5K_EEPROM_VERSION_3_4 |
has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) |
| AR5K_EEPROM_VERSION_4_0 |
has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) |
| AR5K_EEPROM_VERSION_4_0 |
has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) |
| AR5K_EEPROM_VERSION_4_1 |
has ee_margin_tx_rx (eeprom_init) |
| AR5K_EEPROM_VERSION_4_1 |
has ee_margin_tx_rx (eeprom_init) |
| AR5K_EEPROM_VERSION_4_2 |
has ee_cck_ofdm_gain_delta (eeprom_init) |
| AR5K_EEPROM_VERSION_4_2 |
has ee_cck_ofdm_gain_delta (eeprom_init) |
| AR5K_EEPROM_VERSION_4_3 |
power calibration changes |
| AR5K_EEPROM_VERSION_4_3 |
power calibration changes |
| AR5K_EEPROM_VERSION_4_4 |
|
| AR5K_EEPROM_VERSION_4_4 |
|
| AR5K_EEPROM_VERSION_4_5 |
|
| AR5K_EEPROM_VERSION_4_5 |
|
| AR5K_EEPROM_VERSION_4_6 |
has ee_scaled_cck_delta |
| AR5K_EEPROM_VERSION_4_6 |
has ee_scaled_cck_delta |
| AR5K_EEPROM_VERSION_4_7 |
4007 ? |
| AR5K_EEPROM_VERSION_4_7 |
4007 ? |
| AR5K_EEPROM_VERSION_4_9 |
EAR futureproofing |
| AR5K_EEPROM_VERSION_4_9 |
EAR futureproofing |
| AR5K_EEPROM_VERSION_5_0 |
Has 2413 PDADC calibration etc |
| AR5K_EEPROM_VERSION_5_0 |
Has 2413 PDADC calibration etc |
| AR5K_EEPROM_VERSION_5_1 |
Has capability values |
| AR5K_EEPROM_VERSION_5_1 |
Has capability values |
| AR5K_EEPROM_VERSION_5_3 |
Has spur mitigation tables |
| AR5K_EEPROM_VERSION_5_3 |
Has spur mitigation tables |
| AR5K_ENABLE_QUEUE(_q) |
|
| AR5K_ENABLE_QUEUE(_q) |
|
| AR5K_FCS_FAIL |
|
| AR5K_FCS_FAIL |
|
| AR5K_FCS_FAIL_5210 |
|
| AR5K_FCS_FAIL_5210 |
|
| AR5K_FCS_FAIL_5211 |
|
| AR5K_FCS_FAIL_5211 |
|
| AR5K_FRAME_CTL_QOSM |
|
| AR5K_FRAME_CTL_QOSM |
|
| AR5K_GAIN_CCK_OFDM_GAIN_DELTA |
|
| AR5K_GAIN_CCK_OFDM_GAIN_DELTA |
|
| AR5K_GAIN_CCK_PROBE_CORR |
|
| AR5K_GAIN_CCK_PROBE_CORR |
|
| AR5K_GAIN_CHECK_ADJUST(_g) |
|
| AR5K_GAIN_CHECK_ADJUST(_g) |
|
| AR5K_GAIN_CRN_FIX_BITS_5111 |
|
| AR5K_GAIN_CRN_FIX_BITS_5111 |
|
| AR5K_GAIN_CRN_FIX_BITS_5112 |
|
| AR5K_GAIN_CRN_FIX_BITS_5112 |
|
| AR5K_GAIN_CRN_MAX_FIX_BITS |
|
| AR5K_GAIN_CRN_MAX_FIX_BITS |
|
| AR5K_GAIN_DYN_ADJUST_HI_MARGIN |
|
| AR5K_GAIN_DYN_ADJUST_HI_MARGIN |
|
| AR5K_GAIN_DYN_ADJUST_LO_MARGIN |
|
| AR5K_GAIN_DYN_ADJUST_LO_MARGIN |
|
| AR5K_GAIN_STEP_COUNT |
|
| AR5K_GAIN_STEP_COUNT |
|
| AR5K_GPIOCR |
Register Address |
| AR5K_GPIOCR |
Register Address |
| AR5K_GPIOCR_IN(n) |
Mode 0 for pin n |
| AR5K_GPIOCR_IN(n) |
Mode 0 for pin n |
| AR5K_GPIOCR_INT_ENA |
Enable GPIO interrupt |
| AR5K_GPIOCR_INT_ENA |
Enable GPIO interrupt |
| AR5K_GPIOCR_INT_SEL(n) |
Interrupt for GPIO pin n |
| AR5K_GPIOCR_INT_SEL(n) |
Interrupt for GPIO pin n |
| AR5K_GPIOCR_INT_SELH |
Generate interrupt when pin is high |
| AR5K_GPIOCR_INT_SELH |
Generate interrupt when pin is high |
| AR5K_GPIOCR_INT_SELL |
Generate interrupt when pin is low |
| AR5K_GPIOCR_INT_SELL |
Generate interrupt when pin is low |
| AR5K_GPIOCR_OUT(n) |
Mode 3 for pin n |
| AR5K_GPIOCR_OUT(n) |
Mode 3 for pin n |
| AR5K_GPIOCR_OUT0(n) |
Mode 1 for pin n |
| AR5K_GPIOCR_OUT0(n) |
Mode 1 for pin n |
| AR5K_GPIOCR_OUT1(n) |
Mode 2 for pin n |
| AR5K_GPIOCR_OUT1(n) |
Mode 2 for pin n |
| AR5K_GPIODI |
|
| AR5K_GPIODI |
|
| AR5K_GPIODI_M |
|
| AR5K_GPIODI_M |
|
| AR5K_GPIODO |
|
| AR5K_GPIODO |
|
| AR5K_HIGH_ID(_a) |
|
| AR5K_HIGH_ID(_a) |
|
| AR5K_IER |
Register Address |
| AR5K_IER |
Register Address |
| AR5K_IER_DISABLE |
Disable card interrupts |
| AR5K_IER_DISABLE |
Disable card interrupts |
| AR5K_IER_ENABLE |
Enable card interrupts |
| AR5K_IER_ENABLE |
Enable card interrupts |
| AR5K_IFS0 |
|
| AR5K_IFS0 |
|
| AR5K_IFS0_DIFS |
|
| AR5K_IFS0_DIFS |
|
| AR5K_IFS0_DIFS_S |
|
| AR5K_IFS0_DIFS_S |
|
| AR5K_IFS0_SIFS |
|
| AR5K_IFS0_SIFS |
|
| AR5K_IFS0_SIFS_S |
|
| AR5K_IFS0_SIFS_S |
|
| AR5K_IFS1 |
|
| AR5K_IFS1 |
|
| AR5K_IFS1_CS_EN |
|
| AR5K_IFS1_CS_EN |
|
| AR5K_IFS1_EIFS |
|
| AR5K_IFS1_EIFS |
|
| AR5K_IFS1_EIFS_S |
|
| AR5K_IFS1_EIFS_S |
|
| AR5K_IFS1_PIFS |
|
| AR5K_IFS1_PIFS |
|
| AR5K_IFS1_PIFS_S |
|
| AR5K_IFS1_PIFS_S |
|
| AR5K_IMR |
Register Address [5210] |
| AR5K_IMR |
Register Address [5210] |
| AR5K_IMR_BCNMISC |
'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, |
| AR5K_IMR_BCNMISC |
'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, |
| AR5K_IMR_BMISS |
Beacon missed |
| AR5K_IMR_BMISS |
Beacon missed |
| AR5K_IMR_BNR |
Beacon not ready [5211+] |
| AR5K_IMR_BNR |
Beacon not ready [5211+] |
| AR5K_IMR_BRSSI |
Beacon rssi below threshold (?) |
| AR5K_IMR_BRSSI |
Beacon rssi below threshold (?) |
| AR5K_IMR_DPERR |
Det par Error (?) [5210] |
| AR5K_IMR_DPERR |
Det par Error (?) [5210] |
| AR5K_IMR_GPIO |
GPIO (rf kill) |
| AR5K_IMR_GPIO |
GPIO (rf kill) |
| AR5K_IMR_HIUERR |
Host Interface Unit error [5211+] |
| AR5K_IMR_HIUERR |
Host Interface Unit error [5211+] |
| AR5K_IMR_MCABT |
Master Cycle Abort [5210] |
| AR5K_IMR_MCABT |
Master Cycle Abort [5210] |
| AR5K_IMR_MIB |
Update MIB counters |
| AR5K_IMR_MIB |
Update MIB counters |
| AR5K_IMR_QCBRORN |
QCU CBR overrun (?) [5211+] |
| AR5K_IMR_QCBRORN |
QCU CBR overrun (?) [5211+] |
| AR5K_IMR_QCBRURN |
QCU CBR underrun (?) [5211+] |
| AR5K_IMR_QCBRURN |
QCU CBR underrun (?) [5211+] |
| AR5K_IMR_QTRIG |
QCU scheduling trigger [5211+] |
| AR5K_IMR_QTRIG |
QCU scheduling trigger [5211+] |
| AR5K_IMR_RXCHIRP |
CHIRP Received [5212+] |
| AR5K_IMR_RXCHIRP |
CHIRP Received [5212+] |
| AR5K_IMR_RXDESC |
RX descriptor request |
| AR5K_IMR_RXDESC |
RX descriptor request |
| AR5K_IMR_RXDOPPLER |
Doppler chirp received [5212+] |
| AR5K_IMR_RXDOPPLER |
Doppler chirp received [5212+] |
| AR5K_IMR_RXEOL |
Empty RX descriptor |
| AR5K_IMR_RXEOL |
Empty RX descriptor |
| AR5K_IMR_RXERR |
Receive error |
| AR5K_IMR_RXERR |
Receive error |
| AR5K_IMR_RXKCM |
RX Key cache miss |
| AR5K_IMR_RXKCM |
RX Key cache miss |
| AR5K_IMR_RXNOFRM |
No frame received (receive timeout) |
| AR5K_IMR_RXNOFRM |
No frame received (receive timeout) |
| AR5K_IMR_RXOK |
Frame successfuly recieved |
| AR5K_IMR_RXOK |
Frame successfuly recieved |
| AR5K_IMR_RXORN |
Receive FIFO overrun |
| AR5K_IMR_RXORN |
Receive FIFO overrun |
| AR5K_IMR_RXPHY |
PHY error |
| AR5K_IMR_RXPHY |
PHY error |
| AR5K_IMR_SSERR |
Signaled System Error [5210] |
| AR5K_IMR_SSERR |
Signaled System Error [5210] |
| AR5K_IMR_SWBA |
Software beacon alert |
| AR5K_IMR_SWBA |
Software beacon alert |
| AR5K_IMR_SWI |
Software interrupt |
| AR5K_IMR_SWI |
Software interrupt |
| AR5K_IMR_TIM |
[5211+] |
| AR5K_IMR_TIM |
[5211+] |
| AR5K_IMR_TXDESC |
TX descriptor request |
| AR5K_IMR_TXDESC |
TX descriptor request |
| AR5K_IMR_TXEOL |
Empty TX descriptor |
| AR5K_IMR_TXEOL |
Empty TX descriptor |
| AR5K_IMR_TXERR |
Transmit error |
| AR5K_IMR_TXERR |
Transmit error |
| AR5K_IMR_TXNOFRM |
No frame transmited (transmit timeout) |
| AR5K_IMR_TXNOFRM |
No frame transmited (transmit timeout) |
| AR5K_IMR_TXOK |
Frame successfuly transmited |
| AR5K_IMR_TXOK |
Frame successfuly transmited |
| AR5K_IMR_TXURN |
Transmit FIFO underrun |
| AR5K_IMR_TXURN |
Transmit FIFO underrun |
| AR5K_INI_RFGAIN_2GHZ |
|
| AR5K_INI_RFGAIN_2GHZ |
|
| AR5K_INI_RFGAIN_5GHZ |
|
| AR5K_INI_RFGAIN_5GHZ |
|
| AR5K_INI_VAL_11A |
|
| AR5K_INI_VAL_11A |
|
| AR5K_INI_VAL_11A_TURBO |
|
| AR5K_INI_VAL_11A_TURBO |
|
| AR5K_INI_VAL_11B |
|
| AR5K_INI_VAL_11B |
|
| AR5K_INI_VAL_11G |
|
| AR5K_INI_VAL_11G |
|
| AR5K_INI_VAL_11G_TURBO |
|
| AR5K_INI_VAL_11G_TURBO |
|
| AR5K_INI_VAL_MAX |
|
| AR5K_INI_VAL_MAX |
|
| AR5K_INI_VAL_XR |
|
| AR5K_INI_VAL_XR |
|
| AR5K_INIT_ACK_CTS_TIMEOUT |
|
| AR5K_INIT_ACK_CTS_TIMEOUT |
|
| AR5K_INIT_ACK_CTS_TIMEOUT_TURBO |
|
| AR5K_INIT_ACK_CTS_TIMEOUT_TURBO |
|
| AR5K_INIT_CARR_SENSE_EN |
|
| AR5K_INIT_CARR_SENSE_EN |
|
| AR5K_INIT_CFG |
|
| AR5K_INIT_CFG |
|
| AR5K_INIT_CFG |
|
| AR5K_INIT_CFG |
|
| AR5K_INIT_CYCRSSI_THR1 |
|
| AR5K_INIT_CYCRSSI_THR1 |
|
| AR5K_INIT_EIFS |
|
| AR5K_INIT_EIFS |
|
| AR5K_INIT_EIFS_TURBO |
|
| AR5K_INIT_EIFS_TURBO |
|
| AR5K_INIT_LG_RETRY |
|
| AR5K_INIT_LG_RETRY |
|
| AR5K_INIT_PROG_IFS |
|
| AR5K_INIT_PROG_IFS |
|
| AR5K_INIT_PROG_IFS_TURBO |
|
| AR5K_INIT_PROG_IFS_TURBO |
|
| AR5K_INIT_PROTO_TIME_CNTRL |
|
| AR5K_INIT_PROTO_TIME_CNTRL |
|
| AR5K_INIT_PROTO_TIME_CNTRL_TURB |
|
| AR5K_INIT_PROTO_TIME_CNTRL_TURB |
|
| AR5K_INIT_SH_RETRY |
|
| AR5K_INIT_SH_RETRY |
|
| AR5K_INIT_SIFS |
|
| AR5K_INIT_SIFS |
|
| AR5K_INIT_SIFS_TURBO |
|
| AR5K_INIT_SIFS_TURBO |
|
| AR5K_INIT_SLG_RETRY |
|
| AR5K_INIT_SLG_RETRY |
|
| AR5K_INIT_SLOT_TIME |
|
| AR5K_INIT_SLOT_TIME |
|
| AR5K_INIT_SLOT_TIME_TURBO |
|
| AR5K_INIT_SLOT_TIME_TURBO |
|
| AR5K_INIT_SSH_RETRY |
|
| AR5K_INIT_SSH_RETRY |
|
| AR5K_INIT_TRANSMIT_LATENCY |
|
| AR5K_INIT_TRANSMIT_LATENCY |
|
| AR5K_INIT_TRANSMIT_LATENCY_TURB |
|
| AR5K_INIT_TRANSMIT_LATENCY_TURB |
|
| AR5K_INIT_TX_LATENCY |
|
| AR5K_INIT_TX_LATENCY |
|
| AR5K_INIT_TX_RETRY |
|
| AR5K_INIT_TX_RETRY |
|
| AR5K_INIT_USEC |
|
| AR5K_INIT_USEC |
|
| AR5K_INIT_USEC_32 |
|
| AR5K_INIT_USEC_32 |
|
| AR5K_INIT_USEC_TURBO |
|
| AR5K_INIT_USEC_TURBO |
|
| AR5K_INTPEND |
|
| AR5K_INTPEND |
|
| AR5K_INTPEND_M |
|
| AR5K_INTPEND_M |
|
| AR5K_ISR |
Register Address [5210] |
| AR5K_ISR |
Register Address [5210] |
| AR5K_ISR_BCNMISC |
'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, |
| AR5K_ISR_BCNMISC |
'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, |
| AR5K_ISR_BMISS |
Beacon missed |
| AR5K_ISR_BMISS |
Beacon missed |
| AR5K_ISR_BNR |
Beacon not ready [5211+] |
| AR5K_ISR_BNR |
Beacon not ready [5211+] |
| AR5K_ISR_BRSSI |
Beacon rssi below threshold (?) |
| AR5K_ISR_BRSSI |
Beacon rssi below threshold (?) |
| AR5K_ISR_DPERR |
Det par Error (?) [5210] |
| AR5K_ISR_DPERR |
Det par Error (?) [5210] |
| AR5K_ISR_GPIO |
GPIO (rf kill) |
| AR5K_ISR_GPIO |
GPIO (rf kill) |
| AR5K_ISR_HIUERR |
Host Interface Unit error [5211+] |
| AR5K_ISR_HIUERR |
Host Interface Unit error [5211+] |
| AR5K_ISR_MCABT |
Master Cycle Abort [5210] |
| AR5K_ISR_MCABT |
Master Cycle Abort [5210] |
| AR5K_ISR_MIB |
Update MIB counters |
| AR5K_ISR_MIB |
Update MIB counters |
| AR5K_ISR_QCBRORN |
QCU CBR overrun [5211+] |
| AR5K_ISR_QCBRORN |
QCU CBR overrun [5211+] |
| AR5K_ISR_QCBRURN |
QCU CBR underrun [5211+] |
| AR5K_ISR_QCBRURN |
QCU CBR underrun [5211+] |
| AR5K_ISR_QTRIG |
QCU scheduling trigger [5211+] |
| AR5K_ISR_QTRIG |
QCU scheduling trigger [5211+] |
| AR5K_ISR_RXCHIRP |
CHIRP Received [5212+] |
| AR5K_ISR_RXCHIRP |
CHIRP Received [5212+] |
| AR5K_ISR_RXDESC |
RX descriptor request |
| AR5K_ISR_RXDESC |
RX descriptor request |
| AR5K_ISR_RXDOPPLER |
Doppler chirp received [5212+] |
| AR5K_ISR_RXDOPPLER |
Doppler chirp received [5212+] |
| AR5K_ISR_RXEOL |
Empty RX descriptor |
| AR5K_ISR_RXEOL |
Empty RX descriptor |
| AR5K_ISR_RXERR |
Receive error |
| AR5K_ISR_RXERR |
Receive error |
| AR5K_ISR_RXKCM |
RX Key cache miss |
| AR5K_ISR_RXKCM |
RX Key cache miss |
| AR5K_ISR_RXNOFRM |
No frame received (receive timeout) |
| AR5K_ISR_RXNOFRM |
No frame received (receive timeout) |
| AR5K_ISR_RXOK |
Frame successfuly recieved |
| AR5K_ISR_RXOK |
Frame successfuly recieved |
| AR5K_ISR_RXORN |
Receive FIFO overrun |
| AR5K_ISR_RXORN |
Receive FIFO overrun |
| AR5K_ISR_RXPHY |
PHY error |
| AR5K_ISR_RXPHY |
PHY error |
| AR5K_ISR_SSERR |
Signaled System Error [5210] |
| AR5K_ISR_SSERR |
Signaled System Error [5210] |
| AR5K_ISR_SWBA |
Software beacon alert |
| AR5K_ISR_SWBA |
Software beacon alert |
| AR5K_ISR_SWI |
Software interrupt |
| AR5K_ISR_SWI |
Software interrupt |
| AR5K_ISR_TIM |
[5211+] |
| AR5K_ISR_TIM |
[5211+] |
| AR5K_ISR_TXDESC |
TX descriptor request |
| AR5K_ISR_TXDESC |
TX descriptor request |
| AR5K_ISR_TXEOL |
Empty TX descriptor |
| AR5K_ISR_TXEOL |
Empty TX descriptor |
| AR5K_ISR_TXERR |
Transmit error |
| AR5K_ISR_TXERR |
Transmit error |
| AR5K_ISR_TXNOFRM |
No frame transmited (transmit timeout) |
| AR5K_ISR_TXNOFRM |
No frame transmited (transmit timeout) |
| AR5K_ISR_TXOK |
Frame successfuly transmited |
| AR5K_ISR_TXOK |
Frame successfuly transmited |
| AR5K_ISR_TXURN |
Transmit FIFO underrun |
| AR5K_ISR_TXURN |
Transmit FIFO underrun |
| AR5K_KEYCACHE_SIZE |
|
| AR5K_KEYCACHE_SIZE |
|
| AR5K_KEYTABLE(_n) |
|
| AR5K_KEYTABLE(_n) |
|
| AR5K_KEYTABLE_0_5210 |
|
| AR5K_KEYTABLE_0_5210 |
|
| AR5K_KEYTABLE_0_5211 |
|
| AR5K_KEYTABLE_0_5211 |
|
| AR5K_KEYTABLE_5210(_n) |
|
| AR5K_KEYTABLE_5210(_n) |
|
| AR5K_KEYTABLE_5211(_n) |
|
| AR5K_KEYTABLE_5211(_n) |
|
| AR5K_KEYTABLE_ANTENNA |
[5212+] |
| AR5K_KEYTABLE_ANTENNA |
[5212+] |
| AR5K_KEYTABLE_MAC0(_n) |
|
| AR5K_KEYTABLE_MAC0(_n) |
|
| AR5K_KEYTABLE_MAC1(_n) |
|
| AR5K_KEYTABLE_MAC1(_n) |
|
| AR5K_KEYTABLE_MIC_OFFSET |
|
| AR5K_KEYTABLE_MIC_OFFSET |
|
| AR5K_KEYTABLE_OFF(_n, x) |
|
| AR5K_KEYTABLE_OFF(_n, x) |
|
| AR5K_KEYTABLE_SIZE |
|
| AR5K_KEYTABLE_SIZE |
|
| AR5K_KEYTABLE_SIZE_5210 |
|
| AR5K_KEYTABLE_SIZE_5210 |
|
| AR5K_KEYTABLE_SIZE_5211 |
|
| AR5K_KEYTABLE_SIZE_5211 |
|
| AR5K_KEYTABLE_TYPE(_n) |
|
| AR5K_KEYTABLE_TYPE(_n) |
|
| AR5K_KEYTABLE_TYPE_104 |
|
| AR5K_KEYTABLE_TYPE_104 |
|
| AR5K_KEYTABLE_TYPE_128 |
|
| AR5K_KEYTABLE_TYPE_128 |
|
| AR5K_KEYTABLE_TYPE_40 |
|
| AR5K_KEYTABLE_TYPE_40 |
|
| AR5K_KEYTABLE_TYPE_AES |
[5211+] |
| AR5K_KEYTABLE_TYPE_AES |
[5211+] |
| AR5K_KEYTABLE_TYPE_CCM |
[5212+] |
| AR5K_KEYTABLE_TYPE_CCM |
[5212+] |
| AR5K_KEYTABLE_TYPE_NULL |
[5211+] |
| AR5K_KEYTABLE_TYPE_NULL |
[5211+] |
| AR5K_KEYTABLE_TYPE_TKIP |
[5212+] |
| AR5K_KEYTABLE_TYPE_TKIP |
[5212+] |
| AR5K_KEYTABLE_VALID |
|
| AR5K_KEYTABLE_VALID |
|
| AR5K_LAST_TSTP |
|
| AR5K_LAST_TSTP |
|
| AR5K_LOW_ID(_a) |
|
| AR5K_LOW_ID(_a) |
|
| AR5K_MAX_GPIO |
|
| AR5K_MAX_GPIO |
|
| AR5K_MAX_RATES |
|
| AR5K_MAX_RATES |
|
| AR5K_MAX_RF_BANKS |
|
| AR5K_MAX_RF_BANKS |
|
| AR5K_MCAST_FILTER0 |
|
| AR5K_MCAST_FILTER0 |
|
| AR5K_MCAST_FILTER0_5210 |
|
| AR5K_MCAST_FILTER0_5210 |
|
| AR5K_MCAST_FILTER0_5211 |
|
| AR5K_MCAST_FILTER0_5211 |
|
| AR5K_MCAST_FILTER1 |
|
| AR5K_MCAST_FILTER1 |
|
| AR5K_MCAST_FILTER1_5210 |
|
| AR5K_MCAST_FILTER1_5210 |
|
| AR5K_MCAST_FILTER1_5211 |
|
| AR5K_MCAST_FILTER1_5211 |
|
| AR5K_MIBC |
Register Address |
| AR5K_MIBC |
Register Address |
| AR5K_MIBC_CMC |
Clean MIB Counters |
| AR5K_MIBC_CMC |
Clean MIB Counters |
| AR5K_MIBC_COW |
Warn test indicator |
| AR5K_MIBC_COW |
Warn test indicator |
| AR5K_MIBC_FMC |
Freeze MIB Counters |
| AR5K_MIBC_FMC |
Freeze MIB Counters |
| AR5K_MIBC_MCS |
MIB counter strobe |
| AR5K_MIBC_MCS |
MIB counter strobe |
| AR5K_MIC_QOS_CTL |
Register Address |
| AR5K_MIC_QOS_CTL |
Register Address |
| AR5K_MIC_QOS_CTL_MQ_EN |
Enable MIC QoS |
| AR5K_MIC_QOS_CTL_MQ_EN |
Enable MIC QoS |
| AR5K_MIC_QOS_CTL_OFF(_n) |
|
| AR5K_MIC_QOS_CTL_OFF(_n) |
|
| AR5K_MIC_QOS_SEL |
|
| AR5K_MIC_QOS_SEL |
|
| AR5K_MIC_QOS_SEL_OFF(_n) |
|
| AR5K_MIC_QOS_SEL_OFF(_n) |
|
| AR5K_MISC |
Register Address |
| AR5K_MISC |
Register Address |
| AR5K_MISC_DMA_OBS_M |
|
| AR5K_MISC_DMA_OBS_M |
|
| AR5K_MISC_DMA_OBS_S |
|
| AR5K_MISC_DMA_OBS_S |
|
| AR5K_MISC_LED_BLINK |
[5210] |
| AR5K_MISC_LED_BLINK |
[5210] |
| AR5K_MISC_LED_DECAY |
[5210] |
| AR5K_MISC_LED_DECAY |
[5210] |
| AR5K_MISC_MAC_OBS_LSB_M |
|
| AR5K_MISC_MAC_OBS_LSB_M |
|
| AR5K_MISC_MAC_OBS_LSB_S |
|
| AR5K_MISC_MAC_OBS_LSB_S |
|
| AR5K_MISC_MAC_OBS_MSB_M |
|
| AR5K_MISC_MAC_OBS_MSB_M |
|
| AR5K_MISC_MAC_OBS_MSB_S |
|
| AR5K_MISC_MAC_OBS_MSB_S |
|
| AR5K_MISC_MISC_OBS_M |
|
| AR5K_MISC_MISC_OBS_M |
|
| AR5K_MISC_MISC_OBS_S |
|
| AR5K_MISC_MISC_OBS_S |
|
| AR5K_MISC_MODE |
Register Address |
| AR5K_MISC_MODE |
Register Address |
| AR5K_MISC_MODE_ACKSIFS_MEM |
ACK SIFS memory (?) |
| AR5K_MISC_MODE_ACKSIFS_MEM |
ACK SIFS memory (?) |
| AR5K_MISC_MODE_COMBINED_MIC |
use rx/tx MIC key |
| AR5K_MISC_MODE_COMBINED_MIC |
use rx/tx MIC key |
| AR5K_MISC_MODE_FBSSID_MATCH |
Force BSSID match |
| AR5K_MISC_MODE_FBSSID_MATCH |
Force BSSID match |
| AR5K_NAV |
|
| AR5K_NAV |
|
| AR5K_NAV_5210 |
|
| AR5K_NAV_5210 |
|
| AR5K_NAV_5211 |
|
| AR5K_NAV_5211 |
|
| AR5K_NODCU_RETRY_LMT |
Register Address |
| AR5K_NODCU_RETRY_LMT |
Register Address |
| AR5K_NODCU_RETRY_LMT_CW_MIN |
Minimum contention window mask |
| AR5K_NODCU_RETRY_LMT_CW_MIN |
Minimum contention window mask |
| AR5K_NODCU_RETRY_LMT_CW_MIN_S |
|
| AR5K_NODCU_RETRY_LMT_CW_MIN_S |
|
| AR5K_NODCU_RETRY_LMT_LG_RETRY |
Long retry mask |
| AR5K_NODCU_RETRY_LMT_LG_RETRY |
Long retry mask |
| AR5K_NODCU_RETRY_LMT_LG_RETRY_S |
|
| AR5K_NODCU_RETRY_LMT_LG_RETRY_S |
|
| AR5K_NODCU_RETRY_LMT_SH_RETRY |
Short retry limit mask |
| AR5K_NODCU_RETRY_LMT_SH_RETRY |
Short retry limit mask |
| AR5K_NODCU_RETRY_LMT_SH_RETRY_S |
|
| AR5K_NODCU_RETRY_LMT_SH_RETRY_S |
|
| AR5K_NODCU_RETRY_LMT_SLG_RETRY |
Station long retry limit mask |
| AR5K_NODCU_RETRY_LMT_SLG_RETRY |
Station long retry limit mask |
| AR5K_NODCU_RETRY_LMT_SLG_RETRY_ |
|
| AR5K_NODCU_RETRY_LMT_SLG_RETRY_ |
|
| AR5K_NODCU_RETRY_LMT_SSH_RETRY |
Station short retry limit mask |
| AR5K_NODCU_RETRY_LMT_SSH_RETRY |
Station short retry limit mask |
| AR5K_NODCU_RETRY_LMT_SSH_RETRY_ |
|
| AR5K_NODCU_RETRY_LMT_SSH_RETRY_ |
|
| AR5K_NOQCU_TXDP0 |
Queue 0 - data |
| AR5K_NOQCU_TXDP0 |
Queue 0 - data |
| AR5K_NOQCU_TXDP1 |
Queue 1 - beacons |
| AR5K_NOQCU_TXDP1 |
Queue 1 - beacons |
| AR5K_NUM_GPIO |
|
| AR5K_NUM_GPIO |
|
| AR5K_OFDM_FIL_CNT |
|
| AR5K_OFDM_FIL_CNT |
|
| AR5K_PCICFG |
Register Address |
| AR5K_PCICFG |
Register Address |
| AR5K_PCICFG_BUS_SEL |
Mask for "bus select" [5211+] (?) |
| AR5K_PCICFG_BUS_SEL |
Mask for "bus select" [5211+] (?) |
| AR5K_PCICFG_CBEFIX_DIS |
Disable CBE fix |
| AR5K_PCICFG_CBEFIX_DIS |
Disable CBE fix |
| AR5K_PCICFG_CLKRUNEN |
CLKRUN enable [5211+] |
| AR5K_PCICFG_CLKRUNEN |
CLKRUN enable [5211+] |
| AR5K_PCICFG_EEAE |
Eeprom access enable [5210] |
| AR5K_PCICFG_EEAE |
Eeprom access enable [5210] |
| AR5K_PCICFG_EESIZE |
Mask for EEPROM size [5211+] |
| AR5K_PCICFG_EESIZE |
Mask for EEPROM size [5211+] |
| AR5K_PCICFG_EESIZE_16K |
16K |
| AR5K_PCICFG_EESIZE_16K |
16K |
| AR5K_PCICFG_EESIZE_4K |
4K |
| AR5K_PCICFG_EESIZE_4K |
4K |
| AR5K_PCICFG_EESIZE_8K |
8K |
| AR5K_PCICFG_EESIZE_8K |
8K |
| AR5K_PCICFG_EESIZE_FAIL |
Failed to get size [5211+] |
| AR5K_PCICFG_EESIZE_FAIL |
Failed to get size [5211+] |
| AR5K_PCICFG_EESIZE_S |
|
| AR5K_PCICFG_EESIZE_S |
|
| AR5K_PCICFG_LED |
Led status [5211+] |
| AR5K_PCICFG_LED |
Led status [5211+] |
| AR5K_PCICFG_LED_ASSOC |
Associated |
| AR5K_PCICFG_LED_ASSOC |
Associated |
| AR5K_PCICFG_LED_BCTL |
Led blink (?) [5210] |
| AR5K_PCICFG_LED_BCTL |
Led blink (?) [5210] |
| AR5K_PCICFG_LED_NONE |
Default [5211+] |
| AR5K_PCICFG_LED_NONE |
Default [5211+] |
| AR5K_PCICFG_LED_PEND |
Scan / Auth pending |
| AR5K_PCICFG_LED_PEND |
Scan / Auth pending |
| AR5K_PCICFG_LEDBLINK |
Led blink rate |
| AR5K_PCICFG_LEDBLINK |
Led blink rate |
| AR5K_PCICFG_LEDBLINK_S |
|
| AR5K_PCICFG_LEDBLINK_S |
|
| AR5K_PCICFG_LEDMODE |
Ledmode [5211+] |
| AR5K_PCICFG_LEDMODE |
Ledmode [5211+] |
| AR5K_PCICFG_LEDMODE_PROM |
Default mode (blink on any traffic) [5211+] |
| AR5K_PCICFG_LEDMODE_PROM |
Default mode (blink on any traffic) [5211+] |
| AR5K_PCICFG_LEDMODE_PROP |
Blink on standard traffic [5211+] |
| AR5K_PCICFG_LEDMODE_PROP |
Blink on standard traffic [5211+] |
| AR5K_PCICFG_LEDMODE_PWR |
Some other blinking mode (?) [5211+] |
| AR5K_PCICFG_LEDMODE_PWR |
Some other blinking mode (?) [5211+] |
| AR5K_PCICFG_LEDMODE_RAND |
Random blinking (?) [5211+] |
| AR5K_PCICFG_LEDMODE_RAND |
Random blinking (?) [5211+] |
| AR5K_PCICFG_LEDSLOW |
Slowest led blink rate [5211+] |
| AR5K_PCICFG_LEDSLOW |
Slowest led blink rate [5211+] |
| AR5K_PCICFG_LEDSTATE |
|
| AR5K_PCICFG_LEDSTATE |
|
| AR5K_PCICFG_RETRY_FIX |
Enable pci core retry fix |
| AR5K_PCICFG_RETRY_FIX |
Enable pci core retry fix |
| AR5K_PCICFG_SL_INPEN |
Sleep even whith pending interrupts |
| AR5K_PCICFG_SL_INPEN |
Sleep even whith pending interrupts |
| AR5K_PCICFG_SL_INTEN |
Enable interrupts when asleep |
| AR5K_PCICFG_SL_INTEN |
Enable interrupts when asleep |
| AR5K_PCICFG_SLEEP_CLOCK_EN |
Enable sleep clock |
| AR5K_PCICFG_SLEEP_CLOCK_EN |
Enable sleep clock |
| AR5K_PCICFG_SLEEP_CLOCK_RATE |
Sleep clock rate |
| AR5K_PCICFG_SLEEP_CLOCK_RATE |
Sleep clock rate |
| AR5K_PCICFG_SLEEP_CLOCK_RATE_S |
|
| AR5K_PCICFG_SLEEP_CLOCK_RATE_S |
|
| AR5K_PCICFG_SPWR_DN |
Mask for power status |
| AR5K_PCICFG_SPWR_DN |
Mask for power status |
| AR5K_PCIE_PM_CTL |
Register address |
| AR5K_PCIE_PM_CTL |
Register address |
| AR5K_PCIE_PM_CTL_AUX_PWR_DET |
Aux power detect |
| AR5K_PCIE_PM_CTL_AUX_PWR_DET |
Aux power detect |
| AR5K_PCIE_PM_CTL_L0_L0S_CLEAR |
Clear L0 and L0S counters |
| AR5K_PCIE_PM_CTL_L0_L0S_CLEAR |
Clear L0 and L0S counters |
| AR5K_PCIE_PM_CTL_L0_L0S_EN |
Start L0 nd L0S counters |
| AR5K_PCIE_PM_CTL_L0_L0S_EN |
Start L0 nd L0S counters |
| AR5K_PCIE_PM_CTL_L1_WHEN_D2 |
enable PCIe core enter L1 |
| AR5K_PCIE_PM_CTL_L1_WHEN_D2 |
enable PCIe core enter L1 |
| AR5K_PCIE_PM_CTL_LDRESET_EN |
Enable reset when link goes |
| AR5K_PCIE_PM_CTL_LDRESET_EN |
Enable reset when link goes |
| AR5K_PCIE_PM_CTL_PME_CLEAR |
Clear PME |
| AR5K_PCIE_PM_CTL_PME_CLEAR |
Clear PME |
| AR5K_PCIE_PM_CTL_PME_EN |
PME Enable |
| AR5K_PCIE_PM_CTL_PME_EN |
PME Enable |
| AR5K_PCIE_PM_CTL_PSM_D0 |
|
| AR5K_PCIE_PM_CTL_PSM_D0 |
|
| AR5K_PCIE_PM_CTL_PSM_D1 |
|
| AR5K_PCIE_PM_CTL_PSM_D1 |
|
| AR5K_PCIE_PM_CTL_PSM_D2 |
|
| AR5K_PCIE_PM_CTL_PSM_D2 |
|
| AR5K_PCIE_PM_CTL_PSM_D3 |
|
| AR5K_PCIE_PM_CTL_PSM_D3 |
|
| AR5K_PCIE_SERDES |
|
| AR5K_PCIE_SERDES |
|
| AR5K_PCIE_SERDES_RESET |
|
| AR5K_PCIE_SERDES_RESET |
|
| AR5K_PCIE_WAEN |
|
| AR5K_PCIE_WAEN |
|
| AR5K_PCU_MAX |
|
| AR5K_PCU_MAX |
|
| AR5K_PCU_MIN |
|
| AR5K_PCU_MIN |
|
| AR5K_PHY(_n) |
|
| AR5K_PHY(_n) |
|
| AR5K_PHY_ACT |
Register Address |
| AR5K_PHY_ACT |
Register Address |
| AR5K_PHY_ACT_DISABLE |
Deactivate PHY |
| AR5K_PHY_ACT_DISABLE |
Deactivate PHY |
| AR5K_PHY_ACT_ENABLE |
Activate PHY |
| AR5K_PHY_ACT_ENABLE |
Activate PHY |
| AR5K_PHY_ADC_CTL |
|
| AR5K_PHY_ADC_CTL |
|
| AR5K_PHY_ADC_CTL_INBUFGAIN_OFF |
|
| AR5K_PHY_ADC_CTL_INBUFGAIN_OFF |
|
| AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_ |
|
| AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_ |
|
| AR5K_PHY_ADC_CTL_INBUFGAIN_ON |
|
| AR5K_PHY_ADC_CTL_INBUFGAIN_ON |
|
| AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S |
|
| AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S |
|
| AR5K_PHY_ADC_CTL_PWD_ADC_OFF |
|
| AR5K_PHY_ADC_CTL_PWD_ADC_OFF |
|
| AR5K_PHY_ADC_CTL_PWD_BAND_GAP_O |
|
| AR5K_PHY_ADC_CTL_PWD_BAND_GAP_O |
|
| AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
|
| AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
|
| AR5K_PHY_ADC_TEST |
|
| AR5K_PHY_ADC_TEST |
|
| AR5K_PHY_ADC_TEST_I |
|
| AR5K_PHY_ADC_TEST_I |
|
| AR5K_PHY_ADC_TEST_Q |
|
| AR5K_PHY_ADC_TEST_Q |
|
| AR5K_PHY_ADCSAT |
|
| AR5K_PHY_ADCSAT |
|
| AR5K_PHY_ADCSAT_ICNT |
|
| AR5K_PHY_ADCSAT_ICNT |
|
| AR5K_PHY_ADCSAT_ICNT_S |
|
| AR5K_PHY_ADCSAT_ICNT_S |
|
| AR5K_PHY_ADCSAT_THR |
|
| AR5K_PHY_ADCSAT_THR |
|
| AR5K_PHY_ADCSAT_THR_S |
|
| AR5K_PHY_ADCSAT_THR_S |
|
| AR5K_PHY_AGC |
Register Address |
| AR5K_PHY_AGC |
Register Address |
| AR5K_PHY_AGC_DISABLE |
Disable AGC to A2 (?) |
| AR5K_PHY_AGC_DISABLE |
Disable AGC to A2 (?) |
| AR5K_PHY_AGCCOARSE |
Register Address |
| AR5K_PHY_AGCCOARSE |
Register Address |
| AR5K_PHY_AGCCOARSE_HI |
AGC Coarse high |
| AR5K_PHY_AGCCOARSE_HI |
AGC Coarse high |
| AR5K_PHY_AGCCOARSE_HI_S |
|
| AR5K_PHY_AGCCOARSE_HI_S |
|
| AR5K_PHY_AGCCOARSE_LO |
AGC Coarse low |
| AR5K_PHY_AGCCOARSE_LO |
AGC Coarse low |
| AR5K_PHY_AGCCOARSE_LO_S |
|
| AR5K_PHY_AGCCOARSE_LO_S |
|
| AR5K_PHY_AGCCTL |
Register address |
| AR5K_PHY_AGCCTL |
Register address |
| AR5K_PHY_AGCCTL_CAL |
Enable PHY calibration |
| AR5K_PHY_AGCCTL_CAL |
Enable PHY calibration |
| AR5K_PHY_AGCCTL_NF |
Enable Noise Floor calibration |
| AR5K_PHY_AGCCTL_NF |
Enable Noise Floor calibration |
| AR5K_PHY_AGCCTL_NF_EN |
Enable nf calibration to happen (?) |
| AR5K_PHY_AGCCTL_NF_EN |
Enable nf calibration to happen (?) |
| AR5K_PHY_AGCCTL_NF_NOUPDATE |
Don't update nf automaticaly |
| AR5K_PHY_AGCCTL_NF_NOUPDATE |
Don't update nf automaticaly |
| AR5K_PHY_ANT_CTL |
Register Address |
| AR5K_PHY_ANT_CTL |
Register Address |
| AR5K_PHY_ANT_CTL_HITUNE5 |
Hitune5 (?) |
| AR5K_PHY_ANT_CTL_HITUNE5 |
Hitune5 (?) |
| AR5K_PHY_ANT_CTL_SECTORED_ANT |
Sectored Antenna |
| AR5K_PHY_ANT_CTL_SECTORED_ANT |
Sectored Antenna |
| AR5K_PHY_ANT_CTL_SWTABLE_IDLE |
Switch table idle (?) |
| AR5K_PHY_ANT_CTL_SWTABLE_IDLE |
Switch table idle (?) |
| AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S |
|
| AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S |
|
| AR5K_PHY_ANT_CTL_TXRX_EN |
Enable TX/RX (?) |
| AR5K_PHY_ANT_CTL_TXRX_EN |
Enable TX/RX (?) |
| AR5K_PHY_ANT_SWITCH_TABLE_0 |
|
| AR5K_PHY_ANT_SWITCH_TABLE_0 |
|
| AR5K_PHY_ANT_SWITCH_TABLE_1 |
|
| AR5K_PHY_ANT_SWITCH_TABLE_1 |
|
| AR5K_PHY_BAD_TX_RATE |
|
| AR5K_PHY_BAD_TX_RATE |
|
| AR5K_PHY_BASE |
|
| AR5K_PHY_BASE |
|
| AR5K_PHY_BIN_MASK_1 |
|
| AR5K_PHY_BIN_MASK_1 |
|
| AR5K_PHY_BIN_MASK_2 |
|
| AR5K_PHY_BIN_MASK_2 |
|
| AR5K_PHY_BIN_MASK_3 |
|
| AR5K_PHY_BIN_MASK_3 |
|
| AR5K_PHY_BIN_MASK_CTL |
|
| AR5K_PHY_BIN_MASK_CTL |
|
| AR5K_PHY_BIN_MASK_CTL_MASK_4 |
|
| AR5K_PHY_BIN_MASK_CTL_MASK_4 |
|
| AR5K_PHY_BIN_MASK_CTL_MASK_4_S |
|
| AR5K_PHY_BIN_MASK_CTL_MASK_4_S |
|
| AR5K_PHY_BIN_MASK_CTL_RATE |
|
| AR5K_PHY_BIN_MASK_CTL_RATE |
|
| AR5K_PHY_BIN_MASK_CTL_RATE_S |
|
| AR5K_PHY_BIN_MASK_CTL_RATE_S |
|
| AR5K_PHY_BIN_MASK2_1 |
|
| AR5K_PHY_BIN_MASK2_1 |
|
| AR5K_PHY_BIN_MASK2_2 |
|
| AR5K_PHY_BIN_MASK2_2 |
|
| AR5K_PHY_BIN_MASK2_3 |
|
| AR5K_PHY_BIN_MASK2_3 |
|
| AR5K_PHY_BIN_MASK2_4 |
|
| AR5K_PHY_BIN_MASK2_4 |
|
| AR5K_PHY_BIN_MASK2_4_MASK_4 |
|
| AR5K_PHY_BIN_MASK2_4_MASK_4 |
|
| AR5K_PHY_BIN_MASK2_4_MASK_4_S |
|
| AR5K_PHY_BIN_MASK2_4_MASK_4_S |
|
| AR5K_PHY_BLUETOOTH |
|
| AR5K_PHY_BLUETOOTH |
|
| AR5K_PHY_CCK_CROSSCORR |
|
| AR5K_PHY_CCK_CROSSCORR |
|
| AR5K_PHY_CCK_CROSSCORR_WEAK_SIG |
|
| AR5K_PHY_CCK_CROSSCORR_WEAK_SIG |
|
| AR5K_PHY_CCK_CROSSCORR_WEAK_SIG |
|
| AR5K_PHY_CCK_CROSSCORR_WEAK_SIG |
|
| AR5K_PHY_CCK_RX_CTL_4 |
|
| AR5K_PHY_CCK_RX_CTL_4 |
|
| AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_ |
|
| AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_ |
|
| AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_ |
|
| AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_ |
|
| AR5K_PHY_CCKTXCTK_DAC_SCALE |
|
| AR5K_PHY_CCKTXCTK_DAC_SCALE |
|
| AR5K_PHY_CCKTXCTL |
|
| AR5K_PHY_CCKTXCTL |
|
| AR5K_PHY_CCKTXCTL_JAPAN |
|
| AR5K_PHY_CCKTXCTL_JAPAN |
|
| AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS |
|
| AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS |
|
| AR5K_PHY_CCKTXCTL_WORLD |
|
| AR5K_PHY_CCKTXCTL_WORLD |
|
| AR5K_PHY_CHAN_STATUS |
|
| AR5K_PHY_CHAN_STATUS |
|
| AR5K_PHY_CHAN_STATUS_BT_ACT |
|
| AR5K_PHY_CHAN_STATUS_BT_ACT |
|
| AR5K_PHY_CHAN_STATUS_RX_CLR_MAC |
|
| AR5K_PHY_CHAN_STATUS_RX_CLR_MAC |
|
| AR5K_PHY_CHAN_STATUS_RX_CLR_PAP |
|
| AR5K_PHY_CHAN_STATUS_RX_CLR_PAP |
|
| AR5K_PHY_CHAN_STATUS_RX_CLR_RAW |
|
| AR5K_PHY_CHAN_STATUS_RX_CLR_RAW |
|
| AR5K_PHY_CHIP_ID |
|
| AR5K_PHY_CHIP_ID |
|
| AR5K_PHY_CTL |
Register Address |
| AR5K_PHY_CTL |
Register Address |
| AR5K_PHY_CTL_GEN_SCRAMBLER |
Generate scrambler |
| AR5K_PHY_CTL_GEN_SCRAMBLER |
Generate scrambler |
| AR5K_PHY_CTL_LATE_TX_SIG_SYM |
Late tx signal symbol (?) |
| AR5K_PHY_CTL_LATE_TX_SIG_SYM |
Late tx signal symbol (?) |
| AR5K_PHY_CTL_LOW_FREQ_SLE_EN |
Enable low freq sleep |
| AR5K_PHY_CTL_LOW_FREQ_SLE_EN |
Enable low freq sleep |
| AR5K_PHY_CTL_RX_ANT_SEL |
RX antenna select |
| AR5K_PHY_CTL_RX_ANT_SEL |
RX antenna select |
| AR5K_PHY_CTL_RX_ANT_STATIC |
Static RX antenna |
| AR5K_PHY_CTL_RX_ANT_STATIC |
Static RX antenna |
| AR5K_PHY_CTL_RX_DRAIN_RATE |
RX drain rate (?) |
| AR5K_PHY_CTL_RX_DRAIN_RATE |
RX drain rate (?) |
| AR5K_PHY_CTL_TX_ANT_SEL |
TX antenna select |
| AR5K_PHY_CTL_TX_ANT_SEL |
TX antenna select |
| AR5K_PHY_CTL_TX_ANT_STATIC |
Static TX antenna |
| AR5K_PHY_CTL_TX_ANT_STATIC |
Static TX antenna |
| AR5K_PHY_CURRENT_RSSI |
|
| AR5K_PHY_CURRENT_RSSI |
|
| AR5K_PHY_DAC_TEST |
|
| AR5K_PHY_DAC_TEST |
|
| AR5K_PHY_DAC_TEST_I |
|
| AR5K_PHY_DAC_TEST_I |
|
| AR5K_PHY_DAC_TEST_Q |
|
| AR5K_PHY_DAC_TEST_Q |
|
| AR5K_PHY_DAG_CCK_CTL |
|
| AR5K_PHY_DAG_CCK_CTL |
|
| AR5K_PHY_DAG_CCK_CTL_EN_RSSI_TH |
|
| AR5K_PHY_DAG_CCK_CTL_EN_RSSI_TH |
|
| AR5K_PHY_DAG_CCK_CTL_RSSI_THR |
|
| AR5K_PHY_DAG_CCK_CTL_RSSI_THR |
|
| AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S |
|
| AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S |
|
| AR5K_PHY_DESIRED_SIZE |
Register Address |
| AR5K_PHY_DESIRED_SIZE |
Register Address |
| AR5K_PHY_DESIRED_SIZE_ADC |
ADC desired size |
| AR5K_PHY_DESIRED_SIZE_ADC |
ADC desired size |
| AR5K_PHY_DESIRED_SIZE_ADC_S |
|
| AR5K_PHY_DESIRED_SIZE_ADC_S |
|
| AR5K_PHY_DESIRED_SIZE_PGA |
PGA desired size |
| AR5K_PHY_DESIRED_SIZE_PGA |
PGA desired size |
| AR5K_PHY_DESIRED_SIZE_PGA_S |
|
| AR5K_PHY_DESIRED_SIZE_PGA_S |
|
| AR5K_PHY_DESIRED_SIZE_TOT |
Total desired size |
| AR5K_PHY_DESIRED_SIZE_TOT |
Total desired size |
| AR5K_PHY_DESIRED_SIZE_TOT_S |
|
| AR5K_PHY_DESIRED_SIZE_TOT_S |
|
| AR5K_PHY_ERR_FIL |
|
| AR5K_PHY_ERR_FIL |
|
| AR5K_PHY_ERR_FIL_CCK |
CCK false detect (ANI) |
| AR5K_PHY_ERR_FIL_CCK |
CCK false detect (ANI) |
| AR5K_PHY_ERR_FIL_OFDM |
OFDM false detect (ANI) |
| AR5K_PHY_ERR_FIL_OFDM |
OFDM false detect (ANI) |
| AR5K_PHY_ERR_FIL_RADAR |
Radar signal |
| AR5K_PHY_ERR_FIL_RADAR |
Radar signal |
| AR5K_PHY_FAST_ADC |
|
| AR5K_PHY_FAST_ADC |
|
| AR5K_PHY_FAST_ANT_DIV |
|
| AR5K_PHY_FAST_ANT_DIV |
|
| AR5K_PHY_FAST_ANT_DIV_EN |
|
| AR5K_PHY_FAST_ANT_DIV_EN |
|
| AR5K_PHY_FRAME_CTL |
|
| AR5K_PHY_FRAME_CTL |
|
| AR5K_PHY_FRAME_CTL_5210 |
|
| AR5K_PHY_FRAME_CTL_5210 |
|
| AR5K_PHY_FRAME_CTL_5211 |
|
| AR5K_PHY_FRAME_CTL_5211 |
|
| AR5K_PHY_FRAME_CTL_EMU |
|
| AR5K_PHY_FRAME_CTL_EMU |
|
| AR5K_PHY_FRAME_CTL_EMU_S |
|
| AR5K_PHY_FRAME_CTL_EMU_S |
|
| AR5K_PHY_FRAME_CTL_ILLLEN_ERR |
Illegal length |
| AR5K_PHY_FRAME_CTL_ILLLEN_ERR |
Illegal length |
| AR5K_PHY_FRAME_CTL_ILLRATE_ERR |
Illegal rate |
| AR5K_PHY_FRAME_CTL_ILLRATE_ERR |
Illegal rate |
| AR5K_PHY_FRAME_CTL_INI |
|
| AR5K_PHY_FRAME_CTL_INI |
|
| AR5K_PHY_FRAME_CTL_PARITY_ERR |
Parity error |
| AR5K_PHY_FRAME_CTL_PARITY_ERR |
Parity error |
| AR5K_PHY_FRAME_CTL_PREP_CHINFO |
Prepend chan info |
| AR5K_PHY_FRAME_CTL_PREP_CHINFO |
Prepend chan info |
| AR5K_PHY_FRAME_CTL_SERVICE_ERR |
|
| AR5K_PHY_FRAME_CTL_SERVICE_ERR |
|
| AR5K_PHY_FRAME_CTL_TIMING_ERR |
PHY timing error |
| AR5K_PHY_FRAME_CTL_TIMING_ERR |
PHY timing error |
| AR5K_PHY_FRAME_CTL_TX_CLIP |
Mask for tx clip (?) |
| AR5K_PHY_FRAME_CTL_TX_CLIP |
Mask for tx clip (?) |
| AR5K_PHY_FRAME_CTL_TX_CLIP_S |
|
| AR5K_PHY_FRAME_CTL_TX_CLIP_S |
|
| AR5K_PHY_FRAME_CTL_TXURN_ERR |
TX underrun |
| AR5K_PHY_FRAME_CTL_TXURN_ERR |
TX underrun |
| AR5K_PHY_GAIN |
Register Address |
| AR5K_PHY_GAIN |
Register Address |
| AR5K_PHY_GAIN_2GHZ |
|
| AR5K_PHY_GAIN_2GHZ |
|
| AR5K_PHY_GAIN_2GHZ_INI_5111 |
|
| AR5K_PHY_GAIN_2GHZ_INI_5111 |
|
| AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX |
|
| AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX |
|
| AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_ |
|
| AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_ |
|
| AR5K_PHY_GAIN_OFFSET |
Register Address |
| AR5K_PHY_GAIN_OFFSET |
Register Address |
| AR5K_PHY_GAIN_OFFSET_RXTX_FLAG |
RX-TX flag (?) |
| AR5K_PHY_GAIN_OFFSET_RXTX_FLAG |
RX-TX flag (?) |
| AR5K_PHY_GAIN_TXRX_ATTEN |
TX-RX Attenuation |
| AR5K_PHY_GAIN_TXRX_ATTEN |
TX-RX Attenuation |
| AR5K_PHY_GAIN_TXRX_ATTEN_S |
|
| AR5K_PHY_GAIN_TXRX_ATTEN_S |
|
| AR5K_PHY_GAIN_TXRX_RF_MAX |
|
| AR5K_PHY_GAIN_TXRX_RF_MAX |
|
| AR5K_PHY_GAIN_TXRX_RF_MAX_S |
|
| AR5K_PHY_GAIN_TXRX_RF_MAX_S |
|
| AR5K_PHY_HEAVY_CLIP_ENABLE |
|
| AR5K_PHY_HEAVY_CLIP_ENABLE |
|
| AR5K_PHY_IQ |
Register Address |
| AR5K_PHY_IQ |
Register Address |
| AR5K_PHY_IQ_CAL_NUM_LOG_MAX |
Mask for max number of samples in log scale |
| AR5K_PHY_IQ_CAL_NUM_LOG_MAX |
Mask for max number of samples in log scale |
| AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S |
|
| AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S |
|
| AR5K_PHY_IQ_CHAN_MASK_EN |
Enable channel mask (?) |
| AR5K_PHY_IQ_CHAN_MASK_EN |
Enable channel mask (?) |
| AR5K_PHY_IQ_CORR_ENABLE |
Enable i/q correction |
| AR5K_PHY_IQ_CORR_ENABLE |
Enable i/q correction |
| AR5K_PHY_IQ_CORR_Q_I_COFF |
Mask for i correction info |
| AR5K_PHY_IQ_CORR_Q_I_COFF |
Mask for i correction info |
| AR5K_PHY_IQ_CORR_Q_I_COFF_S |
|
| AR5K_PHY_IQ_CORR_Q_I_COFF_S |
|
| AR5K_PHY_IQ_CORR_Q_Q_COFF |
Mask for q correction info |
| AR5K_PHY_IQ_CORR_Q_Q_COFF |
Mask for q correction info |
| AR5K_PHY_IQ_EARLY_TRIG_THR |
Early trigger threshold (?) (field) |
| AR5K_PHY_IQ_EARLY_TRIG_THR |
Early trigger threshold (?) (field) |
| AR5K_PHY_IQ_PILOT_MASK_EN |
Enable pilot mask (?) |
| AR5K_PHY_IQ_PILOT_MASK_EN |
Enable pilot mask (?) |
| AR5K_PHY_IQ_RUN |
Run i/q calibration |
| AR5K_PHY_IQ_RUN |
Run i/q calibration |
| AR5K_PHY_IQ_SPUR_FILT_EN |
Enable spur filter |
| AR5K_PHY_IQ_SPUR_FILT_EN |
Enable spur filter |
| AR5K_PHY_IQ_SPUR_RSSI_EN |
Enable spur rssi |
| AR5K_PHY_IQ_SPUR_RSSI_EN |
Enable spur rssi |
| AR5K_PHY_IQ_USE_PT_DF |
Use pilot track df (?) |
| AR5K_PHY_IQ_USE_PT_DF |
Use pilot track df (?) |
| AR5K_PHY_IQRES_CAL_CORR |
I/Q Correlation |
| AR5K_PHY_IQRES_CAL_CORR |
I/Q Correlation |
| AR5K_PHY_IQRES_CAL_PWR_I |
I (Inphase) power value |
| AR5K_PHY_IQRES_CAL_PWR_I |
I (Inphase) power value |
| AR5K_PHY_IQRES_CAL_PWR_Q |
Q (Quadrature) power value |
| AR5K_PHY_IQRES_CAL_PWR_Q |
Q (Quadrature) power value |
| AR5K_PHY_MAX_RX_LEN |
|
| AR5K_PHY_MAX_RX_LEN |
|
| AR5K_PHY_MODE |
Register Address |
| AR5K_PHY_MODE |
Register Address |
| AR5K_PHY_MODE_FREQ |
Freq mode bit |
| AR5K_PHY_MODE_FREQ |
Freq mode bit |
| AR5K_PHY_MODE_FREQ_2GHZ |
|
| AR5K_PHY_MODE_FREQ_2GHZ |
|
| AR5K_PHY_MODE_FREQ_5GHZ |
|
| AR5K_PHY_MODE_FREQ_5GHZ |
|
| AR5K_PHY_MODE_HALF_RATE |
Enable Half rate (test) |
| AR5K_PHY_MODE_HALF_RATE |
Enable Half rate (test) |
| AR5K_PHY_MODE_MOD |
PHY Modulation bit |
| AR5K_PHY_MODE_MOD |
PHY Modulation bit |
| AR5K_PHY_MODE_MOD_CCK |
|
| AR5K_PHY_MODE_MOD_CCK |
|
| AR5K_PHY_MODE_MOD_DYN |
Enable Dynamic OFDM/CCK mode [5112+] |
| AR5K_PHY_MODE_MOD_DYN |
Enable Dynamic OFDM/CCK mode [5112+] |
| AR5K_PHY_MODE_MOD_OFDM |
|
| AR5K_PHY_MODE_MOD_OFDM |
|
| AR5K_PHY_MODE_QUARTER_RATE |
Enable Quarter rat (test) |
| AR5K_PHY_MODE_QUARTER_RATE |
Enable Quarter rat (test) |
| AR5K_PHY_MODE_RAD |
[5212+] |
| AR5K_PHY_MODE_RAD |
[5212+] |
| AR5K_PHY_MODE_RAD_RF5111 |
|
| AR5K_PHY_MODE_RAD_RF5111 |
|
| AR5K_PHY_MODE_RAD_RF5112 |
|
| AR5K_PHY_MODE_RAD_RF5112 |
|
| AR5K_PHY_MODE_XR |
Enable XR mode [5112+] |
| AR5K_PHY_MODE_XR |
Enable XR mode [5112+] |
| AR5K_PHY_NF |
Register address |
| AR5K_PHY_NF |
Register address |
| AR5K_PHY_NF_ACTIVE |
Noise floor calibration still active |
| AR5K_PHY_NF_ACTIVE |
Noise floor calibration still active |
| AR5K_PHY_NF_AVAL(_n) |
|
| AR5K_PHY_NF_AVAL(_n) |
|
| AR5K_PHY_NF_M |
Noise floor mask |
| AR5K_PHY_NF_M |
Noise floor mask |
| AR5K_PHY_NF_MINCCA_PWR |
??? |
| AR5K_PHY_NF_MINCCA_PWR |
??? |
| AR5K_PHY_NF_MINCCA_PWR_S |
|
| AR5K_PHY_NF_MINCCA_PWR_S |
|
| AR5K_PHY_NF_RVAL(_n) |
|
| AR5K_PHY_NF_RVAL(_n) |
|
| AR5K_PHY_NF_SVAL(_n) |
|
| AR5K_PHY_NF_SVAL(_n) |
|
| AR5K_PHY_NF_THRESH62 |
Thresh62 -check ANI patent- (field) |
| AR5K_PHY_NF_THRESH62 |
Thresh62 -check ANI patent- (field) |
| AR5K_PHY_NF_THRESH62_S |
|
| AR5K_PHY_NF_THRESH62_S |
|
| AR5K_PHY_NFTHRES |
|
| AR5K_PHY_NFTHRES |
|
| AR5K_PHY_OFDM_SELFCORR |
Register Address |
| AR5K_PHY_OFDM_SELFCORR |
Register Address |
| AR5K_PHY_OFDM_SELFCORR_CYPWR_TH |
Enable cyclic RSSI thr 1 |
| AR5K_PHY_OFDM_SELFCORR_CYPWR_TH |
Mask for Cyclic RSSI threshold 1 |
| AR5K_PHY_OFDM_SELFCORR_CYPWR_TH |
|
| AR5K_PHY_OFDM_SELFCORR_CYPWR_TH |
Cyclic RSSI threshold 3 (field) (?) |
| AR5K_PHY_OFDM_SELFCORR_CYPWR_TH |
Enable cyclic RSSI thr 1 |
| AR5K_PHY_OFDM_SELFCORR_CYPWR_TH |
Mask for Cyclic RSSI threshold 1 |
| AR5K_PHY_OFDM_SELFCORR_CYPWR_TH |
|
| AR5K_PHY_OFDM_SELFCORR_CYPWR_TH |
Cyclic RSSI threshold 3 (field) (?) |
| AR5K_PHY_OFDM_SELFCORR_LSCTHR_H |
Long sc threshold hi rssi (?) |
| AR5K_PHY_OFDM_SELFCORR_LSCTHR_H |
Long sc threshold hi rssi (?) |
| AR5K_PHY_OFDM_SELFCORR_RSSI_1AT |
Enable 1A RSSI threshold (?) |
| AR5K_PHY_OFDM_SELFCORR_RSSI_1AT |
1A RSSI threshold (field) (?) |
| AR5K_PHY_OFDM_SELFCORR_RSSI_1AT |
Enable 1A RSSI threshold (?) |
| AR5K_PHY_OFDM_SELFCORR_RSSI_1AT |
1A RSSI threshold (field) (?) |
| AR5K_PHY_PA_CTL |
Register Address |
| AR5K_PHY_PA_CTL |
Register Address |
| AR5K_PHY_PA_CTL_XPA_A_EN |
Enable XPA A |
| AR5K_PHY_PA_CTL_XPA_A_EN |
Enable XPA A |
| AR5K_PHY_PA_CTL_XPA_A_HI |
XPA A high (?) |
| AR5K_PHY_PA_CTL_XPA_A_HI |
XPA A high (?) |
| AR5K_PHY_PA_CTL_XPA_B_EN |
Enable XPA B |
| AR5K_PHY_PA_CTL_XPA_B_EN |
Enable XPA B |
| AR5K_PHY_PA_CTL_XPA_B_HI |
XPA B high (?) |
| AR5K_PHY_PA_CTL_XPA_B_HI |
XPA B high (?) |
| AR5K_PHY_PAPD_I(_n) |
|
| AR5K_PHY_PAPD_I(_n) |
|
| AR5K_PHY_PAPD_I_BASE |
|
| AR5K_PHY_PAPD_I_BASE |
|
| AR5K_PHY_PAPD_PROBE |
|
| AR5K_PHY_PAPD_PROBE |
|
| AR5K_PHY_PAPD_PROBE_COMP_GAIN |
|
| AR5K_PHY_PAPD_PROBE_COMP_GAIN |
|
| AR5K_PHY_PAPD_PROBE_GAINF |
|
| AR5K_PHY_PAPD_PROBE_GAINF |
|
| AR5K_PHY_PAPD_PROBE_GAINF_S |
|
| AR5K_PHY_PAPD_PROBE_GAINF_S |
|
| AR5K_PHY_PAPD_PROBE_INI_5111 |
[5212+] |
| AR5K_PHY_PAPD_PROBE_INI_5111 |
[5212+] |
| AR5K_PHY_PAPD_PROBE_INI_5112 |
[5212+] |
| AR5K_PHY_PAPD_PROBE_INI_5112 |
[5212+] |
| AR5K_PHY_PAPD_PROBE_PCDAC_BIAS |
|
| AR5K_PHY_PAPD_PROBE_PCDAC_BIAS |
|
| AR5K_PHY_PAPD_PROBE_PREDIST_EN |
|
| AR5K_PHY_PAPD_PROBE_PREDIST_EN |
|
| AR5K_PHY_PAPD_PROBE_SH_HI_PAR |
|
| AR5K_PHY_PAPD_PROBE_SH_HI_PAR |
|
| AR5K_PHY_PAPD_PROBE_TX_NEXT |
|
| AR5K_PHY_PAPD_PROBE_TX_NEXT |
|
| AR5K_PHY_PAPD_PROBE_TXPOWER |
|
| AR5K_PHY_PAPD_PROBE_TXPOWER |
|
| AR5K_PHY_PAPD_PROBE_TXPOWER_S |
|
| AR5K_PHY_PAPD_PROBE_TXPOWER_S |
|
| AR5K_PHY_PAPD_PROBE_TYPE |
[5112+] |
| AR5K_PHY_PAPD_PROBE_TYPE |
[5112+] |
| AR5K_PHY_PAPD_PROBE_TYPE_CCK |
|
| AR5K_PHY_PAPD_PROBE_TYPE_CCK |
|
| AR5K_PHY_PAPD_PROBE_TYPE_OFDM |
|
| AR5K_PHY_PAPD_PROBE_TYPE_OFDM |
|
| AR5K_PHY_PAPD_PROBE_TYPE_S |
|
| AR5K_PHY_PAPD_PROBE_TYPE_S |
|
| AR5K_PHY_PAPD_PROBE_TYPE_XR |
|
| AR5K_PHY_PAPD_PROBE_TYPE_XR |
|
| AR5K_PHY_PCDAC_TXPOWER(_n) |
|
| AR5K_PHY_PCDAC_TXPOWER(_n) |
|
| AR5K_PHY_PCDAC_TXPOWER_BASE |
|
| AR5K_PHY_PCDAC_TXPOWER_BASE |
|
| AR5K_PHY_PDADC_TXPOWER(_n) |
|
| AR5K_PHY_PDADC_TXPOWER(_n) |
|
| AR5K_PHY_PDADC_TXPOWER_BASE |
|
| AR5K_PHY_PDADC_TXPOWER_BASE |
|
| AR5K_PHY_PLL |
|
| AR5K_PHY_PLL |
|
| AR5K_PHY_PLL_20MHZ |
For half rate (?) |
| AR5K_PHY_PLL_20MHZ |
For half rate (?) |
| AR5K_PHY_PLL_40MHZ |
|
| AR5K_PHY_PLL_40MHZ |
|
| AR5K_PHY_PLL_40MHZ_5211 |
|
| AR5K_PHY_PLL_40MHZ_5211 |
|
| AR5K_PHY_PLL_40MHZ_5212 |
|
| AR5K_PHY_PLL_40MHZ_5212 |
|
| AR5K_PHY_PLL_40MHZ_5413 |
|
| AR5K_PHY_PLL_40MHZ_5413 |
|
| AR5K_PHY_PLL_44MHZ |
|
| AR5K_PHY_PLL_44MHZ |
|
| AR5K_PHY_PLL_44MHZ_5211 |
|
| AR5K_PHY_PLL_44MHZ_5211 |
|
| AR5K_PHY_PLL_44MHZ_5212 |
|
| AR5K_PHY_PLL_44MHZ_5212 |
|
| AR5K_PHY_PLL_HALF_RATE |
|
| AR5K_PHY_PLL_HALF_RATE |
|
| AR5K_PHY_PLL_QUARTER_RATE |
|
| AR5K_PHY_PLL_QUARTER_RATE |
|
| AR5K_PHY_PLL_RF5111 |
|
| AR5K_PHY_PLL_RF5111 |
|
| AR5K_PHY_PLL_RF5112 |
|
| AR5K_PHY_PLL_RF5112 |
|
| AR5K_PHY_PTAT |
|
| AR5K_PHY_PTAT |
|
| AR5K_PHY_RADAR |
|
| AR5K_PHY_RADAR |
|
| AR5K_PHY_RADAR_DISABLE |
|
| AR5K_PHY_RADAR_DISABLE |
|
| AR5K_PHY_RADAR_ENABLE |
|
| AR5K_PHY_RADAR_ENABLE |
|
| AR5K_PHY_RADAR_FIRPWR_THR |
Finite Impulse Response |
| AR5K_PHY_RADAR_FIRPWR_THR |
Finite Impulse Response |
| AR5K_PHY_RADAR_FIRPWR_THRS |
|
| AR5K_PHY_RADAR_FIRPWR_THRS |
|
| AR5K_PHY_RADAR_INBANDTHR |
Inband threshold |
| AR5K_PHY_RADAR_INBANDTHR |
Inband threshold |
| AR5K_PHY_RADAR_INBANDTHR_S |
|
| AR5K_PHY_RADAR_INBANDTHR_S |
|
| AR5K_PHY_RADAR_PHEIGHT_THR |
Pulse height threshold |
| AR5K_PHY_RADAR_PHEIGHT_THR |
Pulse height threshold |
| AR5K_PHY_RADAR_PHEIGHT_THR_S |
|
| AR5K_PHY_RADAR_PHEIGHT_THR_S |
|
| AR5K_PHY_RADAR_PRSSI_THR |
Pulse RSSI/SNR threshold |
| AR5K_PHY_RADAR_PRSSI_THR |
Pulse RSSI/SNR threshold |
| AR5K_PHY_RADAR_PRSSI_THR_S |
|
| AR5K_PHY_RADAR_PRSSI_THR_S |
|
| AR5K_PHY_RADAR_RSSI_THR |
Radar RSSI/SNR threshold. |
| AR5K_PHY_RADAR_RSSI_THR |
Radar RSSI/SNR threshold. |
| AR5K_PHY_RADAR_RSSI_THR_S |
|
| AR5K_PHY_RADAR_RSSI_THR_S |
|
| AR5K_PHY_READ(ah, _reg) |
|
| AR5K_PHY_READ(ah, _reg) |
|
| AR5K_PHY_RESTART |
restart |
| AR5K_PHY_RESTART |
restart |
| AR5K_PHY_RESTART_DIV_GC |
Fast diversity gc_limit (?) |
| AR5K_PHY_RESTART_DIV_GC |
Fast diversity gc_limit (?) |
| AR5K_PHY_RESTART_DIV_GC_S |
|
| AR5K_PHY_RESTART_DIV_GC_S |
|
| AR5K_PHY_RF_CTL2 |
Register Address |
| AR5K_PHY_RF_CTL2 |
Register Address |
| AR5K_PHY_RF_CTL2_TXF2TXD_START |
TX frame to TX data start |
| AR5K_PHY_RF_CTL2_TXF2TXD_START |
TX frame to TX data start |
| AR5K_PHY_RF_CTL2_TXF2TXD_START_ |
|
| AR5K_PHY_RF_CTL2_TXF2TXD_START_ |
|
| AR5K_PHY_RF_CTL3 |
Register Address |
| AR5K_PHY_RF_CTL3 |
Register Address |
| AR5K_PHY_RF_CTL3_TXE2XLNA_ON |
TX end to XLNA on |
| AR5K_PHY_RF_CTL3_TXE2XLNA_ON |
TX end to XLNA on |
| AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S |
|
| AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S |
|
| AR5K_PHY_RF_CTL4 |
Register Address |
| AR5K_PHY_RF_CTL4 |
Register Address |
| AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF |
TX end to XPA A off (field) |
| AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF |
TX end to XPA A off (field) |
| AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF |
TX end to XPA B off (field) |
| AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF |
TX end to XPA B off (field) |
| AR5K_PHY_RF_CTL4_TXF2XPA_A_ON |
TX frame to XPA A on (field) |
| AR5K_PHY_RF_CTL4_TXF2XPA_A_ON |
TX frame to XPA A on (field) |
| AR5K_PHY_RF_CTL4_TXF2XPA_B_ON |
TX frame to XPA B on (field) |
| AR5K_PHY_RF_CTL4_TXF2XPA_B_ON |
TX frame to XPA B on (field) |
| AR5K_PHY_RFBUS_GRANT |
|
| AR5K_PHY_RFBUS_GRANT |
|
| AR5K_PHY_RFBUS_GRANT_OK |
|
| AR5K_PHY_RFBUS_GRANT_OK |
|
| AR5K_PHY_RFBUS_REQ |
|
| AR5K_PHY_RFBUS_REQ |
|
| AR5K_PHY_RFBUS_REQ_REQUEST |
|
| AR5K_PHY_RFBUS_REQ_REQUEST |
|
| AR5K_PHY_RFSTG |
|
| AR5K_PHY_RFSTG |
|
| AR5K_PHY_RFSTG_DISABLE |
|
| AR5K_PHY_RFSTG_DISABLE |
|
| AR5K_PHY_RX_DELAY |
Register Address |
| AR5K_PHY_RX_DELAY |
Register Address |
| AR5K_PHY_RX_DELAY_M |
Mask for RX activate to receive delay (/100ns) |
| AR5K_PHY_RX_DELAY_M |
Mask for RX activate to receive delay (/100ns) |
| AR5K_PHY_SCAL |
|
| AR5K_PHY_SCAL |
|
| AR5K_PHY_SCAL_32MHZ |
|
| AR5K_PHY_SCAL_32MHZ |
|
| AR5K_PHY_SCAL_32MHZ_2417 |
|
| AR5K_PHY_SCAL_32MHZ_2417 |
|
| AR5K_PHY_SCAL_32MHZ_HB63 |
|
| AR5K_PHY_SCAL_32MHZ_HB63 |
|
| AR5K_PHY_SCLOCK |
|
| AR5K_PHY_SCLOCK |
|
| AR5K_PHY_SCLOCK_32MHZ |
|
| AR5K_PHY_SCLOCK_32MHZ |
|
| AR5K_PHY_SCR |
|
| AR5K_PHY_SCR |
|
| AR5K_PHY_SDELAY |
|
| AR5K_PHY_SDELAY |
|
| AR5K_PHY_SDELAY_32MHZ |
|
| AR5K_PHY_SDELAY_32MHZ |
|
| AR5K_PHY_SETTLING |
Register Address |
| AR5K_PHY_SETTLING |
Register Address |
| AR5K_PHY_SETTLING_AGC |
AGC settling time |
| AR5K_PHY_SETTLING_AGC |
AGC settling time |
| AR5K_PHY_SETTLING_AGC_S |
|
| AR5K_PHY_SETTLING_AGC_S |
|
| AR5K_PHY_SETTLING_SWITCH |
Switch settlig time |
| AR5K_PHY_SETTLING_SWITCH |
Switch settlig time |
| AR5K_PHY_SETTLING_SWITCH_S |
|
| AR5K_PHY_SETTLING_SWITCH_S |
|
| AR5K_PHY_SHIFT_2GHZ |
Used to access 2GHz radios |
| AR5K_PHY_SHIFT_2GHZ |
Used to access 2GHz radios |
| AR5K_PHY_SHIFT_5GHZ |
Used to access 5GHz radios (default) |
| AR5K_PHY_SHIFT_5GHZ |
Used to access 5GHz radios (default) |
| AR5K_PHY_SIG |
Register Address |
| AR5K_PHY_SIG |
Register Address |
| AR5K_PHY_SIG_FIRPWR |
FIPWR |
| AR5K_PHY_SIG_FIRPWR |
FIPWR |
| AR5K_PHY_SIG_FIRPWR_S |
|
| AR5K_PHY_SIG_FIRPWR_S |
|
| AR5K_PHY_SIG_FIRSTEP |
FIRSTEP |
| AR5K_PHY_SIG_FIRSTEP |
FIRSTEP |
| AR5K_PHY_SIG_FIRSTEP_S |
|
| AR5K_PHY_SIG_FIRSTEP_S |
|
| AR5K_PHY_SIGMA_DELTA |
|
| AR5K_PHY_SIGMA_DELTA |
|
| AR5K_PHY_SIGMA_DELTA_ADC_CLIP |
|
| AR5K_PHY_SIGMA_DELTA_ADC_CLIP |
|
| AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S |
|
| AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S |
|
| AR5K_PHY_SIGMA_DELTA_ADC_SEL |
|
| AR5K_PHY_SIGMA_DELTA_ADC_SEL |
|
| AR5K_PHY_SIGMA_DELTA_ADC_SEL_S |
|
| AR5K_PHY_SIGMA_DELTA_ADC_SEL_S |
|
| AR5K_PHY_SIGMA_DELTA_FILT1 |
|
| AR5K_PHY_SIGMA_DELTA_FILT1 |
|
| AR5K_PHY_SIGMA_DELTA_FILT1_S |
|
| AR5K_PHY_SIGMA_DELTA_FILT1_S |
|
| AR5K_PHY_SIGMA_DELTA_FILT2 |
|
| AR5K_PHY_SIGMA_DELTA_FILT2 |
|
| AR5K_PHY_SIGMA_DELTA_FILT2_S |
|
| AR5K_PHY_SIGMA_DELTA_FILT2_S |
|
| AR5K_PHY_SLMT |
|
| AR5K_PHY_SLMT |
|
| AR5K_PHY_SLMT_32MHZ |
|
| AR5K_PHY_SLMT_32MHZ |
|
| AR5K_PHY_SPENDING |
|
| AR5K_PHY_SPENDING |
|
| AR5K_PHY_SPUR_PWR |
Register Address |
| AR5K_PHY_SPUR_PWR |
Register Address |
| AR5K_PHY_SPUR_PWR_FILT |
Power with SPUR removed (field) |
| AR5K_PHY_SPUR_PWR_FILT |
Power with SPUR removed (field) |
| AR5K_PHY_SPUR_PWR_I |
SPUR Power estimate for I (field) |
| AR5K_PHY_SPUR_PWR_I |
SPUR Power estimate for I (field) |
| AR5K_PHY_SPUR_PWR_Q |
SPUR Power estimate for Q (field) |
| AR5K_PHY_SPUR_PWR_Q |
SPUR Power estimate for Q (field) |
| AR5K_PHY_TIMING_10 |
|
| AR5K_PHY_TIMING_10 |
|
| AR5K_PHY_TIMING_10_PILOT_MASK_2 |
|
| AR5K_PHY_TIMING_10_PILOT_MASK_2 |
|
| AR5K_PHY_TIMING_10_PILOT_MASK_2 |
|
| AR5K_PHY_TIMING_10_PILOT_MASK_2 |
|
| AR5K_PHY_TIMING_11 |
Register address |
| AR5K_PHY_TIMING_11 |
Register address |
| AR5K_PHY_TIMING_11_SPUR_DELTA_P |
Spur delta phase |
| AR5K_PHY_TIMING_11_SPUR_DELTA_P |
|
| AR5K_PHY_TIMING_11_SPUR_DELTA_P |
Spur delta phase |
| AR5K_PHY_TIMING_11_SPUR_DELTA_P |
|
| AR5K_PHY_TIMING_11_SPUR_FREQ_SD |
Freq sigma delta |
| AR5K_PHY_TIMING_11_SPUR_FREQ_SD |
|
| AR5K_PHY_TIMING_11_SPUR_FREQ_SD |
Freq sigma delta |
| AR5K_PHY_TIMING_11_SPUR_FREQ_SD |
|
| AR5K_PHY_TIMING_11_USE_SPUR_IN_ |
Spur filter in AGC detector |
| AR5K_PHY_TIMING_11_USE_SPUR_IN_ |
Spur filter in OFDM self correlator |
| AR5K_PHY_TIMING_11_USE_SPUR_IN_ |
Spur filter in AGC detector |
| AR5K_PHY_TIMING_11_USE_SPUR_IN_ |
Spur filter in OFDM self correlator |
| AR5K_PHY_TIMING_3 |
|
| AR5K_PHY_TIMING_3 |
|
| AR5K_PHY_TIMING_3_DSC_EXP |
|
| AR5K_PHY_TIMING_3_DSC_EXP |
|
| AR5K_PHY_TIMING_3_DSC_EXP_S |
|
| AR5K_PHY_TIMING_3_DSC_EXP_S |
|
| AR5K_PHY_TIMING_3_DSC_MAN |
|
| AR5K_PHY_TIMING_3_DSC_MAN |
|
| AR5K_PHY_TIMING_3_DSC_MAN_S |
|
| AR5K_PHY_TIMING_3_DSC_MAN_S |
|
| AR5K_PHY_TIMING_7 |
|
| AR5K_PHY_TIMING_7 |
|
| AR5K_PHY_TIMING_8 |
|
| AR5K_PHY_TIMING_8 |
|
| AR5K_PHY_TIMING_8_PILOT_MASK_2 |
|
| AR5K_PHY_TIMING_8_PILOT_MASK_2 |
|
| AR5K_PHY_TIMING_8_PILOT_MASK_2_ |
|
| AR5K_PHY_TIMING_8_PILOT_MASK_2_ |
|
| AR5K_PHY_TIMING_9 |
|
| AR5K_PHY_TIMING_9 |
|
| AR5K_PHY_TPC_RG1 |
|
| AR5K_PHY_TPC_RG1 |
|
| AR5K_PHY_TPC_RG1_NUM_PD_GAIN |
|
| AR5K_PHY_TPC_RG1_NUM_PD_GAIN |
|
| AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S |
|
| AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S |
|
| AR5K_PHY_TPC_RG1_PDGAIN_1 |
|
| AR5K_PHY_TPC_RG1_PDGAIN_1 |
|
| AR5K_PHY_TPC_RG1_PDGAIN_1_S |
|
| AR5K_PHY_TPC_RG1_PDGAIN_1_S |
|
| AR5K_PHY_TPC_RG1_PDGAIN_2 |
|
| AR5K_PHY_TPC_RG1_PDGAIN_2 |
|
| AR5K_PHY_TPC_RG1_PDGAIN_2_S |
|
| AR5K_PHY_TPC_RG1_PDGAIN_2_S |
|
| AR5K_PHY_TPC_RG1_PDGAIN_3 |
|
| AR5K_PHY_TPC_RG1_PDGAIN_3 |
|
| AR5K_PHY_TPC_RG1_PDGAIN_3_S |
|
| AR5K_PHY_TPC_RG1_PDGAIN_3_S |
|
| AR5K_PHY_TPC_RG5 |
|
| AR5K_PHY_TPC_RG5 |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_OVERLA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_OVERLA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_OVERLA |
|
| AR5K_PHY_TPC_RG5_PD_GAIN_OVERLA |
|
| AR5K_PHY_TST1 |
|
| AR5K_PHY_TST1 |
|
| AR5K_PHY_TST1_TXHOLD |
Set tx hold (?) |
| AR5K_PHY_TST1_TXHOLD |
Set tx hold (?) |
| AR5K_PHY_TST1_TXSRC_ALT |
Set input to tsdac (?) |
| AR5K_PHY_TST1_TXSRC_ALT |
Set input to tsdac (?) |
| AR5K_PHY_TST1_TXSRC_ALT_S |
|
| AR5K_PHY_TST1_TXSRC_ALT_S |
|
| AR5K_PHY_TST1_TXSRC_SRC |
Used with bit 7 (?) |
| AR5K_PHY_TST1_TXSRC_SRC |
Used with bit 7 (?) |
| AR5K_PHY_TST1_TXSRC_SRC_S |
|
| AR5K_PHY_TST1_TXSRC_SRC_S |
|
| AR5K_PHY_TST2 |
Register Address |
| AR5K_PHY_TST2 |
Register Address |
| AR5K_PHY_TST2_ADC_OBS_SEL |
ADC OBS Select (field ?) |
| AR5K_PHY_TST2_ADC_OBS_SEL |
ADC OBS Select (field ?) |
| AR5K_PHY_TST2_AGC_OBS_SEL_3 |
AGC OBS Select 3 (?) |
| AR5K_PHY_TST2_AGC_OBS_SEL_3 |
AGC OBS Select 3 (?) |
| AR5K_PHY_TST2_ALT_RFDATA |
Alternate RFDATA (5-2GHz switch ?) |
| AR5K_PHY_TST2_ALT_RFDATA |
Alternate RFDATA (5-2GHz switch ?) |
| AR5K_PHY_TST2_BBB_OBS_SEL |
BB OBS Select (field ?) |
| AR5K_PHY_TST2_BBB_OBS_SEL |
BB OBS Select (field ?) |
| AR5K_PHY_TST2_CBUS_MODE |
Cardbus mode (?) |
| AR5K_PHY_TST2_CBUS_MODE |
Cardbus mode (?) |
| AR5K_PHY_TST2_CHANCOR_DUMP_EN |
Enable Chancor dump (?) |
| AR5K_PHY_TST2_CHANCOR_DUMP_EN |
Enable Chancor dump (?) |
| AR5K_PHY_TST2_CLK32 |
CLK_OUT is CLK32 (32Khz external) |
| AR5K_PHY_TST2_CLK32 |
CLK_OUT is CLK32 (32Khz external) |
| AR5K_PHY_TST2_EVEN_CHANCOR_DUMP |
Even Chancor dump (?) |
| AR5K_PHY_TST2_EVEN_CHANCOR_DUMP |
Even Chancor dump (?) |
| AR5K_PHY_TST2_FORCE_AGC_CLR |
Force AGC clear (?) |
| AR5K_PHY_TST2_FORCE_AGC_CLR |
Force AGC clear (?) |
| AR5K_PHY_TST2_MINI_OBS_EN |
Enable mini OBS (?) |
| AR5K_PHY_TST2_MINI_OBS_EN |
Enable mini OBS (?) |
| AR5K_PHY_TST2_RFSILENT_EN |
Enable RFSILENT |
| AR5K_PHY_TST2_RFSILENT_EN |
Enable RFSILENT |
| AR5K_PHY_TST2_RX_CLR_SEL |
RX Clear Select (?) |
| AR5K_PHY_TST2_RX_CLR_SEL |
RX Clear Select (?) |
| AR5K_PHY_TST2_RX2_IS_RX5_INV |
2GHz rx path is the 5GHz path inverted (?) |
| AR5K_PHY_TST2_RX2_IS_RX5_INV |
2GHz rx path is the 5GHz path inverted (?) |
| AR5K_PHY_TST2_SLOW_CLK160 |
Slow CLK160 (?) |
| AR5K_PHY_TST2_SLOW_CLK160 |
Slow CLK160 (?) |
| AR5K_PHY_TST2_TRIG |
Trigger (?) |
| AR5K_PHY_TST2_TRIG |
Trigger (?) |
| AR5K_PHY_TST2_TRIG_SEL |
Trigger select (?) |
| AR5K_PHY_TST2_TRIG_SEL |
Trigger select (?) |
| AR5K_PHY_TURBO |
Register Address |
| AR5K_PHY_TURBO |
Register Address |
| AR5K_PHY_TURBO_MIMO |
Set turbo for mimo mimo |
| AR5K_PHY_TURBO_MIMO |
Set turbo for mimo mimo |
| AR5K_PHY_TURBO_MODE |
Enable turbo mode |
| AR5K_PHY_TURBO_MODE |
Enable turbo mode |
| AR5K_PHY_TURBO_SHORT |
Set short symbols to turbo mode |
| AR5K_PHY_TURBO_SHORT |
Set short symbols to turbo mode |
| AR5K_PHY_TX_PWR_ADJ |
|
| AR5K_PHY_TX_PWR_ADJ |
|
| AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE |
|
| AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE |
|
| AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE |
|
| AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE |
|
| AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I |
|
| AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I |
|
| AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I |
|
| AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I |
|
| AR5K_PHY_TXPOWER_RATE_MAX |
|
| AR5K_PHY_TXPOWER_RATE_MAX |
|
| AR5K_PHY_TXPOWER_RATE_MAX_TPC_E |
|
| AR5K_PHY_TXPOWER_RATE_MAX_TPC_E |
|
| AR5K_PHY_TXPOWER_RATE1 |
|
| AR5K_PHY_TXPOWER_RATE1 |
|
| AR5K_PHY_TXPOWER_RATE2 |
|
| AR5K_PHY_TXPOWER_RATE2 |
|
| AR5K_PHY_TXPOWER_RATE3 |
|
| AR5K_PHY_TXPOWER_RATE3 |
|
| AR5K_PHY_TXPOWER_RATE4 |
|
| AR5K_PHY_TXPOWER_RATE4 |
|
| AR5K_PHY_WARM_RESET |
|
| AR5K_PHY_WARM_RESET |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_ |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_ |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ |
|
| AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M1 |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M1 |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M2 |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M2 |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M2_C |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M2_C |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M2_C |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M2_C |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_SELF |
|
| AR5K_PHY_WEAK_OFDM_LOW_THR_SELF |
|
| AR5K_PHY_WRITE(ah, _reg, _val) |
|
| AR5K_PHY_WRITE(ah, _reg, _val) |
|
| AR5K_PHYERR_CNT1 |
|
| AR5K_PHYERR_CNT1 |
|
| AR5K_PHYERR_CNT1_MASK |
|
| AR5K_PHYERR_CNT1_MASK |
|
| AR5K_PHYERR_CNT2 |
|
| AR5K_PHYERR_CNT2 |
|
| AR5K_PHYERR_CNT2_MASK |
|
| AR5K_PHYERR_CNT2_MASK |
|
| AR5K_PIMR |
Register Address [5211+] |
| AR5K_PIMR |
Register Address [5211+] |
| AR5K_PISR |
Register Address [5211+] |
| AR5K_PISR |
Register Address [5211+] |
| AR5K_PROFCNT_CYCLE |
Cycle count (?) |
| AR5K_PROFCNT_CYCLE |
Cycle count (?) |
| AR5K_PROFCNT_RX |
Rx count |
| AR5K_PROFCNT_RX |
Rx count |
| AR5K_PROFCNT_RXCLR |
Clear Rx count |
| AR5K_PROFCNT_RXCLR |
Clear Rx count |
| AR5K_PROFCNT_TX |
Tx count |
| AR5K_PROFCNT_TX |
Tx count |
| AR5K_Q_DISABLE_BITS(_reg, _queue) |
|
| AR5K_Q_DISABLE_BITS(_reg, _queue) |
|
| AR5K_Q_ENABLE_BITS(_reg, _queue) |
|
| AR5K_Q_ENABLE_BITS(_reg, _queue) |
|
| AR5K_QCU_CBB_ADDR |
|
| AR5K_QCU_CBB_ADDR |
|
| AR5K_QCU_CBB_ADDR_S |
|
| AR5K_QCU_CBB_ADDR_S |
|
| AR5K_QCU_CBB_SELECT |
|
| AR5K_QCU_CBB_SELECT |
|
| AR5K_QCU_CBCFG |
|
| AR5K_QCU_CBCFG |
|
| AR5K_QCU_CBRCFG_BASE |
Register Address - Queue0 CBRCFG |
| AR5K_QCU_CBRCFG_BASE |
Register Address - Queue0 CBRCFG |
| AR5K_QCU_CBRCFG_INTVAL |
CBR Interval mask |
| AR5K_QCU_CBRCFG_INTVAL |
CBR Interval mask |
| AR5K_QCU_CBRCFG_INTVAL_S |
|
| AR5K_QCU_CBRCFG_INTVAL_S |
|
| AR5K_QCU_CBRCFG_ORN_THRES |
CBR overrun threshold mask |
| AR5K_QCU_CBRCFG_ORN_THRES |
CBR overrun threshold mask |
| AR5K_QCU_CBRCFG_ORN_THRES_S |
|
| AR5K_QCU_CBRCFG_ORN_THRES_S |
|
| AR5K_QCU_GLOBAL_READ(_r, _q) |
|
| AR5K_QCU_GLOBAL_READ(_r, _q) |
|
| AR5K_QCU_GLOBAL_WRITE(_r, _q) |
|
| AR5K_QCU_GLOBAL_WRITE(_r, _q) |
|
| AR5K_QCU_MISC_BASE |
Register Address -Queue0 MISC |
| AR5K_QCU_MISC_BASE |
Register Address -Queue0 MISC |
| AR5K_QCU_MISC_BCN_ENABLE |
Enable Beacon use |
| AR5K_QCU_MISC_BCN_ENABLE |
Enable Beacon use |
| AR5K_QCU_MISC_CBR_RESET_CNT |
CBR threshold (counter) reset |
| AR5K_QCU_MISC_CBR_RESET_CNT |
CBR threshold (counter) reset |
| AR5K_QCU_MISC_CBR_THRES_ENABLE |
CBR expired threshold enabled |
| AR5K_QCU_MISC_CBR_THRES_ENABLE |
CBR expired threshold enabled |
| AR5K_QCU_MISC_CBREXP_BCN_DIS |
Disable CBR expired counter (beacon queue) |
| AR5K_QCU_MISC_CBREXP_BCN_DIS |
Disable CBR expired counter (beacon queue) |
| AR5K_QCU_MISC_CBREXP_DIS |
Disable CBR expired counter (normal queue) |
| AR5K_QCU_MISC_CBREXP_DIS |
Disable CBR expired counter (normal queue) |
| AR5K_QCU_MISC_DCU_CMP_EN |
Enable frame compression |
| AR5K_QCU_MISC_DCU_CMP_EN |
Enable frame compression |
| AR5K_QCU_MISC_DCU_EARLY |
DCU early termination |
| AR5K_QCU_MISC_DCU_EARLY |
DCU early termination |
| AR5K_QCU_MISC_FRSHED_ASAP |
ASAP |
| AR5K_QCU_MISC_FRSHED_ASAP |
ASAP |
| AR5K_QCU_MISC_FRSHED_BCN_SENT_G |
Beacon sent gated |
| AR5K_QCU_MISC_FRSHED_BCN_SENT_G |
Beacon sent gated |
| AR5K_QCU_MISC_FRSHED_CBR |
Constant Bit Rate |
| AR5K_QCU_MISC_FRSHED_CBR |
Constant Bit Rate |
| AR5K_QCU_MISC_FRSHED_DBA_GT |
DMA Beacon alert gated |
| AR5K_QCU_MISC_FRSHED_DBA_GT |
DMA Beacon alert gated |
| AR5K_QCU_MISC_FRSHED_M |
Frame sheduling mask |
| AR5K_QCU_MISC_FRSHED_M |
Frame sheduling mask |
| AR5K_QCU_MISC_FRSHED_TIM_GT |
TIMT gated |
| AR5K_QCU_MISC_FRSHED_TIM_GT |
TIMT gated |
| AR5K_QCU_MISC_ONESHOT_ENABLE |
Oneshot enable |
| AR5K_QCU_MISC_ONESHOT_ENABLE |
Oneshot enable |
| AR5K_QCU_MISC_RDY_VEOL_POLICY |
TXE reset when RDYTIME expired or VEOL |
| AR5K_QCU_MISC_RDY_VEOL_POLICY |
TXE reset when RDYTIME expired or VEOL |
| AR5K_QCU_ONESHOTARM_CLEAR |
Register Address -QCU "one shot arm clear (?)" |
| AR5K_QCU_ONESHOTARM_CLEAR |
Register Address -QCU "one shot arm clear (?)" |
| AR5K_QCU_ONESHOTARM_CLEAR_M |
|
| AR5K_QCU_ONESHOTARM_CLEAR_M |
|
| AR5K_QCU_ONESHOTARM_SET |
Register Address -QCU "one shot arm set (?)" |
| AR5K_QCU_ONESHOTARM_SET |
Register Address -QCU "one shot arm set (?)" |
| AR5K_QCU_ONESHOTARM_SET_M |
|
| AR5K_QCU_ONESHOTARM_SET_M |
|
| AR5K_QCU_RDYTIMECFG_BASE |
Register Address - Queue0 RDYTIMECFG |
| AR5K_QCU_RDYTIMECFG_BASE |
Register Address - Queue0 RDYTIMECFG |
| AR5K_QCU_RDYTIMECFG_ENABLE |
Ready time enable mask |
| AR5K_QCU_RDYTIMECFG_ENABLE |
Ready time enable mask |
| AR5K_QCU_RDYTIMECFG_INTVAL |
Ready time interval mask |
| AR5K_QCU_RDYTIMECFG_INTVAL |
Ready time interval mask |
| AR5K_QCU_RDYTIMECFG_INTVAL_S |
|
| AR5K_QCU_RDYTIMECFG_INTVAL_S |
|
| AR5K_QCU_RDYTIMESHDN |
|
| AR5K_QCU_RDYTIMESHDN |
|
| AR5K_QCU_RDYTIMESHDN_M |
|
| AR5K_QCU_RDYTIMESHDN_M |
|
| AR5K_QCU_SLEEP_MASK |
|
| AR5K_QCU_SLEEP_MASK |
|
| AR5K_QCU_STS_BASE |
Register Address - Queue0 STS |
| AR5K_QCU_STS_BASE |
Register Address - Queue0 STS |
| AR5K_QCU_STS_CBREXPCNT |
CBR expired counter |
| AR5K_QCU_STS_CBREXPCNT |
CBR expired counter |
| AR5K_QCU_STS_FRMPENDCNT |
Frames pending counter |
| AR5K_QCU_STS_FRMPENDCNT |
Frames pending counter |
| AR5K_QCU_TXD |
|
| AR5K_QCU_TXD |
|
| AR5K_QCU_TXDP_BASE |
Register Address - Queue0 TXDP |
| AR5K_QCU_TXDP_BASE |
Register Address - Queue0 TXDP |
| AR5K_QCU_TXE |
|
| AR5K_QCU_TXE |
|
| AR5K_QCUDCU_CLKGT |
Register Address (?) |
| AR5K_QCUDCU_CLKGT |
Register Address (?) |
| AR5K_QCUDCU_CLKGT_DCU |
Mask for DCU clock |
| AR5K_QCUDCU_CLKGT_DCU |
Mask for DCU clock |
| AR5K_QCUDCU_CLKGT_QCU |
Mask for QCU clock |
| AR5K_QCUDCU_CLKGT_QCU |
Mask for QCU clock |
| AR5K_QOS_NOACK |
Register Address |
| AR5K_QOS_NOACK |
Register Address |
| AR5K_QOS_NOACK_2BIT_VALUES |
??? |
| AR5K_QOS_NOACK_2BIT_VALUES |
??? |
| AR5K_QOS_NOACK_2BIT_VALUES_S |
|
| AR5K_QOS_NOACK_2BIT_VALUES_S |
|
| AR5K_QOS_NOACK_BIT_OFFSET |
??? |
| AR5K_QOS_NOACK_BIT_OFFSET |
??? |
| AR5K_QOS_NOACK_BIT_OFFSET_S |
|
| AR5K_QOS_NOACK_BIT_OFFSET_S |
|
| AR5K_QOS_NOACK_BYTE_OFFSET |
??? |
| AR5K_QOS_NOACK_BYTE_OFFSET |
??? |
| AR5K_QOS_NOACK_BYTE_OFFSET_S |
|
| AR5K_QOS_NOACK_BYTE_OFFSET_S |
|
| AR5K_QUEUE_CBRCFG(_q) |
|
| AR5K_QUEUE_CBRCFG(_q) |
|
| AR5K_QUEUE_DCU_SEQNUM(_q) |
|
| AR5K_QUEUE_DCU_SEQNUM(_q) |
|
| AR5K_QUEUE_DFS_CHANNEL_TIME(_q) |
|
| AR5K_QUEUE_DFS_CHANNEL_TIME(_q) |
|
| AR5K_QUEUE_DFS_LOCAL_IFS(_q) |
|
| AR5K_QUEUE_DFS_LOCAL_IFS(_q) |
|
| AR5K_QUEUE_DFS_MISC(_q) |
|
| AR5K_QUEUE_DFS_MISC(_q) |
|
| AR5K_QUEUE_DFS_RETRY_LIMIT(_q) |
|
| AR5K_QUEUE_DFS_RETRY_LIMIT(_q) |
|
| AR5K_QUEUE_DISABLED(_q) |
|
| AR5K_QUEUE_DISABLED(_q) |
|
| AR5K_QUEUE_ENABLED(_q) |
|
| AR5K_QUEUE_ENABLED(_q) |
|
| AR5K_QUEUE_MISC(_q) |
|
| AR5K_QUEUE_MISC(_q) |
|
| AR5K_QUEUE_QCUMASK(_q) |
|
| AR5K_QUEUE_QCUMASK(_q) |
|
| AR5K_QUEUE_RDYTIMECFG(_q) |
|
| AR5K_QUEUE_RDYTIMECFG(_q) |
|
| AR5K_QUEUE_REG(_r, _q) |
|
| AR5K_QUEUE_REG(_r, _q) |
|
| AR5K_QUEUE_STATUS(_q) |
|
| AR5K_QUEUE_STATUS(_q) |
|
| AR5K_QUEUE_TXDP(_q) |
|
| AR5K_QUEUE_TXDP(_q) |
|
| AR5K_QUIET_CTL1 |
Register Address |
| AR5K_QUIET_CTL1 |
Register Address |
| AR5K_QUIET_CTL1_ACK_CTS_EN |
Send ACK/CTS during quiet period |
| AR5K_QUIET_CTL1_ACK_CTS_EN |
Send ACK/CTS during quiet period |
| AR5K_QUIET_CTL1_NEXT_QT_TSF |
Next quiet period TSF (TU) |
| AR5K_QUIET_CTL1_NEXT_QT_TSF |
Next quiet period TSF (TU) |
| AR5K_QUIET_CTL1_NEXT_QT_TSF_S |
|
| AR5K_QUIET_CTL1_NEXT_QT_TSF_S |
|
| AR5K_QUIET_CTL1_QT_EN |
Enable quiet period |
| AR5K_QUIET_CTL1_QT_EN |
Enable quiet period |
| AR5K_QUIET_CTL2 |
Register Address |
| AR5K_QUIET_CTL2 |
Register Address |
| AR5K_QUIET_CTL2_QT_DUR |
Mask for quiet period duration |
| AR5K_QUIET_CTL2_QT_DUR |
Mask for quiet period duration |
| AR5K_QUIET_CTL2_QT_DUR_S |
|
| AR5K_QUIET_CTL2_QT_DUR_S |
|
| AR5K_QUIET_CTL2_QT_PER |
Mask for quiet period periodicity |
| AR5K_QUIET_CTL2_QT_PER |
Mask for quiet period periodicity |
| AR5K_QUIET_CTL2_QT_PER_S |
|
| AR5K_QUIET_CTL2_QT_PER_S |
|
| AR5K_RAC_PISR |
Read and clear PISR |
| AR5K_RAC_PISR |
Read and clear PISR |
| AR5K_RAC_SISR0 |
Read and clear SISR0 |
| AR5K_RAC_SISR0 |
Read and clear SISR0 |
| AR5K_RAC_SISR1 |
Read and clear SISR1 |
| AR5K_RAC_SISR1 |
Read and clear SISR1 |
| AR5K_RAC_SISR2 |
Read and clear SISR2 |
| AR5K_RAC_SISR2 |
Read and clear SISR2 |
| AR5K_RAC_SISR3 |
Read and clear SISR3 |
| AR5K_RAC_SISR3 |
Read and clear SISR3 |
| AR5K_RAC_SISR4 |
Read and clear SISR4 |
| AR5K_RAC_SISR4 |
Read and clear SISR4 |
| AR5K_RATE_ACKSIFS(_n) |
|
| AR5K_RATE_ACKSIFS(_n) |
|
| AR5K_RATE_ACKSIFS_BASE |
Register Address |
| AR5K_RATE_ACKSIFS_BASE |
Register Address |
| AR5K_RATE_ACKSIFS_NORMAL |
Normal SIFS (field) |
| AR5K_RATE_ACKSIFS_NORMAL |
Normal SIFS (field) |
| AR5K_RATE_ACKSIFS_TURBO |
Turbo SIFS (field) |
| AR5K_RATE_ACKSIFS_TURBO |
Turbo SIFS (field) |
| AR5K_RATE_DUR(_n) |
|
| AR5K_RATE_DUR(_n) |
|
| AR5K_RATE_DUR_BASE |
|
| AR5K_RATE_DUR_BASE |
|
| AR5K_RATE2DB(_n) |
|
| AR5K_RATE2DB(_n) |
|
| AR5K_RATE2DB_BASE |
|
| AR5K_RATE2DB_BASE |
|
| AR5K_REG_DISABLE_BITS(ah, _reg, _flags) |
|
| AR5K_REG_DISABLE_BITS(ah, _reg, _flags) |
|
| AR5K_REG_ENABLE_BITS(ah, _reg, _flags) |
|
| AR5K_REG_ENABLE_BITS(ah, _reg, _flags) |
|
| AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) |
|
| AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) |
|
| AR5K_REG_MS(_val, _flags) |
|
| AR5K_REG_MS(_val, _flags) |
|
| AR5K_REG_READ_Q(ah, _reg, _queue) |
|
| AR5K_REG_READ_Q(ah, _reg, _queue) |
|
| AR5K_REG_SM(_val, _flags) |
|
| AR5K_REG_SM(_val, _flags) |
|
| AR5K_REG_WAIT(_i) |
|
| AR5K_REG_WAIT(_i) |
|
| AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) |
|
| AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) |
|
| AR5K_REG_WRITE_Q(ah, _reg, _queue) |
|
| AR5K_REG_WRITE_Q(ah, _reg, _queue) |
|
| AR5K_RESET_CTL |
Register Address |
| AR5K_RESET_CTL |
Register Address |
| AR5K_RESET_CTL_BASEBAND |
Baseband reset [5211+] |
| AR5K_RESET_CTL_BASEBAND |
Baseband reset [5211+] |
| AR5K_RESET_CTL_DMA |
DMA (Rx/Tx) reset [5210] |
| AR5K_RESET_CTL_DMA |
DMA (Rx/Tx) reset [5210] |
| AR5K_RESET_CTL_MAC |
MAC reset (PCU+Baseband ?) [5210] |
| AR5K_RESET_CTL_MAC |
MAC reset (PCU+Baseband ?) [5210] |
| AR5K_RESET_CTL_PCI |
PCI Core reset (interrupts etc) |
| AR5K_RESET_CTL_PCI |
PCI Core reset (interrupts etc) |
| AR5K_RESET_CTL_PCU |
Protocol Control Unit reset |
| AR5K_RESET_CTL_PCU |
Protocol Control Unit reset |
| AR5K_RESET_CTL_PHY |
PHY reset [5210] |
| AR5K_RESET_CTL_PHY |
PHY reset [5210] |
| AR5K_RETRY_CNT |
Register Address [5210] |
| AR5K_RETRY_CNT |
Register Address [5210] |
| AR5K_RETRY_CNT_SLG |
Station long retry count (?) |
| AR5K_RETRY_CNT_SLG |
Station long retry count (?) |
| AR5K_RETRY_CNT_SSH |
Station short retry count (?) |
| AR5K_RETRY_CNT_SSH |
Station short retry count (?) |
| AR5K_RF_BUFFER |
|
| AR5K_RF_BUFFER |
|
| AR5K_RF_BUFFER_CONTROL_0 |
Channel on 5110 |
| AR5K_RF_BUFFER_CONTROL_0 |
Channel on 5110 |
| AR5K_RF_BUFFER_CONTROL_1 |
Bank 7 on 5112 |
| AR5K_RF_BUFFER_CONTROL_1 |
Bank 7 on 5112 |
| AR5K_RF_BUFFER_CONTROL_2 |
Bank 7 on 5111 |
| AR5K_RF_BUFFER_CONTROL_2 |
Bank 7 on 5111 |
| AR5K_RF_BUFFER_CONTROL_3 |
Bank 2 on 5112 |
| AR5K_RF_BUFFER_CONTROL_3 |
Bank 2 on 5112 |
| AR5K_RF_BUFFER_CONTROL_4 |
RF Stage register on 5110 |
| AR5K_RF_BUFFER_CONTROL_4 |
RF Stage register on 5110 |
| AR5K_RF_BUFFER_CONTROL_5 |
Bank 3 on 5111 |
| AR5K_RF_BUFFER_CONTROL_5 |
Bank 3 on 5111 |
| AR5K_RF_BUFFER_CONTROL_6 |
Bank 3 on 5112 |
| AR5K_RF_BUFFER_CONTROL_6 |
Bank 3 on 5112 |
| AR5K_RF_GAIN(_n) |
|
| AR5K_RF_GAIN(_n) |
|
| AR5K_RF_GAIN_BASE |
RF Amplrifier Gain table base address |
| AR5K_RF_GAIN_BASE |
RF Amplrifier Gain table base address |
| AR5K_RF2316_DB_2GHZ |
|
| AR5K_RF2316_DB_2GHZ |
|
| AR5K_RF2316_OB_2GHZ |
|
| AR5K_RF2316_OB_2GHZ |
|
| AR5K_RF2413_DB_2GHZ |
|
| AR5K_RF2413_DB_2GHZ |
|
| AR5K_RF2413_OB_2GHZ |
|
| AR5K_RF2413_OB_2GHZ |
|
| AR5K_RF2425_DB_2GHZ |
|
| AR5K_RF2425_DB_2GHZ |
|
| AR5K_RF2425_OB_2GHZ |
|
| AR5K_RF2425_OB_2GHZ |
|
| AR5K_RF5111_DB_2GHZ |
|
| AR5K_RF5111_DB_2GHZ |
|
| AR5K_RF5111_DB_5GHZ |
|
| AR5K_RF5111_DB_5GHZ |
|
| AR5K_RF5111_GAIN_I |
|
| AR5K_RF5111_GAIN_I |
|
| AR5K_RF5111_MAX_TIME |
|
| AR5K_RF5111_MAX_TIME |
|
| AR5K_RF5111_OB_2GHZ |
|
| AR5K_RF5111_OB_2GHZ |
|
| AR5K_RF5111_OB_5GHZ |
|
| AR5K_RF5111_OB_5GHZ |
|
| AR5K_RF5111_PLO_SEL |
|
| AR5K_RF5111_PLO_SEL |
|
| AR5K_RF5111_PWD(_n) |
|
| AR5K_RF5111_PWD(_n) |
|
| AR5K_RF5111_PWD_XPD |
|
| AR5K_RF5111_PWD_XPD |
|
| AR5K_RF5111_RFGAIN_SEL |
|
| AR5K_RF5111_RFGAIN_SEL |
|
| AR5K_RF5111_RFGAIN_STEP |
|
| AR5K_RF5111_RFGAIN_STEP |
|
| AR5K_RF5111_WAIT_I |
|
| AR5K_RF5111_WAIT_I |
|
| AR5K_RF5111_WAIT_S |
|
| AR5K_RF5111_WAIT_S |
|
| AR5K_RF5111_XPD_GAIN |
|
| AR5K_RF5111_XPD_GAIN |
|
| AR5K_RF5112_DB_2GHZ |
|
| AR5K_RF5112_DB_2GHZ |
|
| AR5K_RF5112_DB_5GHZ |
|
| AR5K_RF5112_DB_5GHZ |
|
| AR5K_RF5112_FIXED_BIAS_A |
|
| AR5K_RF5112_FIXED_BIAS_A |
|
| AR5K_RF5112_FIXED_BIAS_B |
|
| AR5K_RF5112_FIXED_BIAS_B |
|
| AR5K_RF5112_OB_2GHZ |
|
| AR5K_RF5112_OB_2GHZ |
|
| AR5K_RF5112_OB_5GHZ |
|
| AR5K_RF5112_OB_5GHZ |
|
| AR5K_RF5112_PWD(_n) |
|
| AR5K_RF5112_PWD(_n) |
|
| AR5K_RF5112_XPD_GAIN |
|
| AR5K_RF5112_XPD_GAIN |
|
| AR5K_RF5112_XPD_SEL |
|
| AR5K_RF5112_XPD_SEL |
|
| AR5K_RF5112A_DB_2GHZ |
|
| AR5K_RF5112A_DB_2GHZ |
|
| AR5K_RF5112A_DB_5GHZ |
|
| AR5K_RF5112A_DB_5GHZ |
|
| AR5K_RF5112A_FIXED_BIAS_A |
|
| AR5K_RF5112A_FIXED_BIAS_A |
|
| AR5K_RF5112A_FIXED_BIAS_B |
|
| AR5K_RF5112A_FIXED_BIAS_B |
|
| AR5K_RF5112A_HIGH_VC_CP |
|
| AR5K_RF5112A_HIGH_VC_CP |
|
| AR5K_RF5112A_LOW_VC_CP |
|
| AR5K_RF5112A_LOW_VC_CP |
|
| AR5K_RF5112A_MID_VC_CP |
|
| AR5K_RF5112A_MID_VC_CP |
|
| AR5K_RF5112A_OB_2GHZ |
|
| AR5K_RF5112A_OB_2GHZ |
|
| AR5K_RF5112A_OB_5GHZ |
|
| AR5K_RF5112A_OB_5GHZ |
|
| AR5K_RF5112A_PAD2GND |
|
| AR5K_RF5112A_PAD2GND |
|
| AR5K_RF5112A_PDGAINHI |
|
| AR5K_RF5112A_PDGAINHI |
|
| AR5K_RF5112A_PDGAINLO |
|
| AR5K_RF5112A_PDGAINLO |
|
| AR5K_RF5112A_PUSH_UP |
|
| AR5K_RF5112A_PUSH_UP |
|
| AR5K_RF5112A_PWD(_n) |
|
| AR5K_RF5112A_PWD(_n) |
|
| AR5K_RF5112A_XB2_LVL |
|
| AR5K_RF5112A_XB2_LVL |
|
| AR5K_RF5112A_XB5_LVL |
|
| AR5K_RF5112A_XB5_LVL |
|
| AR5K_RF5112A_XPD_SEL |
|
| AR5K_RF5112A_XPD_SEL |
|
| AR5K_RF5112X_GAIN_I |
|
| AR5K_RF5112X_GAIN_I |
|
| AR5K_RF5112X_MIXGAIN_OVR |
|
| AR5K_RF5112X_MIXGAIN_OVR |
|
| AR5K_RF5112X_MIXGAIN_STEP |
|
| AR5K_RF5112X_MIXGAIN_STEP |
|
| AR5K_RF5112X_MIXVGA_OVR |
|
| AR5K_RF5112X_MIXVGA_OVR |
|
| AR5K_RF5112X_PD_DELAY_A |
|
| AR5K_RF5112X_PD_DELAY_A |
|
| AR5K_RF5112X_PD_DELAY_B |
|
| AR5K_RF5112X_PD_DELAY_B |
|
| AR5K_RF5112X_PD_DELAY_XR |
|
| AR5K_RF5112X_PD_DELAY_XR |
|
| AR5K_RF5112X_PD_PERIOD_A |
|
| AR5K_RF5112X_PD_PERIOD_A |
|
| AR5K_RF5112X_PD_PERIOD_B |
|
| AR5K_RF5112X_PD_PERIOD_B |
|
| AR5K_RF5112X_PD_PERIOD_XR |
|
| AR5K_RF5112X_PD_PERIOD_XR |
|
| AR5K_RF5413_DB_2GHZ |
|
| AR5K_RF5413_DB_2GHZ |
|
| AR5K_RF5413_DB_5GHZ |
|
| AR5K_RF5413_DB_5GHZ |
|
| AR5K_RF5413_DERBY_CHAN_SEL_MODE |
|
| AR5K_RF5413_DERBY_CHAN_SEL_MODE |
|
| AR5K_RF5413_OB_2GHZ |
|
| AR5K_RF5413_OB_2GHZ |
|
| AR5K_RF5413_OB_5GHZ |
|
| AR5K_RF5413_OB_5GHZ |
|
| AR5K_RF5413_PWD_ICLOBUF2G |
|
| AR5K_RF5413_PWD_ICLOBUF2G |
|
| AR5K_RFCNT |
|
| AR5K_RFCNT |
|
| AR5K_RFCNT_M |
[5211+] (?) |
| AR5K_RFCNT_M |
[5211+] (?) |
| AR5K_RFCNT_RFCL |
[5210] |
| AR5K_RFCNT_RFCL |
[5210] |
| AR5K_RPGTO |
|
| AR5K_RPGTO |
|
| AR5K_RPGTO_M |
|
| AR5K_RPGTO_M |
|
| AR5K_RSSI_EP_MULTIPLIER |
|
| AR5K_RSSI_EP_MULTIPLIER |
|
| AR5K_RSSI_THR |
Register Address |
| AR5K_RSSI_THR |
Register Address |
| AR5K_RSSI_THR_BMISS |
|
| AR5K_RSSI_THR_BMISS |
|
| AR5K_RSSI_THR_BMISS_5210 |
Mask for Beacon Missed threshold [5210] |
| AR5K_RSSI_THR_BMISS_5210 |
Mask for Beacon Missed threshold [5210] |
| AR5K_RSSI_THR_BMISS_5210_S |
|
| AR5K_RSSI_THR_BMISS_5210_S |
|
| AR5K_RSSI_THR_BMISS_5211 |
Mask for Beacon Missed threshold [5211+] |
| AR5K_RSSI_THR_BMISS_5211 |
Mask for Beacon Missed threshold [5211+] |
| AR5K_RSSI_THR_BMISS_5211_S |
|
| AR5K_RSSI_THR_BMISS_5211_S |
|
| AR5K_RSSI_THR_BMISS_S |
|
| AR5K_RSSI_THR_BMISS_S |
|
| AR5K_RSSI_THR_M |
Mask for RSSI threshold [5211+] |
| AR5K_RSSI_THR_M |
Mask for RSSI threshold [5211+] |
| AR5K_RTS_FAIL |
|
| AR5K_RTS_FAIL |
|
| AR5K_RTS_FAIL_5210 |
|
| AR5K_RTS_FAIL_5210 |
|
| AR5K_RTS_FAIL_5211 |
|
| AR5K_RTS_FAIL_5211 |
|
| AR5K_RTS_OK |
|
| AR5K_RTS_OK |
|
| AR5K_RTS_OK_5210 |
|
| AR5K_RTS_OK_5210 |
|
| AR5K_RTS_OK_5211 |
|
| AR5K_RTS_OK_5211 |
|
| AR5K_RTSD0 |
Register Address |
| AR5K_RTSD0 |
Register Address |
| AR5K_RTSD0_12 |
12Mb |
| AR5K_RTSD0_12 |
12Mb |
| AR5K_RTSD0_12_S |
|
| AR5K_RTSD0_12_S |
|
| AR5K_RTSD0_18 |
16Mb |
| AR5K_RTSD0_18 |
16Mb |
| AR5K_RTSD0_18_S |
|
| AR5K_RTSD0_18_S |
|
| AR5K_RTSD0_6 |
6Mb RTS duration mask (?) |
| AR5K_RTSD0_6 |
6Mb RTS duration mask (?) |
| AR5K_RTSD0_6_S |
6Mb RTS duration shift (?) |
| AR5K_RTSD0_6_S |
6Mb RTS duration shift (?) |
| AR5K_RTSD0_9 |
9Mb |
| AR5K_RTSD0_9 |
9Mb |
| AR5K_RTSD0_9_S |
|
| AR5K_RTSD0_9_S |
|
| AR5K_RTSD1 |
Register Address |
| AR5K_RTSD1 |
Register Address |
| AR5K_RTSD1_24 |
24Mb |
| AR5K_RTSD1_24 |
24Mb |
| AR5K_RTSD1_24_S |
|
| AR5K_RTSD1_24_S |
|
| AR5K_RTSD1_36 |
36Mb |
| AR5K_RTSD1_36 |
36Mb |
| AR5K_RTSD1_36_S |
|
| AR5K_RTSD1_36_S |
|
| AR5K_RTSD1_48 |
48Mb |
| AR5K_RTSD1_48 |
48Mb |
| AR5K_RTSD1_48_S |
|
| AR5K_RTSD1_48_S |
|
| AR5K_RTSD1_54 |
54Mb |
| AR5K_RTSD1_54 |
54Mb |
| AR5K_RTSD1_54_S |
|
| AR5K_RTSD1_54_S |
|
| AR5K_RX_DESC_ERROR0 |
|
| AR5K_RX_DESC_ERROR0 |
|
| AR5K_RX_DESC_ERROR1_PHY_ERROR_C |
|
| AR5K_RX_DESC_ERROR1_PHY_ERROR_C |
|
| AR5K_RX_DESC_ERROR1_PHY_ERROR_C |
|
| AR5K_RX_DESC_ERROR1_PHY_ERROR_C |
|
| AR5K_RX_FILTER |
|
| AR5K_RX_FILTER |
|
| AR5K_RX_FILTER_5210 |
Register Address [5210] |
| AR5K_RX_FILTER_5210 |
Register Address [5210] |
| AR5K_RX_FILTER_5211 |
Register Address [5211+] |
| AR5K_RX_FILTER_5211 |
Register Address [5211+] |
| AR5K_RX_FILTER_BCAST |
Don't filter broadcast frames |
| AR5K_RX_FILTER_BCAST |
Don't filter broadcast frames |
| AR5K_RX_FILTER_BEACON |
Don't filter beacon frames |
| AR5K_RX_FILTER_BEACON |
Don't filter beacon frames |
| AR5K_RX_FILTER_CONTROL |
Don't filter control frames |
| AR5K_RX_FILTER_CONTROL |
Don't filter control frames |
| AR5K_RX_FILTER_MCAST |
Don't filter multicast frames |
| AR5K_RX_FILTER_MCAST |
Don't filter multicast frames |
| AR5K_RX_FILTER_PHYERR |
|
| AR5K_RX_FILTER_PHYERR |
|
| AR5K_RX_FILTER_PHYERR_5211 |
[5211] |
| AR5K_RX_FILTER_PHYERR_5211 |
[5211] |
| AR5K_RX_FILTER_PHYERR_5212 |
Don't filter phy errors [5212+] |
| AR5K_RX_FILTER_PHYERR_5212 |
Don't filter phy errors [5212+] |
| AR5K_RX_FILTER_PROBEREQ |
Don't filter probe requests [5212+] |
| AR5K_RX_FILTER_PROBEREQ |
Don't filter probe requests [5212+] |
| AR5K_RX_FILTER_PROM |
Set promiscuous mode |
| AR5K_RX_FILTER_PROM |
Set promiscuous mode |
| AR5K_RX_FILTER_RADARERR |
|
| AR5K_RX_FILTER_RADARERR |
|
| AR5K_RX_FILTER_RADARERR_5211 |
[5211] |
| AR5K_RX_FILTER_RADARERR_5211 |
[5211] |
| AR5K_RX_FILTER_RADARERR_5212 |
Don't filter phy radar errors [5212+] |
| AR5K_RX_FILTER_RADARERR_5212 |
Don't filter phy radar errors [5212+] |
| AR5K_RX_FILTER_UCAST |
Don't filter unicast frames |
| AR5K_RX_FILTER_UCAST |
Don't filter unicast frames |
| AR5K_RX_FILTER_XRPOLL |
Don't filter XR poll frame [5212+] |
| AR5K_RX_FILTER_XRPOLL |
Don't filter XR poll frame [5212+] |
| AR5K_RXCFG |
Register Address |
| AR5K_RXCFG |
Register Address |
| AR5K_RXCFG_DEF_ANTENNA |
Default antenna (?) |
| AR5K_RXCFG_DEF_ANTENNA |
Default antenna (?) |
| AR5K_RXCFG_JUMBO_RXE |
Enable jumbo rx descriptors [5211+] |
| AR5K_RXCFG_JUMBO_RXE |
Enable jumbo rx descriptors [5211+] |
| AR5K_RXCFG_JUMBO_WRAP |
Wrap jumbo frames [5211+] |
| AR5K_RXCFG_JUMBO_WRAP |
Wrap jumbo frames [5211+] |
| AR5K_RXCFG_SDMAMW |
DMA size (write) |
| AR5K_RXCFG_SDMAMW |
DMA size (write) |
| AR5K_RXCFG_SDMAMW_S |
|
| AR5K_RXCFG_SDMAMW_S |
|
| AR5K_RXCFG_SLE_ENTRY |
Sleep entry policy |
| AR5K_RXCFG_SLE_ENTRY |
Sleep entry policy |
| AR5K_RXCFG_ZLFDMA |
Enable Zero-length frame DMA |
| AR5K_RXCFG_ZLFDMA |
Enable Zero-length frame DMA |
| AR5K_RXDESC_INTREQ |
|
| AR5K_RXDESC_INTREQ |
|
| AR5K_RXDP |
|
| AR5K_RXDP |
|
| AR5K_RXERR_CRC |
|
| AR5K_RXERR_CRC |
|
| AR5K_RXERR_DECRYPT |
|
| AR5K_RXERR_DECRYPT |
|
| AR5K_RXERR_FIFO |
|
| AR5K_RXERR_FIFO |
|
| AR5K_RXERR_MIC |
|
| AR5K_RXERR_MIC |
|
| AR5K_RXERR_PHY |
|
| AR5K_RXERR_PHY |
|
| AR5K_RXJLA |
|
| AR5K_RXJLA |
|
| AR5K_RXKEYIX_INVALID |
|
| AR5K_RXKEYIX_INVALID |
|
| AR5K_RXNOFRM |
|
| AR5K_RXNOFRM |
|
| AR5K_RXNOFRM_M |
|
| AR5K_RXNOFRM_M |
|
| AR5K_SEQ_MASK |
|
| AR5K_SEQ_MASK |
|
| AR5K_SET_SHORT_PREAMBLE |
|
| AR5K_SET_SHORT_PREAMBLE |
|
| AR5K_SFR |
|
| AR5K_SFR |
|
| AR5K_SFR_EN |
|
| AR5K_SFR_EN |
|
| AR5K_SIMR0 |
Register Address [5211+] |
| AR5K_SIMR0 |
Register Address [5211+] |
| AR5K_SIMR0_QCU_TXDESC |
Mask for QCU_TXDESC |
| AR5K_SIMR0_QCU_TXDESC |
Mask for QCU_TXDESC |
| AR5K_SIMR0_QCU_TXDESC_S |
|
| AR5K_SIMR0_QCU_TXDESC_S |
|
| AR5K_SIMR0_QCU_TXOK |
Mask for QCU_TXOK |
| AR5K_SIMR0_QCU_TXOK |
Mask for QCU_TXOK |
| AR5K_SIMR0_QCU_TXOK_S |
|
| AR5K_SIMR0_QCU_TXOK_S |
|
| AR5K_SIMR1 |
Register Address [5211+] |
| AR5K_SIMR1 |
Register Address [5211+] |
| AR5K_SIMR1_QCU_TXEOL |
Mask for QCU_TXEOL |
| AR5K_SIMR1_QCU_TXEOL |
Mask for QCU_TXEOL |
| AR5K_SIMR1_QCU_TXEOL_S |
|
| AR5K_SIMR1_QCU_TXEOL_S |
|
| AR5K_SIMR1_QCU_TXERR |
Mask for QCU_TXERR |
| AR5K_SIMR1_QCU_TXERR |
Mask for QCU_TXERR |
| AR5K_SIMR1_QCU_TXERR_S |
|
| AR5K_SIMR1_QCU_TXERR_S |
|
| AR5K_SIMR2 |
Register Address [5211+] |
| AR5K_SIMR2 |
Register Address [5211+] |
| AR5K_SIMR2_BCN_TIMEOUT |
Beacon Timeout [5212+] |
| AR5K_SIMR2_BCN_TIMEOUT |
Beacon Timeout [5212+] |
| AR5K_SIMR2_CAB_END |
[5212+] |
| AR5K_SIMR2_CAB_END |
[5212+] |
| AR5K_SIMR2_CAB_TIMEOUT |
CAB Timeout [5212+] |
| AR5K_SIMR2_CAB_TIMEOUT |
CAB Timeout [5212+] |
| AR5K_SIMR2_DPERR |
Bus parity error |
| AR5K_SIMR2_DPERR |
Bus parity error |
| AR5K_SIMR2_DTIM |
[5212+] |
| AR5K_SIMR2_DTIM |
[5212+] |
| AR5K_SIMR2_DTIM_SYNC |
DTIM Sync lost [5212+] |
| AR5K_SIMR2_DTIM_SYNC |
DTIM Sync lost [5212+] |
| AR5K_SIMR2_MCABT |
Master Cycle Abort |
| AR5K_SIMR2_MCABT |
Master Cycle Abort |
| AR5K_SIMR2_QCU_TXURN |
Mask for QCU_TXURN |
| AR5K_SIMR2_QCU_TXURN |
Mask for QCU_TXURN |
| AR5K_SIMR2_QCU_TXURN_S |
|
| AR5K_SIMR2_QCU_TXURN_S |
|
| AR5K_SIMR2_SSERR |
Signaled System Error |
| AR5K_SIMR2_SSERR |
Signaled System Error |
| AR5K_SIMR2_TIM |
[5212+] |
| AR5K_SIMR2_TIM |
[5212+] |
| AR5K_SIMR2_TSFOOR |
TSF OOR (?) |
| AR5K_SIMR2_TSFOOR |
TSF OOR (?) |
| AR5K_SIMR3 |
Register Address [5211+] |
| AR5K_SIMR3 |
Register Address [5211+] |
| AR5K_SIMR3_QCBRORN |
Mask for QCBRORN |
| AR5K_SIMR3_QCBRORN |
Mask for QCBRORN |
| AR5K_SIMR3_QCBRORN_S |
|
| AR5K_SIMR3_QCBRORN_S |
|
| AR5K_SIMR3_QCBRURN |
Mask for QCBRURN |
| AR5K_SIMR3_QCBRURN |
Mask for QCBRURN |
| AR5K_SIMR3_QCBRURN_S |
|
| AR5K_SIMR3_QCBRURN_S |
|
| AR5K_SIMR4 |
Register Address [5211+] |
| AR5K_SIMR4 |
Register Address [5211+] |
| AR5K_SIMR4_QTRIG |
Mask for QTRIG |
| AR5K_SIMR4_QTRIG |
Mask for QTRIG |
| AR5K_SIMR4_QTRIG_S |
|
| AR5K_SIMR4_QTRIG_S |
|
| AR5K_SISR0 |
Register Address [5211+] |
| AR5K_SISR0 |
Register Address [5211+] |
| AR5K_SISR0_QCU_TXDESC |
Mask for QCU_TXDESC |
| AR5K_SISR0_QCU_TXDESC |
Mask for QCU_TXDESC |
| AR5K_SISR0_QCU_TXDESC_S |
|
| AR5K_SISR0_QCU_TXDESC_S |
|
| AR5K_SISR0_QCU_TXOK |
Mask for QCU_TXOK |
| AR5K_SISR0_QCU_TXOK |
Mask for QCU_TXOK |
| AR5K_SISR0_QCU_TXOK_S |
|
| AR5K_SISR0_QCU_TXOK_S |
|
| AR5K_SISR1 |
Register Address [5211+] |
| AR5K_SISR1 |
Register Address [5211+] |
| AR5K_SISR1_QCU_TXEOL |
Mask for QCU_TXEOL |
| AR5K_SISR1_QCU_TXEOL |
Mask for QCU_TXEOL |
| AR5K_SISR1_QCU_TXEOL_S |
|
| AR5K_SISR1_QCU_TXEOL_S |
|
| AR5K_SISR1_QCU_TXERR |
Mask for QCU_TXERR |
| AR5K_SISR1_QCU_TXERR |
Mask for QCU_TXERR |
| AR5K_SISR1_QCU_TXERR_S |
|
| AR5K_SISR1_QCU_TXERR_S |
|
| AR5K_SISR2 |
Register Address [5211+] |
| AR5K_SISR2 |
Register Address [5211+] |
| AR5K_SISR2_BCN_TIMEOUT |
Beacon Timeout [5212+] |
| AR5K_SISR2_BCN_TIMEOUT |
Beacon Timeout [5212+] |
| AR5K_SISR2_CAB_END |
[5212+] |
| AR5K_SISR2_CAB_END |
[5212+] |
| AR5K_SISR2_CAB_TIMEOUT |
CAB Timeout [5212+] |
| AR5K_SISR2_CAB_TIMEOUT |
CAB Timeout [5212+] |
| AR5K_SISR2_DPERR |
Bus parity error |
| AR5K_SISR2_DPERR |
Bus parity error |
| AR5K_SISR2_DTIM |
[5212+] |
| AR5K_SISR2_DTIM |
[5212+] |
| AR5K_SISR2_DTIM_SYNC |
DTIM sync lost [5212+] |
| AR5K_SISR2_DTIM_SYNC |
DTIM sync lost [5212+] |
| AR5K_SISR2_MCABT |
Master Cycle Abort |
| AR5K_SISR2_MCABT |
Master Cycle Abort |
| AR5K_SISR2_QCU_TXURN |
Mask for QCU_TXURN |
| AR5K_SISR2_QCU_TXURN |
Mask for QCU_TXURN |
| AR5K_SISR2_QCU_TXURN_S |
|
| AR5K_SISR2_QCU_TXURN_S |
|
| AR5K_SISR2_SSERR |
Signaled System Error |
| AR5K_SISR2_SSERR |
Signaled System Error |
| AR5K_SISR2_TIM |
[5212+] |
| AR5K_SISR2_TIM |
[5212+] |
| AR5K_SISR2_TSFOOR |
TSF OOR (?) |
| AR5K_SISR2_TSFOOR |
TSF OOR (?) |
| AR5K_SISR3 |
Register Address [5211+] |
| AR5K_SISR3 |
Register Address [5211+] |
| AR5K_SISR3_QCBRORN |
Mask for QCBRORN |
| AR5K_SISR3_QCBRORN |
Mask for QCBRORN |
| AR5K_SISR3_QCBRORN_S |
|
| AR5K_SISR3_QCBRORN_S |
|
| AR5K_SISR3_QCBRURN |
Mask for QCBRURN |
| AR5K_SISR3_QCBRURN |
Mask for QCBRURN |
| AR5K_SISR3_QCBRURN_S |
|
| AR5K_SISR3_QCBRURN_S |
|
| AR5K_SISR4 |
Register Address [5211+] |
| AR5K_SISR4 |
Register Address [5211+] |
| AR5K_SISR4_QTRIG |
Mask for QTRIG |
| AR5K_SISR4_QTRIG |
Mask for QTRIG |
| AR5K_SISR4_QTRIG_S |
|
| AR5K_SISR4_QTRIG_S |
|
| AR5K_SLEEP_CTL |
Register Address |
| AR5K_SLEEP_CTL |
Register Address |
| AR5K_SLEEP_CTL_DUR_TIM_POL |
Sleep duration timing policy |
| AR5K_SLEEP_CTL_DUR_TIM_POL |
Sleep duration timing policy |
| AR5K_SLEEP_CTL_DUR_WRITE_POL |
Sleep duration write policy |
| AR5K_SLEEP_CTL_DUR_WRITE_POL |
Sleep duration write policy |
| AR5K_SLEEP_CTL_SLDUR |
Sleep duration mask |
| AR5K_SLEEP_CTL_SLDUR |
Sleep duration mask |
| AR5K_SLEEP_CTL_SLDUR_S |
|
| AR5K_SLEEP_CTL_SLDUR_S |
|
| AR5K_SLEEP_CTL_SLE |
Sleep enable mask |
| AR5K_SLEEP_CTL_SLE |
Sleep enable mask |
| AR5K_SLEEP_CTL_SLE_ALLOW |
Normal sleep policy |
| AR5K_SLEEP_CTL_SLE_ALLOW |
Normal sleep policy |
| AR5K_SLEEP_CTL_SLE_POL |
Sleep policy mode |
| AR5K_SLEEP_CTL_SLE_POL |
Sleep policy mode |
| AR5K_SLEEP_CTL_SLE_S |
|
| AR5K_SLEEP_CTL_SLE_S |
|
| AR5K_SLEEP_CTL_SLE_SLP |
Force chip sleep |
| AR5K_SLEEP_CTL_SLE_SLP |
Force chip sleep |
| AR5K_SLEEP_CTL_SLE_UNITS |
[5211+] |
| AR5K_SLEEP_CTL_SLE_UNITS |
[5211+] |
| AR5K_SLEEP_CTL_SLE_WAKE |
Force chip awake |
| AR5K_SLEEP_CTL_SLE_WAKE |
Force chip awake |
| AR5K_SLEEP0 |
Register Address |
| AR5K_SLEEP0 |
Register Address |
| AR5K_SLEEP0_ASSUME_DTIM |
Assume DTIM |
| AR5K_SLEEP0_ASSUME_DTIM |
Assume DTIM |
| AR5K_SLEEP0_CABTO |
Mask for CAB Time Out |
| AR5K_SLEEP0_CABTO |
Mask for CAB Time Out |
| AR5K_SLEEP0_CABTO_S |
|
| AR5K_SLEEP0_CABTO_S |
|
| AR5K_SLEEP0_ENH_SLEEP_EN |
Enable enchanced sleep control |
| AR5K_SLEEP0_ENH_SLEEP_EN |
Enable enchanced sleep control |
| AR5K_SLEEP0_NEXT_DTIM |
Mask for next DTIM (?) |
| AR5K_SLEEP0_NEXT_DTIM |
Mask for next DTIM (?) |
| AR5K_SLEEP0_NEXT_DTIM_S |
|
| AR5K_SLEEP0_NEXT_DTIM_S |
|
| AR5K_SLEEP1 |
Register Address |
| AR5K_SLEEP1 |
Register Address |
| AR5K_SLEEP1_BEACON_TO |
Mask for Beacon Time Out |
| AR5K_SLEEP1_BEACON_TO |
Mask for Beacon Time Out |
| AR5K_SLEEP1_BEACON_TO_S |
|
| AR5K_SLEEP1_BEACON_TO_S |
|
| AR5K_SLEEP1_NEXT_TIM |
Mask for next TIM (?) |
| AR5K_SLEEP1_NEXT_TIM |
Mask for next TIM (?) |
| AR5K_SLEEP1_NEXT_TIM_S |
|
| AR5K_SLEEP1_NEXT_TIM_S |
|
| AR5K_SLEEP2 |
Register Address |
| AR5K_SLEEP2 |
Register Address |
| AR5K_SLEEP2_DTIM_PER |
Mask for DTIM period (?) |
| AR5K_SLEEP2_DTIM_PER |
Mask for DTIM period (?) |
| AR5K_SLEEP2_DTIM_PER_S |
|
| AR5K_SLEEP2_DTIM_PER_S |
|
| AR5K_SLEEP2_TIM_PER |
Mask for TIM period (?) |
| AR5K_SLEEP2_TIM_PER |
Mask for TIM period (?) |
| AR5K_SLEEP2_TIM_PER_S |
|
| AR5K_SLEEP2_TIM_PER_S |
|
| AR5K_SLOT_TIME |
|
| AR5K_SLOT_TIME |
|
| AR5K_SLOT_TIME_20 |
|
| AR5K_SLOT_TIME_20 |
|
| AR5K_SLOT_TIME_9 |
|
| AR5K_SLOT_TIME_9 |
|
| AR5K_SLOT_TIME_MAX |
|
| AR5K_SLOT_TIME_MAX |
|
| AR5K_SOFTLED_OFF |
|
| AR5K_SOFTLED_OFF |
|
| AR5K_SOFTLED_ON |
|
| AR5K_SOFTLED_ON |
|
| AR5K_SOFTLED_PIN |
|
| AR5K_SOFTLED_PIN |
|
| AR5K_SREV |
Register Address |
| AR5K_SREV |
Register Address |
| AR5K_SREV_AR2413 |
Griffin lite |
| AR5K_SREV_AR2413 |
Griffin lite |
| AR5K_SREV_AR2414 |
Griffin |
| AR5K_SREV_AR2414 |
Griffin |
| AR5K_SREV_AR2415 |
Talon |
| AR5K_SREV_AR2415 |
Talon |
| AR5K_SREV_AR2417 |
Nala |
| AR5K_SREV_AR2417 |
Nala |
| AR5K_SREV_AR2425 |
Swan |
| AR5K_SREV_AR2425 |
Swan |
| AR5K_SREV_AR5210 |
Crete |
| AR5K_SREV_AR5210 |
Crete |
| AR5K_SREV_AR5211 |
Oahu |
| AR5K_SREV_AR5211 |
Oahu |
| AR5K_SREV_AR5212 |
Venice |
| AR5K_SREV_AR5212 |
Venice |
| AR5K_SREV_AR5213 |
??? |
| AR5K_SREV_AR5213 |
??? |
| AR5K_SREV_AR5213A |
Hainan |
| AR5K_SREV_AR5213A |
Hainan |
| AR5K_SREV_AR5311 |
Maui 1 |
| AR5K_SREV_AR5311 |
Maui 1 |
| AR5K_SREV_AR5311A |
Maui 2 |
| AR5K_SREV_AR5311A |
Maui 2 |
| AR5K_SREV_AR5311B |
Spirit |
| AR5K_SREV_AR5311B |
Spirit |
| AR5K_SREV_AR5413 |
Eagle lite |
| AR5K_SREV_AR5413 |
Eagle lite |
| AR5K_SREV_AR5414 |
Eagle |
| AR5K_SREV_AR5414 |
Eagle |
| AR5K_SREV_AR5416 |
PCI-E |
| AR5K_SREV_AR5416 |
PCI-E |
| AR5K_SREV_AR5418 |
PCI-E |
| AR5K_SREV_AR5418 |
PCI-E |
| AR5K_SREV_AR5424 |
Condor |
| AR5K_SREV_AR5424 |
Condor |
| AR5K_SREV_PHY_2413 |
|
| AR5K_SREV_PHY_2413 |
|
| AR5K_SREV_PHY_2425 |
|
| AR5K_SREV_PHY_2425 |
|
| AR5K_SREV_PHY_5211 |
|
| AR5K_SREV_PHY_5211 |
|
| AR5K_SREV_PHY_5212 |
|
| AR5K_SREV_PHY_5212 |
|
| AR5K_SREV_PHY_5212A |
|
| AR5K_SREV_PHY_5212A |
|
| AR5K_SREV_PHY_5212B |
|
| AR5K_SREV_PHY_5212B |
|
| AR5K_SREV_PHY_5413 |
|
| AR5K_SREV_PHY_5413 |
|
| AR5K_SREV_RAD_2111 |
|
| AR5K_SREV_RAD_2111 |
|
| AR5K_SREV_RAD_2112 |
|
| AR5K_SREV_RAD_2112 |
|
| AR5K_SREV_RAD_2112A |
|
| AR5K_SREV_RAD_2112A |
|
| AR5K_SREV_RAD_2112B |
|
| AR5K_SREV_RAD_2112B |
|
| AR5K_SREV_RAD_2316 |
Cobra SoC |
| AR5K_SREV_RAD_2316 |
Cobra SoC |
| AR5K_SREV_RAD_2317 |
|
| AR5K_SREV_RAD_2317 |
|
| AR5K_SREV_RAD_2413 |
|
| AR5K_SREV_RAD_2413 |
|
| AR5K_SREV_RAD_2425 |
|
| AR5K_SREV_RAD_2425 |
|
| AR5K_SREV_RAD_5110 |
|
| AR5K_SREV_RAD_5110 |
|
| AR5K_SREV_RAD_5111 |
|
| AR5K_SREV_RAD_5111 |
|
| AR5K_SREV_RAD_5111A |
|
| AR5K_SREV_RAD_5111A |
|
| AR5K_SREV_RAD_5112 |
|
| AR5K_SREV_RAD_5112 |
|
| AR5K_SREV_RAD_5112A |
|
| AR5K_SREV_RAD_5112A |
|
| AR5K_SREV_RAD_5112B |
|
| AR5K_SREV_RAD_5112B |
|
| AR5K_SREV_RAD_5133 |
|
| AR5K_SREV_RAD_5133 |
|
| AR5K_SREV_RAD_5413 |
|
| AR5K_SREV_RAD_5413 |
|
| AR5K_SREV_RAD_5424 |
Mostly same as 5413 |
| AR5K_SREV_RAD_5424 |
Mostly same as 5413 |
| AR5K_SREV_REV |
Mask for revision |
| AR5K_SREV_REV |
Mask for revision |
| AR5K_SREV_REV_S |
|
| AR5K_SREV_REV_S |
|
| AR5K_SREV_UNKNOWN |
|
| AR5K_SREV_UNKNOWN |
|
| AR5K_SREV_VER |
Mask for version |
| AR5K_SREV_VER |
Mask for version |
| AR5K_SREV_VER_S |
|
| AR5K_SREV_VER_S |
|
| AR5K_STA_ID0 |
|
| AR5K_STA_ID0 |
|
| AR5K_STA_ID0_ARRD_L32 |
|
| AR5K_STA_ID0_ARRD_L32 |
|
| AR5K_STA_ID1 |
Register Address |
| AR5K_STA_ID1 |
Register Address |
| AR5K_STA_ID1_ACKCTS_6MB |
Use 6Mbit/s for ACK/CTS |
| AR5K_STA_ID1_ACKCTS_6MB |
Use 6Mbit/s for ACK/CTS |
| AR5K_STA_ID1_ADDR_U16 |
Upper 16 bits of MAC addres |
| AR5K_STA_ID1_ADDR_U16 |
Upper 16 bits of MAC addres |
| AR5K_STA_ID1_ADHOC |
Set Ad-Hoc mode |
| AR5K_STA_ID1_ADHOC |
Set Ad-Hoc mode |
| AR5K_STA_ID1_AP |
Set AP mode |
| AR5K_STA_ID1_AP |
Set AP mode |
| AR5K_STA_ID1_BASE_RATE_11B |
Use 11b base rate for ACK/CTS [5211+] |
| AR5K_STA_ID1_BASE_RATE_11B |
Use 11b base rate for ACK/CTS [5211+] |
| AR5K_STA_ID1_CBCIV_ENDIAN |
??? |
| AR5K_STA_ID1_CBCIV_ENDIAN |
??? |
| AR5K_STA_ID1_CRYPT_MIC_EN |
Enable MIC |
| AR5K_STA_ID1_CRYPT_MIC_EN |
Enable MIC |
| AR5K_STA_ID1_DEFAULT_ANTENNA |
Use default antenna |
| AR5K_STA_ID1_DEFAULT_ANTENNA |
Use default antenna |
| AR5K_STA_ID1_DESC_ANTENNA |
Update antenna from descriptor |
| AR5K_STA_ID1_DESC_ANTENNA |
Update antenna from descriptor |
| AR5K_STA_ID1_KEYSRCH_MCAST |
Do key cache search for mcast frames |
| AR5K_STA_ID1_KEYSRCH_MCAST |
Do key cache search for mcast frames |
| AR5K_STA_ID1_KEYSRCH_MODE |
Look up key when key id != 0 |
| AR5K_STA_ID1_KEYSRCH_MODE |
Look up key when key id != 0 |
| AR5K_STA_ID1_NO_KEYSRCH |
No key search |
| AR5K_STA_ID1_NO_KEYSRCH |
No key search |
| AR5K_STA_ID1_NO_PSPOLL |
No power save polling [5210] |
| AR5K_STA_ID1_NO_PSPOLL |
No power save polling [5210] |
| AR5K_STA_ID1_PCF |
|
| AR5K_STA_ID1_PCF |
|
| AR5K_STA_ID1_PCF_5210 |
Enable PCF on [5210] |
| AR5K_STA_ID1_PCF_5210 |
Enable PCF on [5210] |
| AR5K_STA_ID1_PCF_5211 |
Enable PCF on [5211+] |
| AR5K_STA_ID1_PCF_5211 |
Enable PCF on [5211+] |
| AR5K_STA_ID1_PRESERVE_SEQ_NUM |
Preserve sequence number |
| AR5K_STA_ID1_PRESERVE_SEQ_NUM |
Preserve sequence number |
| AR5K_STA_ID1_PWR_SV |
Power save reporting |
| AR5K_STA_ID1_PWR_SV |
Power save reporting |
| AR5K_STA_ID1_RTS_DEF_ANTENNA |
Use default antenna for RTS |
| AR5K_STA_ID1_RTS_DEF_ANTENNA |
Use default antenna for RTS |
| AR5K_STA_ID1_SELFGEN_DEF_ANT |
Use def. antenna for self generated frames |
| AR5K_STA_ID1_SELFGEN_DEF_ANT |
Use def. antenna for self generated frames |
| AR5K_TIME_OUT |
Register Address |
| AR5K_TIME_OUT |
Register Address |
| AR5K_TIME_OUT_ACK |
ACK timeout mask |
| AR5K_TIME_OUT_ACK |
ACK timeout mask |
| AR5K_TIME_OUT_ACK_S |
|
| AR5K_TIME_OUT_ACK_S |
|
| AR5K_TIME_OUT_CTS |
CTS timeout mask |
| AR5K_TIME_OUT_CTS |
CTS timeout mask |
| AR5K_TIME_OUT_CTS_S |
|
| AR5K_TIME_OUT_CTS_S |
|
| AR5K_TIMER0 |
|
| AR5K_TIMER0 |
|
| AR5K_TIMER0_5210 |
|
| AR5K_TIMER0_5210 |
|
| AR5K_TIMER0_5211 |
|
| AR5K_TIMER0_5211 |
|
| AR5K_TIMER1 |
|
| AR5K_TIMER1 |
|
| AR5K_TIMER1_5210 |
|
| AR5K_TIMER1_5210 |
|
| AR5K_TIMER1_5211 |
|
| AR5K_TIMER1_5211 |
|
| AR5K_TIMER2 |
|
| AR5K_TIMER2 |
|
| AR5K_TIMER2_5210 |
|
| AR5K_TIMER2_5210 |
|
| AR5K_TIMER2_5211 |
|
| AR5K_TIMER2_5211 |
|
| AR5K_TIMER3 |
|
| AR5K_TIMER3 |
|
| AR5K_TIMER3_5210 |
|
| AR5K_TIMER3_5210 |
|
| AR5K_TIMER3_5211 |
|
| AR5K_TIMER3_5211 |
|
| AR5K_TOPS |
|
| AR5K_TOPS |
|
| AR5K_TOPS_M |
|
| AR5K_TOPS_M |
|
| AR5K_TPC |
|
| AR5K_TPC |
|
| AR5K_TPC_ACK |
ack frames |
| AR5K_TPC_ACK |
ack frames |
| AR5K_TPC_ACK_S |
|
| AR5K_TPC_ACK_S |
|
| AR5K_TPC_CHIRP |
chirp frames |
| AR5K_TPC_CHIRP |
chirp frames |
| AR5K_TPC_CHIRP_S |
|
| AR5K_TPC_CHIRP_S |
|
| AR5K_TPC_CTS |
cts frames |
| AR5K_TPC_CTS |
cts frames |
| AR5K_TPC_CTS_S |
|
| AR5K_TPC_CTS_S |
|
| AR5K_TPC_DOPPLER |
doppler chirp span |
| AR5K_TPC_DOPPLER |
doppler chirp span |
| AR5K_TPC_DOPPLER_S |
|
| AR5K_TPC_DOPPLER_S |
|
| AR5K_TRIG_LVL |
|
| AR5K_TRIG_LVL |
|
| AR5K_TSF_L32 |
|
| AR5K_TSF_L32 |
|
| AR5K_TSF_L32_5210 |
|
| AR5K_TSF_L32_5210 |
|
| AR5K_TSF_L32_5211 |
|
| AR5K_TSF_L32_5211 |
|
| AR5K_TSF_PARM |
Register Address |
| AR5K_TSF_PARM |
Register Address |
| AR5K_TSF_PARM_INC |
Mask for TSF increment |
| AR5K_TSF_PARM_INC |
Mask for TSF increment |
| AR5K_TSF_PARM_INC_S |
|
| AR5K_TSF_PARM_INC_S |
|
| AR5K_TSF_THRES |
|
| AR5K_TSF_THRES |
|
| AR5K_TSF_U32 |
|
| AR5K_TSF_U32 |
|
| AR5K_TSF_U32_5210 |
|
| AR5K_TSF_U32_5210 |
|
| AR5K_TSF_U32_5211 |
|
| AR5K_TSF_U32_5211 |
|
| AR5K_TUNE_ADDITIONAL_SWBA_BACKO |
|
| AR5K_TUNE_ADDITIONAL_SWBA_BACKO |
|
| AR5K_TUNE_AIFS |
|
| AR5K_TUNE_AIFS |
|
| AR5K_TUNE_AIFS_11B |
|
| AR5K_TUNE_AIFS_11B |
|
| AR5K_TUNE_AIFS_XR |
|
| AR5K_TUNE_AIFS_XR |
|
| AR5K_TUNE_ANT_DIVERSITY |
|
| AR5K_TUNE_ANT_DIVERSITY |
|
| AR5K_TUNE_BEACON_INTERVAL |
|
| AR5K_TUNE_BEACON_INTERVAL |
|
| AR5K_TUNE_BMISS_THRES |
|
| AR5K_TUNE_BMISS_THRES |
|
| AR5K_TUNE_CWMAX |
|
| AR5K_TUNE_CWMAX |
|
| AR5K_TUNE_CWMAX_11B |
|
| AR5K_TUNE_CWMAX_11B |
|
| AR5K_TUNE_CWMAX_XR |
|
| AR5K_TUNE_CWMAX_XR |
|
| AR5K_TUNE_CWMIN |
|
| AR5K_TUNE_CWMIN |
|
| AR5K_TUNE_CWMIN_11B |
|
| AR5K_TUNE_CWMIN_11B |
|
| AR5K_TUNE_CWMIN_XR |
|
| AR5K_TUNE_CWMIN_XR |
|
| AR5K_TUNE_DEFAULT_TXPOWER |
|
| AR5K_TUNE_DEFAULT_TXPOWER |
|
| AR5K_TUNE_DMA_BEACON_RESP |
|
| AR5K_TUNE_DMA_BEACON_RESP |
|
| AR5K_TUNE_HWTXTRIES |
|
| AR5K_TUNE_HWTXTRIES |
|
| AR5K_TUNE_MAX_TX_FIFO_THRES |
|
| AR5K_TUNE_MAX_TX_FIFO_THRES |
|
| AR5K_TUNE_MAX_TXPOWER |
|
| AR5K_TUNE_MAX_TXPOWER |
|
| AR5K_TUNE_MIN_TX_FIFO_THRES |
|
| AR5K_TUNE_MIN_TX_FIFO_THRES |
|
| AR5K_TUNE_NOISE_FLOOR |
|
| AR5K_TUNE_NOISE_FLOOR |
|
| AR5K_TUNE_RADAR_ALERT |
|
| AR5K_TUNE_RADAR_ALERT |
|
| AR5K_TUNE_REGISTER_DWELL_TIME |
|
| AR5K_TUNE_REGISTER_DWELL_TIME |
|
| AR5K_TUNE_REGISTER_TIMEOUT |
|
| AR5K_TUNE_REGISTER_TIMEOUT |
|
| AR5K_TUNE_RSSI_THRES |
|
| AR5K_TUNE_RSSI_THRES |
|
| AR5K_TUNE_SW_BEACON_RESP |
|
| AR5K_TUNE_SW_BEACON_RESP |
|
| AR5K_TUNE_TPC_TXPOWER |
|
| AR5K_TUNE_TPC_TXPOWER |
|
| AR5K_TX_MASK0 |
|
| AR5K_TX_MASK0 |
|
| AR5K_TX_MASK1 |
|
| AR5K_TX_MASK1 |
|
| AR5K_TXCFG |
Register Address |
| AR5K_TXCFG |
Register Address |
| AR5K_TXCFG_ADHOC_BCN_ATIM |
Adhoc Beacon ATIM Policy |
| AR5K_TXCFG_ADHOC_BCN_ATIM |
Adhoc Beacon ATIM Policy |
| AR5K_TXCFG_ATIM_WINDOW_DEF_DIS |
Disable ATIM window defer [5211+] |
| AR5K_TXCFG_ATIM_WINDOW_DEF_DIS |
Disable ATIM window defer [5211+] |
| AR5K_TXCFG_B_MODE |
Set b mode for 5111 (enable 2111) |
| AR5K_TXCFG_B_MODE |
Set b mode for 5111 (enable 2111) |
| AR5K_TXCFG_DCU_CACHING_DIS |
Disable DCU caching |
| AR5K_TXCFG_DCU_CACHING_DIS |
Disable DCU caching |
| AR5K_TXCFG_DCU_DBL_BUF_DIS |
Disable double buffering on DCU |
| AR5K_TXCFG_DCU_DBL_BUF_DIS |
Disable double buffering on DCU |
| AR5K_TXCFG_DMASIZE |
Flag for passing DMA size [5210] |
| AR5K_TXCFG_DMASIZE |
Flag for passing DMA size [5210] |
| AR5K_TXCFG_FRMPAD_DIS |
[5211+] |
| AR5K_TXCFG_FRMPAD_DIS |
[5211+] |
| AR5K_TXCFG_JUMBO_DESC_EN |
Enable jumbo tx descriptors [5211+] |
| AR5K_TXCFG_JUMBO_DESC_EN |
Enable jumbo tx descriptors [5211+] |
| AR5K_TXCFG_JUMBO_FRM_MODE |
Jumbo frame mode [5211+] |
| AR5K_TXCFG_JUMBO_FRM_MODE |
Jumbo frame mode [5211+] |
| AR5K_TXCFG_RDY_CBR_DIS |
Ready time CBR disable [5211+] |
| AR5K_TXCFG_RDY_CBR_DIS |
Ready time CBR disable [5211+] |
| AR5K_TXCFG_RTSRND |
[5211+] |
| AR5K_TXCFG_RTSRND |
[5211+] |
| AR5K_TXCFG_SDMAMR |
DMA size (read) |
| AR5K_TXCFG_SDMAMR |
DMA size (read) |
| AR5K_TXCFG_SDMAMR_S |
|
| AR5K_TXCFG_SDMAMR_S |
|
| AR5K_TXCFG_TXCONT_EN |
|
| AR5K_TXCFG_TXCONT_EN |
|
| AR5K_TXCFG_TXFSTP |
TX DMA full Stop [5210] |
| AR5K_TXCFG_TXFSTP |
TX DMA full Stop [5210] |
| AR5K_TXCFG_TXFULL |
TX Triger level mask |
| AR5K_TXCFG_TXFULL |
TX Triger level mask |
| AR5K_TXCFG_TXFULL_0B |
|
| AR5K_TXCFG_TXFULL_0B |
|
| AR5K_TXCFG_TXFULL_128B |
|
| AR5K_TXCFG_TXFULL_128B |
|
| AR5K_TXCFG_TXFULL_192B |
|
| AR5K_TXCFG_TXFULL_192B |
|
| AR5K_TXCFG_TXFULL_256B |
|
| AR5K_TXCFG_TXFULL_256B |
|
| AR5K_TXCFG_TXFULL_64B |
|
| AR5K_TXCFG_TXFULL_64B |
|
| AR5K_TXCFG_TXFULL_S |
|
| AR5K_TXCFG_TXFULL_S |
|
| AR5K_TXDESC_CLRDMASK |
|
| AR5K_TXDESC_CLRDMASK |
|
| AR5K_TXDESC_CTSENA |
|
| AR5K_TXDESC_CTSENA |
|
| AR5K_TXDESC_INTREQ |
|
| AR5K_TXDESC_INTREQ |
|
| AR5K_TXDESC_NOACK |
[5211+] |
| AR5K_TXDESC_NOACK |
[5211+] |
| AR5K_TXDESC_RTSENA |
|
| AR5K_TXDESC_RTSENA |
|
| AR5K_TXDESC_VEOL |
[5211+] |
| AR5K_TXDESC_VEOL |
[5211+] |
| AR5K_TXEPOST |
|
| AR5K_TXEPOST |
|
| AR5K_TXERR_FIFO |
|
| AR5K_TXERR_FIFO |
|
| AR5K_TXERR_FILT |
|
| AR5K_TXERR_FILT |
|
| AR5K_TXERR_XRETRY |
|
| AR5K_TXERR_XRETRY |
|
| AR5K_TXKEYIX_INVALID |
|
| AR5K_TXKEYIX_INVALID |
|
| AR5K_TXNOFRM |
|
| AR5K_TXNOFRM |
|
| AR5K_TXNOFRM_M |
|
| AR5K_TXNOFRM_M |
|
| AR5K_TXNOFRM_QCU |
|
| AR5K_TXNOFRM_QCU |
|
| AR5K_TXNOFRM_QCU_S |
|
| AR5K_TXNOFRM_QCU_S |
|
| AR5K_TXPC |
Register Address |
| AR5K_TXPC |
Register Address |
| AR5K_TXPC_ACK_M |
ACK tx power |
| AR5K_TXPC_ACK_M |
ACK tx power |
| AR5K_TXPC_ACK_S |
|
| AR5K_TXPC_ACK_S |
|
| AR5K_TXPC_CHIRP_M |
CHIRP tx power |
| AR5K_TXPC_CHIRP_M |
CHIRP tx power |
| AR5K_TXPC_CHIRP_S |
|
| AR5K_TXPC_CHIRP_S |
|
| AR5K_TXPC_CTS_M |
CTS tx power |
| AR5K_TXPC_CTS_M |
CTS tx power |
| AR5K_TXPC_CTS_S |
|
| AR5K_TXPC_CTS_S |
|
| AR5K_TXPC_DOPPLER |
Doppler chirp span (?) |
| AR5K_TXPC_DOPPLER |
Doppler chirp span (?) |
| AR5K_TXPC_DOPPLER_S |
|
| AR5K_TXPC_DOPPLER_S |
|
| AR5K_TXPOWER_CCK(_r, _v) |
|
| AR5K_TXPOWER_CCK(_r, _v) |
|
| AR5K_TXPOWER_OFDM(_r, _v) |
|
| AR5K_TXPOWER_OFDM(_r, _v) |
|
| AR5K_TXQ_FLAG_BACKOFF_DISABLE |
Disable random post-backoff |
| AR5K_TXQ_FLAG_BACKOFF_DISABLE |
Disable random post-backoff |
| AR5K_TXQ_FLAG_CBRORNINT_ENABLE |
Enable CBRORN interrupt |
| AR5K_TXQ_FLAG_CBRORNINT_ENABLE |
Enable CBRORN interrupt |
| AR5K_TXQ_FLAG_CBRURNINT_ENABLE |
Enable CBRURN interrupt |
| AR5K_TXQ_FLAG_CBRURNINT_ENABLE |
Enable CBRURN interrupt |
| AR5K_TXQ_FLAG_COMPRESSION_ENABL |
Enable hw compression -not implemented- |
| AR5K_TXQ_FLAG_COMPRESSION_ENABL |
Enable hw compression -not implemented- |
| AR5K_TXQ_FLAG_FRAG_BURST_BACKOF |
Enable backoff while bursting |
| AR5K_TXQ_FLAG_FRAG_BURST_BACKOF |
Enable backoff while bursting |
| AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS |
Disable backoff while bursting |
| AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS |
Disable backoff while bursting |
| AR5K_TXQ_FLAG_QTRIGINT_ENABLE |
Enable QTRIG interrupt |
| AR5K_TXQ_FLAG_QTRIGINT_ENABLE |
Enable QTRIG interrupt |
| AR5K_TXQ_FLAG_RDYTIME_EXP_POLIC |
Enable ready time expiry policy (?) |
| AR5K_TXQ_FLAG_RDYTIME_EXP_POLIC |
Enable ready time expiry policy (?) |
| AR5K_TXQ_FLAG_TXDESCINT_ENABLE |
Enable TXDESC interrupt -not used- |
| AR5K_TXQ_FLAG_TXDESCINT_ENABLE |
Enable TXDESC interrupt -not used- |
| AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
Enable TXEOL interrupt -not used- |
| AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
Enable TXEOL interrupt -not used- |
| AR5K_TXQ_FLAG_TXERRINT_ENABLE |
Enable TXERR interrupt |
| AR5K_TXQ_FLAG_TXERRINT_ENABLE |
Enable TXERR interrupt |
| AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE |
Enable TXNOFRM interrupt |
| AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE |
Enable TXNOFRM interrupt |
| AR5K_TXQ_FLAG_TXOKINT_ENABLE |
Enable TXOK interrupt |
| AR5K_TXQ_FLAG_TXOKINT_ENABLE |
Enable TXOK interrupt |
| AR5K_TXQ_FLAG_TXURNINT_ENABLE |
Enable TXURN interrupt |
| AR5K_TXQ_FLAG_TXURNINT_ENABLE |
Enable TXURN interrupt |
| AR5K_TXQ_USEDEFAULT |
|
| AR5K_TXQ_USEDEFAULT |
|
| AR5K_TXSTAT_ALTRATE |
|
| AR5K_TXSTAT_ALTRATE |
|
| AR5K_USEC |
|
| AR5K_USEC |
|
| AR5K_USEC_1 |
clock cycles for 1us |
| AR5K_USEC_1 |
clock cycles for 1us |
| AR5K_USEC_1_S |
|
| AR5K_USEC_1_S |
|
| AR5K_USEC_32 |
clock cycles for 1us while on 32Mhz clock |
| AR5K_USEC_32 |
clock cycles for 1us while on 32Mhz clock |
| AR5K_USEC_32_S |
|
| AR5K_USEC_32_S |
|
| AR5K_USEC_5210 |
Register Address [5210] |
| AR5K_USEC_5210 |
Register Address [5210] |
| AR5K_USEC_5211 |
Register Address [5211+] |
| AR5K_USEC_5211 |
Register Address [5211+] |
| AR5K_USEC_RX_LATENCY_5210 |
also for 5311 |
| AR5K_USEC_RX_LATENCY_5210 |
also for 5311 |
| AR5K_USEC_RX_LATENCY_5210_S |
|
| AR5K_USEC_RX_LATENCY_5210_S |
|
| AR5K_USEC_RX_LATENCY_5211 |
|
| AR5K_USEC_RX_LATENCY_5211 |
|
| AR5K_USEC_RX_LATENCY_5211_S |
|
| AR5K_USEC_RX_LATENCY_5211_S |
|
| AR5K_USEC_TX_LATENCY_5210 |
also for 5311 |
| AR5K_USEC_TX_LATENCY_5210 |
also for 5311 |
| AR5K_USEC_TX_LATENCY_5210_S |
|
| AR5K_USEC_TX_LATENCY_5210_S |
|
| AR5K_USEC_TX_LATENCY_5211 |
|
| AR5K_USEC_TX_LATENCY_5211 |
|
| AR5K_USEC_TX_LATENCY_5211_S |
|
| AR5K_USEC_TX_LATENCY_5211_S |
|
| AR5K_WOW_PAT_DATA |
Register Address |
| AR5K_WOW_PAT_DATA |
Register Address |
| AR5K_WOW_PAT_DATA_0_3_M |
Pattern 0, 3 mask |
| AR5K_WOW_PAT_DATA_0_3_M |
Pattern 0, 3 mask |
| AR5K_WOW_PAT_DATA_0_3_V |
Pattern 0, 3 value |
| AR5K_WOW_PAT_DATA_0_3_V |
Pattern 0, 3 value |
| AR5K_WOW_PAT_DATA_1_4_M |
Pattern 1, 4 mask |
| AR5K_WOW_PAT_DATA_1_4_M |
Pattern 1, 4 mask |
| AR5K_WOW_PAT_DATA_1_4_V |
Pattern 1, 4 value |
| AR5K_WOW_PAT_DATA_1_4_V |
Pattern 1, 4 value |
| AR5K_WOW_PAT_DATA_2_5_M |
Pattern 2, 5 mask |
| AR5K_WOW_PAT_DATA_2_5_M |
Pattern 2, 5 mask |
| AR5K_WOW_PAT_DATA_2_5_V |
Pattern 2, 5 value |
| AR5K_WOW_PAT_DATA_2_5_V |
Pattern 2, 5 value |
| AR5K_WOW_PAT_IDX |
|
| AR5K_WOW_PAT_IDX |
|
| AR5K_WOW_PCFG |
Register Address |
| AR5K_WOW_PCFG |
Register Address |
| AR5K_WOW_PCFG_LONG_FRAME_POL |
Long frame policy |
| AR5K_WOW_PCFG_LONG_FRAME_POL |
Long frame policy |
| AR5K_WOW_PCFG_PAT_0_EN |
Enable pattern 0 |
| AR5K_WOW_PCFG_PAT_0_EN |
Enable pattern 0 |
| AR5K_WOW_PCFG_PAT_1_EN |
Enable pattern 1 |
| AR5K_WOW_PCFG_PAT_1_EN |
Enable pattern 1 |
| AR5K_WOW_PCFG_PAT_2_EN |
Enable pattern 2 |
| AR5K_WOW_PCFG_PAT_2_EN |
Enable pattern 2 |
| AR5K_WOW_PCFG_PAT_3_EN |
Enable pattern 3 |
| AR5K_WOW_PCFG_PAT_3_EN |
Enable pattern 3 |
| AR5K_WOW_PCFG_PAT_4_EN |
Enable pattern 4 |
| AR5K_WOW_PCFG_PAT_4_EN |
Enable pattern 4 |
| AR5K_WOW_PCFG_PAT_5_EN |
Enable pattern 5 |
| AR5K_WOW_PCFG_PAT_5_EN |
Enable pattern 5 |
| AR5K_WOW_PCFG_PAT_MATCH_EN |
Pattern match enable |
| AR5K_WOW_PCFG_PAT_MATCH_EN |
Pattern match enable |
| AR5K_WOW_PCFG_WOBMISS |
Wake on bea(con) miss (?) |
| AR5K_WOW_PCFG_WOBMISS |
Wake on bea(con) miss (?) |
| AR5K_XRCHIRP |
Register Address |
| AR5K_XRCHIRP |
Register Address |
| AR5K_XRCHIRP_GAP |
Mask for CHIRP gap (?) |
| AR5K_XRCHIRP_GAP |
Mask for CHIRP gap (?) |
| AR5K_XRCHIRP_SEND |
Send CHIRP |
| AR5K_XRCHIRP_SEND |
Send CHIRP |
| AR5K_XRDELAY |
Register Address |
| AR5K_XRDELAY |
Register Address |
| AR5K_XRDELAY_CHIRP_DELAY_M |
Mask for CHIRP data delay |
| AR5K_XRDELAY_CHIRP_DELAY_M |
Mask for CHIRP data delay |
| AR5K_XRDELAY_CHIRP_DELAY_S |
|
| AR5K_XRDELAY_CHIRP_DELAY_S |
|
| AR5K_XRDELAY_SLOT_DELAY_M |
Mask for slot delay |
| AR5K_XRDELAY_SLOT_DELAY_M |
Mask for slot delay |
| AR5K_XRDELAY_SLOT_DELAY_S |
|
| AR5K_XRDELAY_SLOT_DELAY_S |
|
| AR5K_XRLAT_TX |
|
| AR5K_XRLAT_TX |
|
| AR5K_XRMODE |
Register Address |
| AR5K_XRMODE |
Register Address |
| AR5K_XRMODE_FRAME_HOLD_M |
Mask for frame hold (?) |
| AR5K_XRMODE_FRAME_HOLD_M |
Mask for frame hold (?) |
| AR5K_XRMODE_FRAME_HOLD_S |
|
| AR5K_XRMODE_FRAME_HOLD_S |
|
| AR5K_XRMODE_POLL_SUBTYPE_M |
Mask for Poll subtype (?) |
| AR5K_XRMODE_POLL_SUBTYPE_M |
Mask for Poll subtype (?) |
| AR5K_XRMODE_POLL_SUBTYPE_S |
|
| AR5K_XRMODE_POLL_SUBTYPE_S |
|
| AR5K_XRMODE_POLL_TYPE_M |
Mask for Poll type (?) |
| AR5K_XRMODE_POLL_TYPE_M |
Mask for Poll type (?) |
| AR5K_XRMODE_POLL_TYPE_S |
|
| AR5K_XRMODE_POLL_TYPE_S |
|
| AR5K_XRMODE_POLL_WAIT_ALL |
Wait for poll |
| AR5K_XRMODE_POLL_WAIT_ALL |
Wait for poll |
| AR5K_XRMODE_SIFS_DELAY |
Mask for SIFS delay |
| AR5K_XRMODE_SIFS_DELAY |
Mask for SIFS delay |
| AR5K_XRSTOMP |
Register Address |
| AR5K_XRSTOMP |
Register Address |
| AR5K_XRSTOMP_DATA |
Stomp data (?) |
| AR5K_XRSTOMP_DATA |
Stomp data (?) |
| AR5K_XRSTOMP_RSSI_THRES |
Mask for XR RSSI threshold |
| AR5K_XRSTOMP_RSSI_THRES |
Mask for XR RSSI threshold |
| AR5K_XRSTOMP_RX |
Stomp Rx (?) |
| AR5K_XRSTOMP_RX |
Stomp Rx (?) |
| AR5K_XRSTOMP_TX |
Stomp Tx (?) |
| AR5K_XRSTOMP_TX |
Stomp Tx (?) |
| AR5K_XRSTOMP_TX_BSSID |
Stomp Tx BSSID (?) |
| AR5K_XRSTOMP_TX_BSSID |
Stomp Tx BSSID (?) |
| AR5K_XRSTOMP_TX_RSSI |
Stomp Tx RSSI (?) |
| AR5K_XRSTOMP_TX_RSSI |
Stomp Tx RSSI (?) |
| AR5K_XRTIMEOUT |
Register Address |
| AR5K_XRTIMEOUT |
Register Address |
| AR5K_XRTIMEOUT_CHIRP_M |
Mask for CHIRP timeout |
| AR5K_XRTIMEOUT_CHIRP_M |
Mask for CHIRP timeout |
| AR5K_XRTIMEOUT_CHIRP_S |
|
| AR5K_XRTIMEOUT_CHIRP_S |
|
| AR5K_XRTIMEOUT_POLL_M |
Mask for Poll timeout |
| AR5K_XRTIMEOUT_POLL_M |
Mask for Poll timeout |
| AR5K_XRTIMEOUT_POLL_S |
|
| AR5K_XRTIMEOUT_POLL_S |
|
| arbel |
|
| arbel |
|
| arbel.c |
|
| arbel.c |
|
| arbel.h |
|
| arbel.h |
|
| arbel_alloc_icm |
Allocate ICM |
| arbel_alloc_icm |
Allocate ICM |
| arbel_alloc_qn_offset |
@file |
| arbel_alloc_qn_offset |
@file |
| ARBEL_BITMASK_SIZE(max_entries) |
|
| ARBEL_BITMASK_SIZE(max_entries) |
|
| arbel_close |
Close Infiniband link |
| arbel_close |
Close Infiniband link |
| arbel_cmd |
Issue HCA command |
| arbel_cmd |
Issue HCA command |
| arbel_cmd_2rst_qpee |
|
| arbel_cmd_2rst_qpee |
|
| arbel_cmd_close_hca |
|
| arbel_cmd_close_hca |
|
| arbel_cmd_close_ib |
|
| arbel_cmd_close_ib |
|
| arbel_cmd_disable_lam |
|
| arbel_cmd_disable_lam |
|
| arbel_cmd_enable_lam |
|
| arbel_cmd_enable_lam |
|
| arbel_cmd_hw2sw_cq |
|
| arbel_cmd_hw2sw_cq |
|
| arbel_cmd_hw2sw_eq |
|
| arbel_cmd_hw2sw_eq |
|
| arbel_cmd_init_hca |
|
| arbel_cmd_init_hca |
|
| arbel_cmd_init_ib |
|
| arbel_cmd_init_ib |
|
| arbel_cmd_init2rtr_qpee |
|
| arbel_cmd_init2rtr_qpee |
|
| arbel_cmd_mad_ifc |
|
| arbel_cmd_mad_ifc |
|
| arbel_cmd_map_eq |
|
| arbel_cmd_map_eq |
|
| arbel_cmd_map_fa |
|
| arbel_cmd_map_fa |
|
| arbel_cmd_map_icm |
|
| arbel_cmd_map_icm |
|
| arbel_cmd_map_icm_aux |
|
| arbel_cmd_map_icm_aux |
|
| arbel_cmd_mgid_hash |
|
| arbel_cmd_mgid_hash |
|
| arbel_cmd_query_dev_lim |
|
| arbel_cmd_query_dev_lim |
|
| arbel_cmd_query_fw |
|
| arbel_cmd_query_fw |
|
| arbel_cmd_read_mgm |
|
| arbel_cmd_read_mgm |
|
| arbel_cmd_rst2init_qpee |
|
| arbel_cmd_rst2init_qpee |
|
| arbel_cmd_rtr2rts_qpee |
|
| arbel_cmd_rtr2rts_qpee |
|
| arbel_cmd_rts2rts_qp |
|
| arbel_cmd_rts2rts_qp |
|
| arbel_cmd_run_fw |
|
| arbel_cmd_run_fw |
|
| arbel_cmd_set_icm_size |
|
| arbel_cmd_set_icm_size |
|
| arbel_cmd_sw2hw_cq |
|
| arbel_cmd_sw2hw_cq |
|
| arbel_cmd_sw2hw_eq |
|
| arbel_cmd_sw2hw_eq |
|
| arbel_cmd_sw2hw_mpt |
|
| arbel_cmd_sw2hw_mpt |
|
|
A