索引 - Excel2010

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A_ALTCHARSET
A_ATTRIBUTES
A_BLINK
A_BOLD
A_CHARTEXT
A_CNF_10B_2
A_CNF_10B_2
A_CNF_10B_T
A_CNF_10B_T
A_CNF_AUI
A_CNF_AUI
A_CNF_DC_DC_POLARITY
A_CNF_DC_DC_POLARITY
A_CNF_EXTND_10B_2
A_CNF_EXTND_10B_2
A_CNF_LOW_RX_SQUELCH
A_CNF_LOW_RX_SQUELCH
A_CNF_MEDIA_10B_2
A_CNF_MEDIA_10B_2
A_CNF_MEDIA_10B_T
A_CNF_MEDIA_10B_T
A_CNF_MEDIA_AUI
A_CNF_MEDIA_AUI
A_CNF_MEDIA_AUTO
A_CNF_MEDIA_AUTO
A_CNF_MEDIA_TYPE
A_CNF_MEDIA_TYPE
A_CNF_NO_AUTO_POLARITY
A_CNF_NO_AUTO_POLARITY
A_COLOR
A_COLOUR
A_DEFAULT
A_DIM
A_INVIS
A_N_ENABLE
A_N_ENABLE
A_PROTECT
A_REVERSE
A_STANDOUT
A_UNDERLINE
A20_INT15_RETRIES
A20_KBC_RETRIES
A20_MAX_RETRIES
a20_methods
A20_SCPA_RETRIES
a3c90x_close	a3c90x_close - free()s TX and RX ring, disablex RX/TX, resets NIC
a3c90x_close	a3c90x_close - free()s TX and RX ring, disablex RX/TX, resets NIC
a3c90x_free_resources
a3c90x_free_resources
a3c90x_free_rx_iobuf
a3c90x_free_rx_iobuf
a3c90x_free_rx_ring
a3c90x_free_rx_ring
a3c90x_free_tx_ring
a3c90x_free_tx_ring
a3c90x_hw_start	a3c90x_hw_start - Initialize hardware, copy MAC address
a3c90x_hw_start	a3c90x_hw_start - Initialize hardware, copy MAC address
a3c90x_internal_IssueCommand
a3c90x_internal_IssueCommand
a3c90x_internal_ReadEeprom	a3c90x_internal_ReadEeprom - nvs routine to read eeprom data
a3c90x_internal_ReadEeprom	a3c90x_internal_ReadEeprom - nvs routine to read eeprom data
a3c90x_internal_ReadEepromContents
a3c90x_internal_ReadEepromContents
a3c90x_internal_SetWindow
a3c90x_internal_SetWindow
a3c90x_internal_WaitForEeprom
a3c90x_internal_WaitForEeprom
a3c90x_internal_WriteEeprom	a3c90x_internal_WriteEeprom - nvs routine to write eeprom data
a3c90x_internal_WriteEeprom	a3c90x_internal_WriteEeprom - nvs routine to write eeprom data
a3c90x_irq
a3c90x_irq
a3c90x_open	a3c90x_open - Routine to initialize the card. Initialize hardware,
a3c90x_open	a3c90x_open - Routine to initialize the card. Initialize hardware,
a3c90x_poll	a3c90x_poll - Routine that gets called periodically.
a3c90x_poll	a3c90x_poll - Routine that gets called periodically.
a3c90x_prepare_rx_desc	a3c90x_prepare_rx_desc - fills the rx desc with initial data
a3c90x_prepare_rx_desc	a3c90x_prepare_rx_desc - fills the rx desc with initial data
a3c90x_probe
a3c90x_probe
a3c90x_process_rx_packets	a3c90x_process_rx_packets - Checks for received packets,
a3c90x_process_rx_packets	a3c90x_process_rx_packets - Checks for received packets,
a3c90x_process_tx_packets	a3c90x_process_tx_packets - Checks for successfully sent packets,
a3c90x_process_tx_packets	a3c90x_process_tx_packets - Checks for successfully sent packets,
a3c90x_refill_rx_ring	a3c90x_refill_rx_ring -checks every entry in the rx ring and reallocates
a3c90x_refill_rx_ring	a3c90x_refill_rx_ring -checks every entry in the rx ring and reallocates
a3c90x_remove	a3c90x_remove - Routine to remove the card. Unregisters
a3c90x_remove	a3c90x_remove - Routine to remove the card. Unregisters
a3c90x_reset
a3c90x_reset
a3c90x_setup_rx_ring	a3c90x_setup_rx_ring - Allocates RX ring, initialize rx_desc values
a3c90x_setup_rx_ring	a3c90x_setup_rx_ring - Allocates RX ring, initialize rx_desc values
a3c90x_setup_tx_ring	a3c90x_setup_tx_ring - Allocates TX ring, initialize tx_desc values
a3c90x_setup_tx_ring	a3c90x_setup_tx_ring - Allocates TX ring, initialize tx_desc values
a3c90x_transmit	a3c90x_transmit - Transmits a packet.
a3c90x_transmit	a3c90x_transmit - Transmits a packet.
AAC	Address ROM Address Counter (1->enable)
AAC	Address ROM Address Counter (1->enable)
abft.c
abft.h
abft_fill_data	Fill in all variable portions of aBFT
ABFT_SIG
abft_table
abftab
abort()
abort()
ACF_CONNECTOR_AUI
ACF_CONNECTOR_AUI
ACF_CONNECTOR_BITS
ACF_CONNECTOR_BITS
ACF_CONNECTOR_BNC
ACF_CONNECTOR_BNC
ACF_CONNECTOR_UTP
ACF_CONNECTOR_UTP
ACK
ACK_INTR
ACK_INTR
ACK_INTR
ACK_INTR
ACON	ALE control
ACON	ALE control
acpi.c
acpi.c
acpi.h
ACPI_ADR_DEVICE_PATH
ACPI_ADR_DISPLAY_TYPE_EXTERNAL_
ACPI_ADR_DISPLAY_TYPE_INTERNAL_
ACPI_ADR_DISPLAY_TYPE_OTHER
ACPI_ADR_DISPLAY_TYPE_TV
ACPI_ADR_DISPLAY_TYPE_VGA
ACPI_ADR_DP
acpi_description_header
ACPI_DEVICE_PATH
ACPI_DISPLAY_ADR(_DeviceIdScheme, _HeadId, _NonVgaOutput, _BiosCanDetect, _VendorInfo, _Type, _Port, _Index)
ACPI_DP
ACPI_EXTENDED_DP
ACPI_EXTENDED_HID_DEVICE_PATH
acpi_fix_checksum	@file
acpi_fix_checksum	@file
ACPI_HID_DEVICE_PATH
ACPI_LENOFF_LEN_MASK
ACPI_LENOFF_LEN_MASK
ACPI_LENOFF_LEN_SHIFT
ACPI_LENOFF_LEN_SHIFT
ACPI_LENOFF_OFF_MASK
ACPI_LENOFF_OFF_MASK
ACPI_LENOFF_OFF_SHIFT
ACPI_LENOFF_OFF_SHIFT
ACS_BLOCK
ACS_BOARD
ACS_BTEE
ACS_BULLET
ACS_CKBOARD
ACS_DARROW
ACS_DEGREE
ACS_DIAMOND
ACS_HLINE
ACS_LANTERN
ACS_LARROW
ACS_LLCORNER
ACS_LRCORNER
ACS_LTEE
ACS_PLMINUS
ACS_PLUS
ACS_RARROW
ACS_RTEE
ACS_S1
ACS_S9
ACS_TTEE
ACS_UARROW
ACS_ULCORNER
ACS_URCORNER
ACS_VLINE
ActionCommands
ACTIVATE_ADAPTER_TO_CONFIG
ACTIVATE_ADAPTER_TO_CONFIG
activate_t509_device
activate_t509_device
ACTIVE_33V
ACTIVE_33V
adapter
adapter
ADAPTER_CNF_OFFSET
ADAPTER_CNF_OFFSET
add_ipv4_miniroute	Add IPv4 minirouting table entry
add_ipv6_address	Add IPv6 interface
add_ipv6_miniroute	Add IPv6 minirouting table entry
ADD_MASK	Mask it use of the ADD_PORT register
ADD_MASK	Mask it use of the ADD_PORT register
add_ndp_entry	Add NDP entry
ADD_PORT
ADD_PORT
ADD_SIG	Expected ID signature
ADD_SIG	Expected ID signature
add_socket_i365
add_socket_i365
add_tls	Instantiator
ADDR0
ADDR0
ADDR1
ADDR1
ADDR2
ADDR2
adjust_pci_device	Enable PCI device
adjust_pci_device	Enable PCI device
ADVERTISE_10_FULL
ADVERTISE_10_FULL
ADVERTISE_10_HALF
ADVERTISE_10_HALF
ADVERTISE_100_FULL
ADVERTISE_100_FULL
ADVERTISE_100_HALF
ADVERTISE_100_HALF
ADVERTISE_1000_FULL
ADVERTISE_1000_FULL
ADVERTISE_1000_HALF
ADVERTISE_1000_HALF
ADVERTISE_1000FULL	Advertise 1000BASE-T full duplex
ADVERTISE_1000HALF	Advertise 1000BASE-T half duplex
ADVERTISE_1000XFULL	Try for 1000BASE-X full-duplex
ADVERTISE_1000XHALF	Try for 1000BASE-X half-duplex
ADVERTISE_1000XPAUSE	Try for 1000BASE-X pause
ADVERTISE_1000XPSE_ASYM	Try for 1000BASE-X asym pause
ADVERTISE_100BASE4	Try for 100mbps 4k packets
ADVERTISE_100FULL	Try for 100mbps full-duplex
ADVERTISE_100HALF	Try for 100mbps half-duplex
ADVERTISE_10FULL	Try for 10mbps full-duplex
ADVERTISE_10HALF	Try for 10mbps half-duplex
ADVERTISE_ALL
ADVERTISE_CSMA	Only selector supported
ADVERTISE_FULL
ADVERTISE_LPACK	Ack link partners response
ADVERTISE_NPAGE	Next page bit
ADVERTISE_PAUSE_ASYM	Try for asymetric pause
ADVERTISE_PAUSE_CAP	Try for pause
ADVERTISE_RESV	Unused...
ADVERTISE_RFAULT	Say we can detect faults
ADVERTISE_SLCT	Selector bits
ADVERTISED_1000baseT_Full
ADVERTISED_1000baseT_Full
ADVERTISED_1000baseT_Full
ADVERTISED_1000baseT_Full
ADVERTISED_1000baseT_Full
ADVERTISED_1000baseT_Full
ADVERTISED_1000baseT_Full
ADVERTISED_1000baseT_Half
ADVERTISED_1000baseT_Half
ADVERTISED_1000baseT_Half
ADVERTISED_1000baseT_Half
ADVERTISED_1000baseT_Half
ADVERTISED_1000baseT_Half
ADVERTISED_1000baseT_Half
ADVERTISED_100baseT_Full
ADVERTISED_100baseT_Full
ADVERTISED_100baseT_Full
ADVERTISED_100baseT_Full
ADVERTISED_100baseT_Full
ADVERTISED_100baseT_Full
ADVERTISED_100baseT_Full
ADVERTISED_100baseT_Half
ADVERTISED_100baseT_Half
ADVERTISED_100baseT_Half
ADVERTISED_100baseT_Half
ADVERTISED_100baseT_Half
ADVERTISED_100baseT_Half
ADVERTISED_100baseT_Half
ADVERTISED_10baseT_Full
ADVERTISED_10baseT_Full
ADVERTISED_10baseT_Full
ADVERTISED_10baseT_Full
ADVERTISED_10baseT_Full
ADVERTISED_10baseT_Full
ADVERTISED_10baseT_Full
ADVERTISED_10baseT_Half
ADVERTISED_10baseT_Half
ADVERTISED_10baseT_Half
ADVERTISED_10baseT_Half
ADVERTISED_10baseT_Half
ADVERTISED_10baseT_Half
ADVERTISED_10baseT_Half
ADVERTISED_AUI
ADVERTISED_AUI
ADVERTISED_AUI
ADVERTISED_AUI
ADVERTISED_Autoneg
ADVERTISED_Autoneg
ADVERTISED_Autoneg
ADVERTISED_Autoneg
ADVERTISED_BNC
ADVERTISED_BNC
ADVERTISED_BNC
ADVERTISED_BNC
ADVERTISED_FIBRE
ADVERTISED_FIBRE
ADVERTISED_FIBRE
ADVERTISED_FIBRE
ADVERTISED_MII
ADVERTISED_MII
ADVERTISED_MII
ADVERTISED_MII
ADVERTISED_TP
ADVERTISED_TP
ADVERTISED_TP
ADVERTISED_TP
aes.c
aes.c
aes.h
AES_BLOCKSIZE
aes_call_axtls	Call AXTLS' AES_encrypt() or AES_decrypt() functions
aes_call_axtls	Call AXTLS' AES_encrypt() or AES_decrypt() functions
AES_cbc_decrypt	Decrypt a byte sequence (with a block size 16) using the AES cipher.
AES_cbc_decrypt	Decrypt a byte sequence (with a block size 16) using the AES cipher.
AES_cbc_encrypt	Encrypt a byte sequence (with a block size 16) using the AES cipher.
AES_cbc_encrypt	Encrypt a byte sequence (with a block size 16) using the AES cipher.
aes_context
AES_convert_key	Change a key for decryption.
AES_convert_key	Change a key for decryption.
aes_decrypt	Decrypt data
aes_decrypt	Decrypt data
AES_decrypt	Decrypt a single block (16 bytes) of data
AES_decrypt	Decrypt a single block (16 bytes) of data
aes_encrypt	Encrypt data
aes_encrypt	Encrypt data
AES_encrypt	Encrypt a single block (16 bytes) of data
AES_encrypt	Encrypt a single block (16 bytes) of data
AES_set_key	Set up AES with the key/iv and cipher size.
AES_set_key	Set up AES with the key/iv and cipher size.
aes_setiv	Set initialisation vector
aes_setiv	Set initialisation vector
aes_setkey	Set key
aes_setkey	@file
aes_unwrap	Unwrap a key or other data using AES Key Wrap (RFC 3394)
aes_wrap	Wrap a key or other data using AES Key Wrap (RFC 3394)
aes_wrap.c
AES_xtime
AES_xtime
AF
AF_INET	*< IPv4 Internet addresses
AF_INET6	*< IPv6 Internet addresses
AGGREGATE_WAIT_TIME
AGGREGATE_WAIT_TIME
AhdocPHYID0
AhdocPHYID0
alaska_init	Alaska PHY
alaska_init	Alaska PHY
alert	Print alert message
alert.c
alert.c
ALERT_ROW
align
ALIGN	Keep the LANCE happy...
ALIGN	Keep the LANCE happy...
ALIGN_HIDDEN	4kB page alignment should be enough
ALIGN_POINTER(Pointer, Alignment)
ALIGN_VALUE(Value, Alignment)
ALIGN_VARIABLE(Value)
ALIGN4	1 longword align
ALIGN4	1 longword align
ALIGN8	2 longword (quadword) align
ALIGN8	2 longword (quadword) align
ALL_MASK
ALL_MASK
alloc
alloc
alloc_etherdev	Allocate Ethernet device
alloc_ibdev	Infiniband device creation/destruction
alloc_image	Allocate executable/loadable image
alloc_image	Allocate executable/loadable image
alloc_iob	@file
alloc_iob	@file
alloc_ipoibdev	Allocate IPoIB device
alloc_ipoibdev	Allocate IPoIB device
alloc_memblock	Allocate a memory block
alloc_memblock	Allocate a memory block
alloc_netdev	Allocate network device
alloc_output_file
alloc_rx
alloc_rx
alloca(size)
alloca.h
ALLOW_FDX
ALLOW_FDX
ALT_FORM
ALT_FORM
alta_offsets
alta_offsets
amd_mii_registers
amd_mii_registers
amd79c901_read_mode
amd79c901_read_mode
amd8111e.c
amd8111e.c
amd8111e.h
amd8111e.h
amd8111e_disable
amd8111e_disable
amd8111e_disable_interrupt
amd8111e_disable_interrupt
amd8111e_enable_interrupt
amd8111e_enable_interrupt
amd8111e_force_interrupt
amd8111e_force_interrupt
amd8111e_get_mac_address
amd8111e_get_mac_address
amd8111e_init_hw_default
amd8111e_init_hw_default
amd8111e_init_rx_ring
amd8111e_init_rx_ring
amd8111e_init_tx_ring
amd8111e_init_tx_ring
amd8111e_irq
amd8111e_irq
amd8111e_poll
amd8111e_poll
amd8111e_poll_link
amd8111e_poll_link
amd8111e_priv
amd8111e_priv
amd8111e_probe
amd8111e_probe
amd8111e_probe_ext_phy
amd8111e_probe_ext_phy
amd8111e_read_phy
amd8111e_read_phy
AMD8111E_REG_DUMP_LEN
AMD8111E_REG_DUMP_LEN
amd8111e_restart
amd8111e_restart
amd8111e_rx_desc
amd8111e_rx_desc
amd8111e_start
amd8111e_start
amd8111e_transmit	Interface Functions *
amd8111e_transmit	Interface Functions *
amd8111e_tx_desc
amd8111e_tx_desc
amd8111e_wait_link
amd8111e_wait_link
amd8111e_wait_tx_ring
amd8111e_wait_tx_ring
amd8111e_write_phy
amd8111e_write_phy
amd8111e_writeq(_UlData,_memMap)
amd8111e_writeq(_UlData,_memMap)
ANAPARAM_PWR0_MASK
ANAPARAM_PWR0_MASK
ANAPARAM_PWR0_SHIFT
ANAPARAM_PWR0_SHIFT
ANAPARAM_PWR1_MASK
ANAPARAM_PWR1_MASK
ANAPARAM_PWR1_SHIFT
ANAPARAM_PWR1_SHIFT
ANAPARAM_TXDACOFF_SHIFT
ANAPARAM_TXDACOFF_SHIFT
ANAR_10
ANAR_10
ANAR_10FD
ANAR_10FD
ANAR_ASMDIR	Asymmetric PAUSE support
ANAR_ASMDIR	Asymmetric PAUSE support
ANAR_PAUSE	Symmetric PAUSE Support
ANAR_PAUSE	Symmetric PAUSE Support
ANAR_T4
ANAR_T4
ANAR_TX
ANAR_TX
ANAR_TXFD
ANAR_TXFD
ANEG_DONE
ANEG_DONE
ANEG_FAILED
ANEG_FAILED
ANEG_OK
ANEG_OK
ANEG_STATE_SETTLE_TIME
ANEG_STATE_SETTLE_TIME
ANEG_TIMER_ENAB
ANEG_TIMER_ENAB
ANLPAR_10
ANLPAR_10
ANLPAR_10FD
ANLPAR_10FD
ANLPAR_ASMDIR	Asymmetric PAUSE support
ANLPAR_ASMDIR	Asymmetric PAUSE support
ANLPAR_PAUSE	Symmetric PAUSE Support
ANLPAR_PAUSE	Symmetric PAUSE Support
ANLPAR_T4
ANLPAR_T4
ANLPAR_TX
ANLPAR_TX
ANLPAR_TXFD
ANLPAR_TXFD
ansi_screen.c
ansiesc.c
ansiesc.c
ansiesc.h
ansiesc_call_handler	@file
ansiesc_call_handler	@file
ansiesc_context
ANSIESC_CUP
ANSIESC_ED
ANSIESC_ED_ALL
ANSIESC_ED_FROM_START
ANSIESC_ED_TO_END
ansiesc_handler
ANSIESC_MAX_PARAMS
ansiesc_process	Process character that may be part of ANSI escape sequence
ansiesc_process	Process character that may be part of ANSI escape sequence
ANSIESC_SGR
ansiscr_getc
ansiscr_movetoyx
ansiscr_peek
ansiscr_putc
ansiscr_reset
ANY_ISA_DMA
ANY_ISA_DMA
aoe.c
aoe.h
aoe_attach
AOE_CMD_ATA	*< Issue ATA command
AOE_CMD_CONFIG	*< Query Config Information
aoe_command	Issue ATA command via an open AoE session
aoe_detach
aoe_detached_command
aoe_discover	Issue AoE config query for AoE target discovery
aoe_done	Mark current AoE command complete
AOE_ERR_BAD_COMMAND	*< Unrecognised command code
AOE_ERR_BAD_PARAMETER	*< Bad argument parameter
AOE_ERR_BAD_VERSION	*< Unsupported version
AOE_ERR_CONFIG_EXISTS	*< Config string present
AOE_ERR_UNAVAILABLE	*< Device unavailable
AOE_FL_ASYNC	*< Asynchronous write
AOE_FL_DEV_HEAD	*< Device/head flag
AOE_FL_ERROR	*< Command generated an error
AOE_FL_EXTENDED	*< LBA48 extended addressing
AOE_FL_RESPONSE	*< Message is a response
AOE_FL_WRITE	*< Write command
aoe_free
AOE_MAJOR_BROADCAST
AOE_MAX_COUNT
AOE_MINOR_BROADCAST
aoe_parse_root_path
aoe_rx	Process incoming AoE packets
aoe_rx_ata	Handle AoE ATA command response
aoe_rx_cfg	Handle AoE configuration command response
aoe_send_command	Send AoE command
aoe_session
AOE_STATUS_ERR_MASK	*< Error portion of status code
AOE_STATUS_PENDING	*< Command pending
AOE_TAG_MAGIC
aoe_timer_expired	Handle AoE retry timer expiry
AOE_VERSION	*< Version 1
AOE_VERSION_MASK	*< Version part of ver_flags field
aoeata
aoeboot
aoeboot.c
aoecfg
aoecmd
aoehdr
aout_download
aout_freebsd_boot
aout_freebsd_probe
aout_loader.c
aout_probe
aout_state
AP_VALUE	Auto-poll value register
AP_VALUE	Auto-poll value register
AP_VALUE_BITS
AP_VALUE_BITS
api.h
apply_dns_settings	Apply DNS settings
apply_iscsi_settings	Apply iSCSI settings
apply_iscsi_string_setting	Apply iSCSI setting
apply_settings	Apply all settings
apply_settings	Apply all settings
AR5K_2W_TX_DESC_CTL0_ANT_MODE_X
AR5K_2W_TX_DESC_CTL0_ANT_MODE_X
AR5K_2W_TX_DESC_CTL0_ANT_MODE_X
AR5K_2W_TX_DESC_CTL0_ANT_MODE_X
AR5K_2W_TX_DESC_CTL0_ANT_MODE_X
AR5K_2W_TX_DESC_CTL0_ANT_MODE_X
AR5K_2W_TX_DESC_CTL0_ANT_MODE_X
AR5K_2W_TX_DESC_CTL0_ANT_MODE_X
AR5K_2W_TX_DESC_CTL0_CLRDMASK
AR5K_2W_TX_DESC_CTL0_CLRDMASK
AR5K_2W_TX_DESC_CTL0_ENCRYPT_KE
AR5K_2W_TX_DESC_CTL0_ENCRYPT_KE
AR5K_2W_TX_DESC_CTL0_FRAME_LEN
AR5K_2W_TX_DESC_CTL0_FRAME_LEN
AR5K_2W_TX_DESC_CTL0_FRAME_TYPE	[5210]
AR5K_2W_TX_DESC_CTL0_FRAME_TYPE
AR5K_2W_TX_DESC_CTL0_FRAME_TYPE	[5210]
AR5K_2W_TX_DESC_CTL0_FRAME_TYPE
AR5K_2W_TX_DESC_CTL0_HEADER_LEN	[5210 ?]
AR5K_2W_TX_DESC_CTL0_HEADER_LEN
AR5K_2W_TX_DESC_CTL0_HEADER_LEN	[5210 ?]
AR5K_2W_TX_DESC_CTL0_HEADER_LEN
AR5K_2W_TX_DESC_CTL0_INTREQ
AR5K_2W_TX_DESC_CTL0_INTREQ
AR5K_2W_TX_DESC_CTL0_LONG_PACKE	[5210]
AR5K_2W_TX_DESC_CTL0_LONG_PACKE	[5210]
AR5K_2W_TX_DESC_CTL0_RTSENA
AR5K_2W_TX_DESC_CTL0_RTSENA
AR5K_2W_TX_DESC_CTL0_VEOL	[5211]
AR5K_2W_TX_DESC_CTL0_VEOL	[5211]
AR5K_2W_TX_DESC_CTL0_XMIT_RATE
AR5K_2W_TX_DESC_CTL0_XMIT_RATE
AR5K_2W_TX_DESC_CTL0_XMIT_RATE_
AR5K_2W_TX_DESC_CTL0_XMIT_RATE_
AR5K_2W_TX_DESC_CTL1_BUF_LEN
AR5K_2W_TX_DESC_CTL1_BUF_LEN
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KE
AR5K_2W_TX_DESC_CTL1_FRAME_TYPE	[5211]
AR5K_2W_TX_DESC_CTL1_FRAME_TYPE
AR5K_2W_TX_DESC_CTL1_FRAME_TYPE	[5211]
AR5K_2W_TX_DESC_CTL1_FRAME_TYPE
AR5K_2W_TX_DESC_CTL1_MORE
AR5K_2W_TX_DESC_CTL1_MORE
AR5K_2W_TX_DESC_CTL1_NOACK	[5211]
AR5K_2W_TX_DESC_CTL1_NOACK	[5211]
AR5K_2W_TX_DESC_CTL1_RTS_DURATI	[5210 ?]
AR5K_2W_TX_DESC_CTL1_RTS_DURATI	[5210 ?]
AR5K_5210_RX_DESC_STATUS0_DATA_
AR5K_5210_RX_DESC_STATUS0_DATA_
AR5K_5210_RX_DESC_STATUS0_MORE
AR5K_5210_RX_DESC_STATUS0_MORE
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS0_RECEI
AR5K_5210_RX_DESC_STATUS1_CRC_E
AR5K_5210_RX_DESC_STATUS1_CRC_E
AR5K_5210_RX_DESC_STATUS1_DECRY
AR5K_5210_RX_DESC_STATUS1_DECRY
AR5K_5210_RX_DESC_STATUS1_DONE
AR5K_5210_RX_DESC_STATUS1_DONE
AR5K_5210_RX_DESC_STATUS1_FIFO_
AR5K_5210_RX_DESC_STATUS1_FIFO_
AR5K_5210_RX_DESC_STATUS1_FRAME
AR5K_5210_RX_DESC_STATUS1_FRAME
AR5K_5210_RX_DESC_STATUS1_KEY_C
AR5K_5210_RX_DESC_STATUS1_KEY_C
AR5K_5210_RX_DESC_STATUS1_KEY_I
AR5K_5210_RX_DESC_STATUS1_KEY_I
AR5K_5210_RX_DESC_STATUS1_KEY_I
AR5K_5210_RX_DESC_STATUS1_KEY_I
AR5K_5210_RX_DESC_STATUS1_KEY_I
AR5K_5210_RX_DESC_STATUS1_KEY_I
AR5K_5210_RX_DESC_STATUS1_PHY_E
AR5K_5210_RX_DESC_STATUS1_PHY_E
AR5K_5210_RX_DESC_STATUS1_PHY_E
AR5K_5210_RX_DESC_STATUS1_PHY_E
AR5K_5210_RX_DESC_STATUS1_RECEI
AR5K_5210_RX_DESC_STATUS1_RECEI
AR5K_5210_RX_DESC_STATUS1_RECEI
AR5K_5210_RX_DESC_STATUS1_RECEI
AR5K_5212_RX_DESC_STATUS0_DATA_
AR5K_5212_RX_DESC_STATUS0_DATA_
AR5K_5212_RX_DESC_STATUS0_DECOM
AR5K_5212_RX_DESC_STATUS0_DECOM
AR5K_5212_RX_DESC_STATUS0_MORE
AR5K_5212_RX_DESC_STATUS0_MORE
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS0_RECEI
AR5K_5212_RX_DESC_STATUS1_CRC_E
AR5K_5212_RX_DESC_STATUS1_CRC_E
AR5K_5212_RX_DESC_STATUS1_DECRY
AR5K_5212_RX_DESC_STATUS1_DECRY
AR5K_5212_RX_DESC_STATUS1_DONE
AR5K_5212_RX_DESC_STATUS1_DONE
AR5K_5212_RX_DESC_STATUS1_FRAME
AR5K_5212_RX_DESC_STATUS1_FRAME
AR5K_5212_RX_DESC_STATUS1_KEY_C
AR5K_5212_RX_DESC_STATUS1_KEY_C
AR5K_5212_RX_DESC_STATUS1_KEY_I
AR5K_5212_RX_DESC_STATUS1_KEY_I
AR5K_5212_RX_DESC_STATUS1_KEY_I
AR5K_5212_RX_DESC_STATUS1_KEY_I
AR5K_5212_RX_DESC_STATUS1_KEY_I
AR5K_5212_RX_DESC_STATUS1_KEY_I
AR5K_5212_RX_DESC_STATUS1_MIC_E
AR5K_5212_RX_DESC_STATUS1_MIC_E
AR5K_5212_RX_DESC_STATUS1_PHY_E
AR5K_5212_RX_DESC_STATUS1_PHY_E
AR5K_5212_RX_DESC_STATUS1_RECEI
AR5K_5212_RX_DESC_STATUS1_RECEI
AR5K_5212_RX_DESC_STATUS1_RECEI
AR5K_5212_RX_DESC_STATUS1_RECEI
AR5K_5414_CBCFG
AR5K_5414_CBCFG
AR5K_5414_CBCFG_BUF_DIS	Disable buffer
AR5K_5414_CBCFG_BUF_DIS	Disable buffer
AR5K_ACK_FAIL
AR5K_ACK_FAIL
AR5K_ACK_FAIL_5210
AR5K_ACK_FAIL_5210
AR5K_ACK_FAIL_5211
AR5K_ACK_FAIL_5211
AR5K_ACKSIFS	Register Address
AR5K_ACKSIFS	Register Address
AR5K_ACKSIFS_INC	ACK SIFS Increment (field)
AR5K_ACKSIFS_INC	ACK SIFS Increment (field)
AR5K_ADDAC_TEST	Register Address
AR5K_ADDAC_TEST	Register Address
AR5K_ADDAC_TEST_CAPTURE	Begin capture
AR5K_ADDAC_TEST_CAPTURE	Begin capture
AR5K_ADDAC_TEST_LOOP_EN	Enable loop
AR5K_ADDAC_TEST_LOOP_EN	Enable loop
AR5K_ADDAC_TEST_LOOP_LEN	Loop length (field)
AR5K_ADDAC_TEST_LOOP_LEN	Loop length (field)
AR5K_ADDAC_TEST_MSB	State of MSB
AR5K_ADDAC_TEST_MSB	State of MSB
AR5K_ADDAC_TEST_RXCONT	Continuous capture
AR5K_ADDAC_TEST_RXCONT	Continuous capture
AR5K_ADDAC_TEST_TRIG_PTY	Trigger polarity
AR5K_ADDAC_TEST_TRIG_PTY	Trigger polarity
AR5K_ADDAC_TEST_TRIG_SEL	Trigger select
AR5K_ADDAC_TEST_TRIG_SEL	Trigger select
AR5K_ADDAC_TEST_TST_ARM	ARM rx buffer for capture
AR5K_ADDAC_TEST_TST_ARM	ARM rx buffer for capture
AR5K_ADDAC_TEST_TST_MODE	Test mode
AR5K_ADDAC_TEST_TST_MODE	Test mode
AR5K_ADDAC_TEST_TXCONT	Test continuous tx
AR5K_ADDAC_TEST_TXCONT	Test continuous tx
AR5K_ADDAC_TEST_USE_U8	Use upper 8 bits
AR5K_ADDAC_TEST_USE_U8	Use upper 8 bits
AR5K_AR5210_TX_DESC_FRAME_TYPE_
AR5K_AR5210_TX_DESC_FRAME_TYPE_
AR5K_AR5210_TX_DESC_FRAME_TYPE_
AR5K_AR5210_TX_DESC_FRAME_TYPE_
AR5K_AR5210_TX_DESC_FRAME_TYPE_
AR5K_AR5210_TX_DESC_FRAME_TYPE_
AR5K_AR5210_TX_DESC_FRAME_TYPE_
AR5K_AR5210_TX_DESC_FRAME_TYPE_
AR5K_AR5210_TX_DESC_FRAME_TYPE_
AR5K_AR5210_TX_DESC_FRAME_TYPE_
AR5K_ASSERT_ENTRY(_e, _s)
AR5K_ASSERT_ENTRY(_e, _s)
AR5K_BACKOFF	Register Address [5210]
AR5K_BACKOFF	Register Address [5210]
AR5K_BACKOFF_CNT	Backoff count (?)
AR5K_BACKOFF_CNT	Backoff count (?)
AR5K_BACKOFF_CW	Backoff Contention Window (?)
AR5K_BACKOFF_CW	Backoff Contention Window (?)
AR5K_BB_GAIN(_n)
AR5K_BB_GAIN(_n)
AR5K_BB_GAIN_BASE	BaseBand Amplifier Gain table base address
AR5K_BB_GAIN_BASE	BaseBand Amplifier Gain table base address
AR5K_BCR	Register Address
AR5K_BCR	Register Address
AR5K_BCR_ADHOC	Ad-Hoc mode
AR5K_BCR_ADHOC	Ad-Hoc mode
AR5K_BCR_AP	AP mode
AR5K_BCR_AP	AP mode
AR5K_BCR_BCGET
AR5K_BCR_BCGET
AR5K_BCR_BDMAE	DMA enable
AR5K_BCR_BDMAE	DMA enable
AR5K_BCR_TQ1FV	Use Queue1 for CAB traffic
AR5K_BCR_TQ1FV	Use Queue1 for CAB traffic
AR5K_BCR_TQ1V	Use Queue1 for Beacon traffic
AR5K_BCR_TQ1V	Use Queue1 for Beacon traffic
AR5K_BEACON
AR5K_BEACON
AR5K_BEACON_5210	Register Address [5210]
AR5K_BEACON_5210	Register Address [5210]
AR5K_BEACON_5211	Register Address [5211+]
AR5K_BEACON_5211	Register Address [5211+]
AR5K_BEACON_CNT
AR5K_BEACON_CNT
AR5K_BEACON_CNT_5210
AR5K_BEACON_CNT_5210
AR5K_BEACON_CNT_5211
AR5K_BEACON_CNT_5211
AR5K_BEACON_ENABLE	Enable beacons
AR5K_BEACON_ENABLE	Enable beacons
AR5K_BEACON_PERIOD	Mask for beacon period
AR5K_BEACON_PERIOD	Mask for beacon period
AR5K_BEACON_PERIOD_S
AR5K_BEACON_PERIOD_S
AR5K_BEACON_RESET_TSF	Force TSF reset
AR5K_BEACON_RESET_TSF	Force TSF reset
AR5K_BEACON_TIM	Mask for TIM offset
AR5K_BEACON_TIM	Mask for TIM offset
AR5K_BEACON_TIM_S
AR5K_BEACON_TIM_S
AR5K_BSR	Register Address
AR5K_BSR	Register Address
AR5K_BSR_ATIMDLY	ATIM delay (?)
AR5K_BSR_ATIMDLY	ATIM delay (?)
AR5K_BSR_BDLYDMA	DMA Beacon delay (?)
AR5K_BSR_BDLYDMA	DMA Beacon delay (?)
AR5K_BSR_BDLYSW	SW Beacon delay (?)
AR5K_BSR_BDLYSW	SW Beacon delay (?)
AR5K_BSR_SNAPSHOTSVALID	BCR snapshots are valid (?)
AR5K_BSR_SNAPSHOTSVALID	BCR snapshots are valid (?)
AR5K_BSR_SNPADHOC	Ad-hoc mode set (?)
AR5K_BSR_SNPADHOC	Ad-hoc mode set (?)
AR5K_BSR_SNPBDMAE	Beacon DMA enabled (?)
AR5K_BSR_SNPBDMAE	Beacon DMA enabled (?)
AR5K_BSR_SNPTQ1FV	Queue1 is used for CAB traffic (?)
AR5K_BSR_SNPTQ1FV	Queue1 is used for CAB traffic (?)
AR5K_BSR_SNPTQ1V	Queue1 is used for Beacon traffic (?)
AR5K_BSR_SNPTQ1V	Queue1 is used for Beacon traffic (?)
AR5K_BSR_SWBA_CNT
AR5K_BSR_SWBA_CNT
AR5K_BSR_TXQ1F	Beacon queue (1) finished
AR5K_BSR_TXQ1F	Beacon queue (1) finished
AR5K_BSS_ID0
AR5K_BSS_ID0
AR5K_BSS_ID1
AR5K_BSS_ID1
AR5K_BSS_ID1_AID
AR5K_BSS_ID1_AID
AR5K_BSS_ID1_AID_S
AR5K_BSS_ID1_AID_S
AR5K_BSS_IDM0	Upper bits
AR5K_BSS_IDM0	Upper bits
AR5K_BSS_IDM1	Lower bits
AR5K_BSS_IDM1	Lower bits
AR5K_CCFG	Register Address
AR5K_CCFG	Register Address
AR5K_CCFG_CCU	Register Address
AR5K_CCFG_CCU	Register Address
AR5K_CCFG_CCU_CD_THRES	CCU Cyc(lic?) debt threshold (field)
AR5K_CCFG_CCU_CD_THRES	CCU Cyc(lic?) debt threshold (field)
AR5K_CCFG_CCU_CREDIT	CCU Credit (field)
AR5K_CCFG_CCU_CREDIT	CCU Credit (field)
AR5K_CCFG_CCU_CUP_EN	CCU Catchup enable
AR5K_CCFG_CCU_CUP_EN	CCU Catchup enable
AR5K_CCFG_CCU_CUP_LCNT	CCU Catchup lit(?) count
AR5K_CCFG_CCU_CUP_LCNT	CCU Catchup lit(?) count
AR5K_CCFG_CCU_INIT	Initial value during reset
AR5K_CCFG_CCU_INIT	Initial value during reset
AR5K_CCFG_CPC_EN	Enable performance counters
AR5K_CCFG_CPC_EN	Enable performance counters
AR5K_CCFG_WINDOW_SIZE	Compression window size
AR5K_CCFG_WINDOW_SIZE	Compression window size
AR5K_CCK_FIL_CNT
AR5K_CCK_FIL_CNT
AR5K_CFG	Register Address
AR5K_CFG	Register Address
AR5K_CFG_CLKGD	Clock gated (Disable dynamic clock)
AR5K_CFG_CLKGD	Clock gated (Disable dynamic clock)
AR5K_CFG_EEBS	EEPROM is busy
AR5K_CFG_EEBS	EEPROM is busy
AR5K_CFG_IBSS	0-BSS, 1-IBSS [5211+]
AR5K_CFG_IBSS	0-BSS, 1-IBSS [5211+]
AR5K_CFG_PCI_THRES	PCI Master req q threshold [5211+]
AR5K_CFG_PCI_THRES	PCI Master req q threshold [5211+]
AR5K_CFG_PCI_THRES_S
AR5K_CFG_PCI_THRES_S
AR5K_CFG_PHY_OK	[5211+]
AR5K_CFG_PHY_OK	[5211+]
AR5K_CFG_SWRB	Byte-swap RX buffer
AR5K_CFG_SWRB	Byte-swap RX buffer
AR5K_CFG_SWRD	Byte-swap RX descriptor
AR5K_CFG_SWRD	Byte-swap RX descriptor
AR5K_CFG_SWRG	Byte-swap Register access
AR5K_CFG_SWRG	Byte-swap Register access
AR5K_CFG_SWTB	Byte-swap TX buffer
AR5K_CFG_SWTB	Byte-swap TX buffer
AR5K_CFG_SWTD	Byte-swap TX descriptor (for big endian archs)
AR5K_CFG_SWTD	Byte-swap TX descriptor (for big endian archs)
AR5K_CFG_TXCNT	Tx frame count (?) [5210]
AR5K_CFG_TXCNT	Tx frame count (?) [5210]
AR5K_CFG_TXCNT_S
AR5K_CFG_TXCNT_S
AR5K_CFG_TXFSTAT	Tx frame status (?) [5210]
AR5K_CFG_TXFSTAT	Tx frame status (?) [5210]
AR5K_CFG_TXFSTRT	[5210]
AR5K_CFG_TXFSTRT	[5210]
AR5K_CFP_DUR
AR5K_CFP_DUR
AR5K_CFP_DUR_5210
AR5K_CFP_DUR_5210
AR5K_CFP_DUR_5211
AR5K_CFP_DUR_5211
AR5K_CFP_PERIOD
AR5K_CFP_PERIOD
AR5K_CFP_PERIOD_5210
AR5K_CFP_PERIOD_5210
AR5K_CFP_PERIOD_5211
AR5K_CFP_PERIOD_5211
AR5K_CLR_TMASK
AR5K_CLR_TMASK
AR5K_CPC0	Compression performance counter 0
AR5K_CPC0	Compression performance counter 0
AR5K_CPC1	Compression performance counter 1
AR5K_CPC1	Compression performance counter 1
AR5K_CPC2	Compression performance counter 2
AR5K_CPC2	Compression performance counter 2
AR5K_CPC3	Compression performance counter 3
AR5K_CPC3	Compression performance counter 3
AR5K_CPCOVF	Compression performance overflow
AR5K_CPCOVF	Compression performance overflow
AR5K_CR	Register Address
AR5K_CR	Register Address
AR5K_CR_RXD	RX Disable
AR5K_CR_RXD	RX Disable
AR5K_CR_RXE	RX Enable
AR5K_CR_RXE	RX Enable
AR5K_CR_SWI	Software Interrupt
AR5K_CR_SWI	Software Interrupt
AR5K_CR_TXD0	TX Disable for queue 0 on 5210
AR5K_CR_TXD0	TX Disable for queue 0 on 5210
AR5K_CR_TXD1	TX Disable for queue 1 on 5210
AR5K_CR_TXD1	TX Disable for queue 1 on 5210
AR5K_CR_TXE0	TX Enable for queue 0 on 5210
AR5K_CR_TXE0	TX Enable for queue 0 on 5210
AR5K_CR_TXE1	TX Enable for queue 1 on 5210
AR5K_CR_TXE1	TX Enable for queue 1 on 5210
AR5K_CTL_CUSTOM
AR5K_CTL_CUSTOM
AR5K_CTL_ETSI
AR5K_CTL_ETSI
AR5K_CTL_FCC
AR5K_CTL_FCC
AR5K_CTL_MKK
AR5K_CTL_MKK
AR5K_CTL_NO_CTL
AR5K_CTL_NO_CTL
AR5K_CTL_NO_REGDOMAIN
AR5K_CTL_NO_REGDOMAIN
AR5K_DB2RATE(_n)
AR5K_DB2RATE(_n)
AR5K_DB2RATE_BASE
AR5K_DB2RATE_BASE
AR5K_DCCFG	Register Address
AR5K_DCCFG	Register Address
AR5K_DCCFG_BCAST_EN	Enable decompression for bcast frames
AR5K_DCCFG_BCAST_EN	Enable decompression for bcast frames
AR5K_DCCFG_BYPASS_EN	Bypass decompression
AR5K_DCCFG_BYPASS_EN	Bypass decompression
AR5K_DCCFG_GLOBAL_EN	Enable decompression on all queues
AR5K_DCCFG_GLOBAL_EN	Enable decompression on all queues
AR5K_DCCFG_MCAST_EN	Enable decompression for mcast frames
AR5K_DCCFG_MCAST_EN	Enable decompression for mcast frames
AR5K_DCM_ADDR	Decompression mask address (index)
AR5K_DCM_ADDR	Decompression mask address (index)
AR5K_DCM_DATA	Decompression mask data
AR5K_DCM_DATA	Decompression mask data
AR5K_DCU_CHAN_TIME_BASE	Register Address -Queue0 DCU_CHAN_TIME
AR5K_DCU_CHAN_TIME_BASE	Register Address -Queue0 DCU_CHAN_TIME
AR5K_DCU_CHAN_TIME_DUR	Channel time duration
AR5K_DCU_CHAN_TIME_DUR	Channel time duration
AR5K_DCU_CHAN_TIME_DUR_S
AR5K_DCU_CHAN_TIME_DUR_S
AR5K_DCU_CHAN_TIME_ENABLE	Enable channel time
AR5K_DCU_CHAN_TIME_ENABLE	Enable channel time
AR5K_DCU_FP	Register Address
AR5K_DCU_FP	Register Address
AR5K_DCU_FP_BURST_DCU_EN	Enable burst prefetch on DCU (?)
AR5K_DCU_FP_BURST_DCU_EN	Enable burst prefetch on DCU (?)
AR5K_DCU_FP_NOBURST_DCU_EN	Enable non-burst prefetch on DCU (?)
AR5K_DCU_FP_NOBURST_DCU_EN	Enable non-burst prefetch on DCU (?)
AR5K_DCU_FP_NOBURST_EN	Enable non-burst prefetch (?)
AR5K_DCU_FP_NOBURST_EN	Enable non-burst prefetch (?)
AR5K_DCU_GBL_IFS_EIFS
AR5K_DCU_GBL_IFS_EIFS
AR5K_DCU_GBL_IFS_EIFS_M
AR5K_DCU_GBL_IFS_EIFS_M
AR5K_DCU_GBL_IFS_MISC	Register Address
AR5K_DCU_GBL_IFS_MISC	Register Address
AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_	AIFS cnt reset policy (?)
AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_	AIFS cnt reset policy (?)
AR5K_DCU_GBL_IFS_MISC_DCU_ARB_D	DCU Arbiter delay mask
AR5K_DCU_GBL_IFS_MISC_DCU_ARB_D	DCU Arbiter delay mask
AR5K_DCU_GBL_IFS_MISC_LFSR_SLIC	LFSR Slice Select
AR5K_DCU_GBL_IFS_MISC_LFSR_SLIC	LFSR Slice Select
AR5K_DCU_GBL_IFS_MISC_RND_LFSR_	Disable random LFSR slice
AR5K_DCU_GBL_IFS_MISC_RND_LFSR_	Disable random LFSR slice
AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_	SIFS cnt reset policy (?)
AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_	SIFS cnt reset policy (?)
AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_	SIFS Duration mask
AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_	SIFS Duration mask
AR5K_DCU_GBL_IFS_MISC_TURBO_MOD	Turbo mode
AR5K_DCU_GBL_IFS_MISC_TURBO_MOD	Turbo mode
AR5K_DCU_GBL_IFS_MISC_USEC_DUR	USEC Duration mask
AR5K_DCU_GBL_IFS_MISC_USEC_DUR	USEC Duration mask
AR5K_DCU_GBL_IFS_MISC_USEC_DUR_
AR5K_DCU_GBL_IFS_MISC_USEC_DUR_
AR5K_DCU_GBL_IFS_SIFS
AR5K_DCU_GBL_IFS_SIFS
AR5K_DCU_GBL_IFS_SIFS_M
AR5K_DCU_GBL_IFS_SIFS_M
AR5K_DCU_GBL_IFS_SLOT
AR5K_DCU_GBL_IFS_SLOT
AR5K_DCU_GBL_IFS_SLOT_M
AR5K_DCU_GBL_IFS_SLOT_M
AR5K_DCU_LCL_IFS_AIFS	Arbitrated Interframe Space
AR5K_DCU_LCL_IFS_AIFS	Arbitrated Interframe Space
AR5K_DCU_LCL_IFS_AIFS_MAX	Anything above that can cause DCU to hang
AR5K_DCU_LCL_IFS_AIFS_MAX	Anything above that can cause DCU to hang
AR5K_DCU_LCL_IFS_AIFS_S
AR5K_DCU_LCL_IFS_AIFS_S
AR5K_DCU_LCL_IFS_BASE	Register Address -Queue0 DCU_LCL_IFS
AR5K_DCU_LCL_IFS_BASE	Register Address -Queue0 DCU_LCL_IFS
AR5K_DCU_LCL_IFS_CW_MAX	Maximum Contention Window
AR5K_DCU_LCL_IFS_CW_MAX	Maximum Contention Window
AR5K_DCU_LCL_IFS_CW_MAX_S
AR5K_DCU_LCL_IFS_CW_MAX_S
AR5K_DCU_LCL_IFS_CW_MIN	Minimum Contention Window
AR5K_DCU_LCL_IFS_CW_MIN	Minimum Contention Window
AR5K_DCU_LCL_IFS_CW_MIN_S
AR5K_DCU_LCL_IFS_CW_MIN_S
AR5K_DCU_MISC_ARBLOCK_CTL	Arbiter lockout control mask
AR5K_DCU_MISC_ARBLOCK_CTL	Arbiter lockout control mask
AR5K_DCU_MISC_ARBLOCK_CTL_GLOBA	Global lockout
AR5K_DCU_MISC_ARBLOCK_CTL_GLOBA	Global lockout
AR5K_DCU_MISC_ARBLOCK_CTL_INTFR	Intra-frame lockout
AR5K_DCU_MISC_ARBLOCK_CTL_INTFR	Intra-frame lockout
AR5K_DCU_MISC_ARBLOCK_CTL_NONE	No arbiter lockout
AR5K_DCU_MISC_ARBLOCK_CTL_NONE	No arbiter lockout
AR5K_DCU_MISC_ARBLOCK_CTL_S
AR5K_DCU_MISC_ARBLOCK_CTL_S
AR5K_DCU_MISC_ARBLOCK_IGNORE	Ignore Arbiter lockout
AR5K_DCU_MISC_ARBLOCK_IGNORE	Ignore Arbiter lockout
AR5K_DCU_MISC_BACKOFF	Mask for backoff threshold
AR5K_DCU_MISC_BACKOFF	Mask for backoff threshold
AR5K_DCU_MISC_BACKOFF_FRAG	Enable backoff while bursting
AR5K_DCU_MISC_BACKOFF_FRAG	Enable backoff while bursting
AR5K_DCU_MISC_BACKOFF_PERSIST	Persistent backoff
AR5K_DCU_MISC_BACKOFF_PERSIST	Persistent backoff
AR5K_DCU_MISC_BASE	Register Address -Queue0 DCU_MISC
AR5K_DCU_MISC_BASE	Register Address -Queue0 DCU_MISC
AR5K_DCU_MISC_BCN_ENABLE	Enable Beacon use
AR5K_DCU_MISC_BCN_ENABLE	Enable Beacon use
AR5K_DCU_MISC_BLOWN_IFS_POLICY	Blown IFS policy (?)
AR5K_DCU_MISC_BLOWN_IFS_POLICY	Blown IFS policy (?)
AR5K_DCU_MISC_ETS_CW_POL	End of transmission series
AR5K_DCU_MISC_ETS_CW_POL	End of transmission series
AR5K_DCU_MISC_ETS_RTS_POL	End of transmission series
AR5K_DCU_MISC_ETS_RTS_POL	End of transmission series
AR5K_DCU_MISC_FRAG_WAIT	Wait for next fragment
AR5K_DCU_MISC_FRAG_WAIT	Wait for next fragment
AR5K_DCU_MISC_FRMPRFTCH_ENABLE	Enable frame pre-fetch
AR5K_DCU_MISC_FRMPRFTCH_ENABLE	Enable frame pre-fetch
AR5K_DCU_MISC_HCFPOLL_ENABLE	CF - Poll enable
AR5K_DCU_MISC_HCFPOLL_ENABLE	CF - Poll enable
AR5K_DCU_MISC_POST_FR_BKOFF_DIS	Disable post-frame backoff
AR5K_DCU_MISC_POST_FR_BKOFF_DIS	Disable post-frame backoff
AR5K_DCU_MISC_SEQ_NUM_INCR_DIS	Disable sequence number increment
AR5K_DCU_MISC_SEQ_NUM_INCR_DIS	Disable sequence number increment
AR5K_DCU_MISC_SEQNUM_CTL	Sequence number control (?)
AR5K_DCU_MISC_SEQNUM_CTL	Sequence number control (?)
AR5K_DCU_MISC_VIRT_COLL_POLICY	Virtual Collision cw policy
AR5K_DCU_MISC_VIRT_COLL_POLICY	Virtual Collision cw policy
AR5K_DCU_MISC_VIRTCOL	Mask for Virtual Collision (?)
AR5K_DCU_MISC_VIRTCOL	Mask for Virtual Collision (?)
AR5K_DCU_MISC_VIRTCOL_IGNORE
AR5K_DCU_MISC_VIRTCOL_IGNORE
AR5K_DCU_MISC_VIRTCOL_NORMAL
AR5K_DCU_MISC_VIRTCOL_NORMAL
AR5K_DCU_QCUMASK_BASE	Register Address -Queue0 DCU_QCUMASK
AR5K_DCU_QCUMASK_BASE	Register Address -Queue0 DCU_QCUMASK
AR5K_DCU_QCUMASK_M
AR5K_DCU_QCUMASK_M
AR5K_DCU_RETRY_LMT_BASE	Register Address -Queue0 DCU_RETRY_LMT
AR5K_DCU_RETRY_LMT_BASE	Register Address -Queue0 DCU_RETRY_LMT
AR5K_DCU_RETRY_LMT_LG_RETRY	Long retry limit mask
AR5K_DCU_RETRY_LMT_LG_RETRY	Long retry limit mask
AR5K_DCU_RETRY_LMT_LG_RETRY_S
AR5K_DCU_RETRY_LMT_LG_RETRY_S
AR5K_DCU_RETRY_LMT_SH_RETRY	Short retry limit mask
AR5K_DCU_RETRY_LMT_SH_RETRY	Short retry limit mask
AR5K_DCU_RETRY_LMT_SH_RETRY_S
AR5K_DCU_RETRY_LMT_SH_RETRY_S
AR5K_DCU_RETRY_LMT_SLG_RETRY	Station long retry limit mask (?)
AR5K_DCU_RETRY_LMT_SLG_RETRY	Station long retry limit mask (?)
AR5K_DCU_RETRY_LMT_SLG_RETRY_S
AR5K_DCU_RETRY_LMT_SLG_RETRY_S
AR5K_DCU_RETRY_LMT_SSH_RETRY	Station short retry limit mask (?)
AR5K_DCU_RETRY_LMT_SSH_RETRY	Station short retry limit mask (?)
AR5K_DCU_RETRY_LMT_SSH_RETRY_S
AR5K_DCU_RETRY_LMT_SSH_RETRY_S
AR5K_DCU_SEQNUM_BASE
AR5K_DCU_SEQNUM_BASE
AR5K_DCU_SEQNUM_M
AR5K_DCU_SEQNUM_M
AR5K_DCU_TX_FILTER_0(_n)
AR5K_DCU_TX_FILTER_0(_n)
AR5K_DCU_TX_FILTER_0_BASE
AR5K_DCU_TX_FILTER_0_BASE
AR5K_DCU_TX_FILTER_1(_n)
AR5K_DCU_TX_FILTER_1(_n)
AR5K_DCU_TX_FILTER_1_BASE
AR5K_DCU_TX_FILTER_1_BASE
AR5K_DCU_TX_FILTER_CLR
AR5K_DCU_TX_FILTER_CLR
AR5K_DCU_TX_FILTER_SET
AR5K_DCU_TX_FILTER_SET
AR5K_DCU_TXP	Register Address
AR5K_DCU_TXP	Register Address
AR5K_DCU_TXP_M	Tx pause mask
AR5K_DCU_TXP_M	Tx pause mask
AR5K_DCU_TXP_STATUS	Tx pause status
AR5K_DCU_TXP_STATUS	Tx pause status
AR5K_DEFAULT_ANTENNA
AR5K_DEFAULT_ANTENNA
AR5K_DESC_RX_CTL0
AR5K_DESC_RX_CTL0
AR5K_DESC_RX_CTL1_BUF_LEN
AR5K_DESC_RX_CTL1_BUF_LEN
AR5K_DESC_RX_CTL1_INTREQ
AR5K_DESC_RX_CTL1_INTREQ
AR5K_DESC_RX_PHY_ERROR_64QAM
AR5K_DESC_RX_PHY_ERROR_64QAM
AR5K_DESC_RX_PHY_ERROR_LENGTH
AR5K_DESC_RX_PHY_ERROR_LENGTH
AR5K_DESC_RX_PHY_ERROR_NONE
AR5K_DESC_RX_PHY_ERROR_NONE
AR5K_DESC_RX_PHY_ERROR_PARITY
AR5K_DESC_RX_PHY_ERROR_PARITY
AR5K_DESC_RX_PHY_ERROR_RATE
AR5K_DESC_RX_PHY_ERROR_RATE
AR5K_DESC_RX_PHY_ERROR_SERVICE
AR5K_DESC_RX_PHY_ERROR_SERVICE
AR5K_DESC_RX_PHY_ERROR_TIMING
AR5K_DESC_RX_PHY_ERROR_TIMING
AR5K_DESC_RX_PHY_ERROR_TRANSMIT
AR5K_DESC_RX_PHY_ERROR_TRANSMIT
AR5K_DESC_TX_STATUS0_EXCESSIVE_
AR5K_DESC_TX_STATUS0_EXCESSIVE_
AR5K_DESC_TX_STATUS0_FIFO_UNDER
AR5K_DESC_TX_STATUS0_FIFO_UNDER
AR5K_DESC_TX_STATUS0_FILTERED
AR5K_DESC_TX_STATUS0_FILTERED
AR5K_DESC_TX_STATUS0_FRAME_XMIT
AR5K_DESC_TX_STATUS0_FRAME_XMIT
AR5K_DESC_TX_STATUS0_LONG_RETRY
AR5K_DESC_TX_STATUS0_LONG_RETRY
AR5K_DESC_TX_STATUS0_LONG_RETRY
AR5K_DESC_TX_STATUS0_LONG_RETRY
AR5K_DESC_TX_STATUS0_SEND_TIMES
AR5K_DESC_TX_STATUS0_SEND_TIMES
AR5K_DESC_TX_STATUS0_SEND_TIMES
AR5K_DESC_TX_STATUS0_SEND_TIMES
AR5K_DESC_TX_STATUS0_SHORT_RETR
AR5K_DESC_TX_STATUS0_SHORT_RETR
AR5K_DESC_TX_STATUS0_SHORT_RETR
AR5K_DESC_TX_STATUS0_SHORT_RETR
AR5K_DESC_TX_STATUS0_VIRT_COLL_
AR5K_DESC_TX_STATUS0_VIRT_COLL_
AR5K_DESC_TX_STATUS0_VIRT_COLL_
AR5K_DESC_TX_STATUS0_VIRT_COLL_
AR5K_DESC_TX_STATUS1_ACK_SIG_ST
AR5K_DESC_TX_STATUS1_ACK_SIG_ST
AR5K_DESC_TX_STATUS1_ACK_SIG_ST
AR5K_DESC_TX_STATUS1_ACK_SIG_ST
AR5K_DESC_TX_STATUS1_COMP_SUCCE
AR5K_DESC_TX_STATUS1_COMP_SUCCE
AR5K_DESC_TX_STATUS1_DONE
AR5K_DESC_TX_STATUS1_DONE
AR5K_DESC_TX_STATUS1_FINAL_TS_I
AR5K_DESC_TX_STATUS1_FINAL_TS_I
AR5K_DESC_TX_STATUS1_FINAL_TS_I
AR5K_DESC_TX_STATUS1_FINAL_TS_I
AR5K_DESC_TX_STATUS1_SEQ_NUM
AR5K_DESC_TX_STATUS1_SEQ_NUM
AR5K_DESC_TX_STATUS1_SEQ_NUM_S
AR5K_DESC_TX_STATUS1_SEQ_NUM_S
AR5K_DESC_TX_STATUS1_XMIT_ANTEN
AR5K_DESC_TX_STATUS1_XMIT_ANTEN
AR5K_DIAG_SW
AR5K_DIAG_SW
AR5K_DIAG_SW_5210	Register Address [5210]
AR5K_DIAG_SW_5210	Register Address [5210]
AR5K_DIAG_SW_5211	Register Address [5211+]
AR5K_DIAG_SW_5211	Register Address [5211+]
AR5K_DIAG_SW_CHAN_INFO
AR5K_DIAG_SW_CHAN_INFO
AR5K_DIAG_SW_CHAN_INFO_5210	Dump channel info
AR5K_DIAG_SW_CHAN_INFO_5210	Dump channel info
AR5K_DIAG_SW_CHAN_INFO_5211
AR5K_DIAG_SW_CHAN_INFO_5211
AR5K_DIAG_SW_CHANEL_IDLE_HIGH	Force channel idle high
AR5K_DIAG_SW_CHANEL_IDLE_HIGH	Force channel idle high
AR5K_DIAG_SW_CORR_FCS
AR5K_DIAG_SW_CORR_FCS
AR5K_DIAG_SW_CORR_FCS_5210	Corrupted FCS
AR5K_DIAG_SW_CORR_FCS_5210	Corrupted FCS
AR5K_DIAG_SW_CORR_FCS_5211
AR5K_DIAG_SW_CORR_FCS_5211
AR5K_DIAG_SW_DIS_ACK	Disable ACKs
AR5K_DIAG_SW_DIS_ACK	Disable ACKs
AR5K_DIAG_SW_DIS_CTS	Disable CTSs
AR5K_DIAG_SW_DIS_CTS	Disable CTSs
AR5K_DIAG_SW_DIS_DEC	Disable decryption
AR5K_DIAG_SW_DIS_DEC	Disable decryption
AR5K_DIAG_SW_DIS_ENC	Disable encryption
AR5K_DIAG_SW_DIS_ENC	Disable encryption
AR5K_DIAG_SW_DIS_RX
AR5K_DIAG_SW_DIS_RX
AR5K_DIAG_SW_DIS_RX_5210	Disable recieve
AR5K_DIAG_SW_DIS_RX_5210	Disable recieve
AR5K_DIAG_SW_DIS_RX_5211
AR5K_DIAG_SW_DIS_RX_5211
AR5K_DIAG_SW_DIS_SEQ_INC	Disable seqnum increment (?)[5210]
AR5K_DIAG_SW_DIS_SEQ_INC	Disable seqnum increment (?)[5210]
AR5K_DIAG_SW_DIS_TX	Disable transmit [5210]
AR5K_DIAG_SW_DIS_TX	Disable transmit [5210]
AR5K_DIAG_SW_DIS_WEP_ACK	Disable ACKs if WEP key is invalid
AR5K_DIAG_SW_DIS_WEP_ACK	Disable ACKs if WEP key is invalid
AR5K_DIAG_SW_ECO_ENABLE	[5211+]
AR5K_DIAG_SW_ECO_ENABLE	[5211+]
AR5K_DIAG_SW_EN_SCRAM_SEED
AR5K_DIAG_SW_EN_SCRAM_SEED
AR5K_DIAG_SW_EN_SCRAM_SEED_5210	Enable fixed scrambler seed
AR5K_DIAG_SW_EN_SCRAM_SEED_5210	Enable fixed scrambler seed
AR5K_DIAG_SW_EN_SCRAM_SEED_5211
AR5K_DIAG_SW_EN_SCRAM_SEED_5211
AR5K_DIAG_SW_FRAME_NV0
AR5K_DIAG_SW_FRAME_NV0
AR5K_DIAG_SW_FRAME_NV0_5210
AR5K_DIAG_SW_FRAME_NV0_5210
AR5K_DIAG_SW_FRAME_NV0_5211	Accept frames of non-zero protocol number
AR5K_DIAG_SW_FRAME_NV0_5211	Accept frames of non-zero protocol number
AR5K_DIAG_SW_IGNORE_CARR_SENSE	Ignore virtual carrier sense
AR5K_DIAG_SW_IGNORE_CARR_SENSE	Ignore virtual carrier sense
AR5K_DIAG_SW_LOOP_BACK
AR5K_DIAG_SW_LOOP_BACK
AR5K_DIAG_SW_LOOP_BACK_5210	Loopback (i guess it goes with DIS_TX) [5210]
AR5K_DIAG_SW_LOOP_BACK_5210	Loopback (i guess it goes with DIS_TX) [5210]
AR5K_DIAG_SW_LOOP_BACK_5211
AR5K_DIAG_SW_LOOP_BACK_5211
AR5K_DIAG_SW_OBSPT_M	Observation point select (?)
AR5K_DIAG_SW_OBSPT_M	Observation point select (?)
AR5K_DIAG_SW_OBSPT_S
AR5K_DIAG_SW_OBSPT_S
AR5K_DIAG_SW_PHEAR_ME	???
AR5K_DIAG_SW_PHEAR_ME	???
AR5K_DIAG_SW_RX_CLEAR_HIGH	Force RX Clear high
AR5K_DIAG_SW_RX_CLEAR_HIGH	Force RX Clear high
AR5K_DIAG_SW_SCRAM_SEED_M	Scrambler seed mask
AR5K_DIAG_SW_SCRAM_SEED_M	Scrambler seed mask
AR5K_DIAG_SW_SCRAM_SEED_S
AR5K_DIAG_SW_SCRAM_SEED_S
AR5K_DIAG_SW_SCVRAM_SEED	[5210]
AR5K_DIAG_SW_SCVRAM_SEED	[5210]
AR5K_DISABLE_QUEUE(_q)
AR5K_DISABLE_QUEUE(_q)
AR5K_EEPROM_AES_DIS(_v)
AR5K_EEPROM_AES_DIS(_v)
AR5K_EEPROM_ANT_GAIN(_v)
AR5K_EEPROM_ANT_GAIN(_v)
AR5K_EEPROM_ANT_GAIN_2GHZ(_v)
AR5K_EEPROM_ANT_GAIN_2GHZ(_v)
AR5K_EEPROM_ANT_GAIN_5GHZ(_v)
AR5K_EEPROM_ANT_GAIN_5GHZ(_v)
AR5K_EEPROM_ART_BUILD_NUM(_v)
AR5K_EEPROM_ART_BUILD_NUM(_v)
AR5K_EEPROM_BASE
AR5K_EEPROM_BASE
AR5K_EEPROM_BURST_DIS(_v)
AR5K_EEPROM_BURST_DIS(_v)
AR5K_EEPROM_CAL_DATA_START(_v)
AR5K_EEPROM_CAL_DATA_START(_v)
AR5K_EEPROM_CCK_OFDM_DELTA
AR5K_EEPROM_CCK_OFDM_DELTA
AR5K_EEPROM_CFG	Register Addres
AR5K_EEPROM_CFG	Register Addres
AR5K_EEPROM_CFG_CLK_RATE	Clock rate
AR5K_EEPROM_CFG_CLK_RATE	Clock rate
AR5K_EEPROM_CFG_CLK_RATE_156KHZ
AR5K_EEPROM_CFG_CLK_RATE_156KHZ
AR5K_EEPROM_CFG_CLK_RATE_312KHZ
AR5K_EEPROM_CFG_CLK_RATE_312KHZ
AR5K_EEPROM_CFG_CLK_RATE_625KHZ
AR5K_EEPROM_CFG_CLK_RATE_625KHZ
AR5K_EEPROM_CFG_CLK_RATE_S
AR5K_EEPROM_CFG_CLK_RATE_S
AR5K_EEPROM_CFG_LIND_EN	Enable length indicator (?)
AR5K_EEPROM_CFG_LIND_EN	Enable length indicator (?)
AR5K_EEPROM_CFG_PROT_KEY	Protection key
AR5K_EEPROM_CFG_PROT_KEY	Protection key
AR5K_EEPROM_CFG_PROT_KEY_S
AR5K_EEPROM_CFG_PROT_KEY_S
AR5K_EEPROM_CFG_SIZE	Size determination override
AR5K_EEPROM_CFG_SIZE	Size determination override
AR5K_EEPROM_CFG_SIZE_16KBIT
AR5K_EEPROM_CFG_SIZE_16KBIT
AR5K_EEPROM_CFG_SIZE_4KBIT
AR5K_EEPROM_CFG_SIZE_4KBIT
AR5K_EEPROM_CFG_SIZE_8KBIT
AR5K_EEPROM_CFG_SIZE_8KBIT
AR5K_EEPROM_CFG_SIZE_AUTO
AR5K_EEPROM_CFG_SIZE_AUTO
AR5K_EEPROM_CFG_WR_WAIT_DIS	Disable write wait
AR5K_EEPROM_CFG_WR_WAIT_DIS	Disable write wait
AR5K_EEPROM_CHANNEL_DIS
AR5K_EEPROM_CHANNEL_DIS
AR5K_EEPROM_CHANNEL_POWER
AR5K_EEPROM_CHANNEL_POWER
AR5K_EEPROM_CHECKSUM	EEPROM checksum
AR5K_EEPROM_CHECKSUM	EEPROM checksum
AR5K_EEPROM_CMD	Register Addres
AR5K_EEPROM_CMD	Register Addres
AR5K_EEPROM_CMD_READ	EEPROM read
AR5K_EEPROM_CMD_READ	EEPROM read
AR5K_EEPROM_CMD_RESET	EEPROM reset
AR5K_EEPROM_CMD_RESET	EEPROM reset
AR5K_EEPROM_CMD_WRITE	EEPROM write
AR5K_EEPROM_CMD_WRITE	EEPROM write
AR5K_EEPROM_COMP_DIS(_v)
AR5K_EEPROM_COMP_DIS(_v)
AR5K_EEPROM_CTL(_v)	Conformance test limits
AR5K_EEPROM_CTL(_v)	Conformance test limits
AR5K_EEPROM_DATA
AR5K_EEPROM_DATA
AR5K_EEPROM_DATA_5210
AR5K_EEPROM_DATA_5210
AR5K_EEPROM_DATA_5211
AR5K_EEPROM_DATA_5211
AR5K_EEPROM_EAR_FILE_ID(_v)
AR5K_EEPROM_EAR_FILE_ID(_v)
AR5K_EEPROM_EAR_FILE_VERSION(_v)
AR5K_EEPROM_EAR_FILE_VERSION(_v)
AR5K_EEPROM_EARSTART(_v)
AR5K_EEPROM_EARSTART(_v)
AR5K_EEPROM_EEMAP(_v)
AR5K_EEPROM_EEMAP(_v)
AR5K_EEPROM_EEP_DELTA
AR5K_EEPROM_EEP_DELTA
AR5K_EEPROM_EEP_FILE_VERSION(_v)
AR5K_EEPROM_EEP_FILE_VERSION(_v)
AR5K_EEPROM_EEP_SCALE
AR5K_EEPROM_EEP_SCALE
AR5K_EEPROM_FCC_MID_EN
AR5K_EEPROM_FCC_MID_EN
AR5K_EEPROM_FF_DIS(_v)
AR5K_EEPROM_FF_DIS(_v)
AR5K_EEPROM_FREQ_M(_v)
AR5K_EEPROM_FREQ_M(_v)
AR5K_EEPROM_GROUP1_OFFSET
AR5K_EEPROM_GROUP1_OFFSET
AR5K_EEPROM_GROUP2_OFFSET
AR5K_EEPROM_GROUP2_OFFSET
AR5K_EEPROM_GROUP3_OFFSET
AR5K_EEPROM_GROUP3_OFFSET
AR5K_EEPROM_GROUP4_OFFSET
AR5K_EEPROM_GROUP4_OFFSET
AR5K_EEPROM_GROUP5_OFFSET
AR5K_EEPROM_GROUP5_OFFSET
AR5K_EEPROM_GROUP6_OFFSET
AR5K_EEPROM_GROUP6_OFFSET
AR5K_EEPROM_GROUP7_OFFSET
AR5K_EEPROM_GROUP7_OFFSET
AR5K_EEPROM_GROUP8_OFFSET
AR5K_EEPROM_GROUP8_OFFSET
AR5K_EEPROM_GROUPS_START(_v)	Start of Groups
AR5K_EEPROM_GROUPS_START(_v)	Start of Groups
AR5K_EEPROM_HAS32KHZCRYSTAL(_v)
AR5K_EEPROM_HAS32KHZCRYSTAL(_v)
AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v)
AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v)
AR5K_EEPROM_HDR	Header that contains the device caps
AR5K_EEPROM_HDR	Header that contains the device caps
AR5K_EEPROM_HDR_11A(_v)
AR5K_EEPROM_HDR_11A(_v)
AR5K_EEPROM_HDR_11B(_v)
AR5K_EEPROM_HDR_11B(_v)
AR5K_EEPROM_HDR_11G(_v)
AR5K_EEPROM_HDR_11G(_v)
AR5K_EEPROM_HDR_DEVICE(_v)
AR5K_EEPROM_HDR_DEVICE(_v)
AR5K_EEPROM_HDR_RFKILL(_v)	Device has RFKill support
AR5K_EEPROM_HDR_RFKILL(_v)	Device has RFKill support
AR5K_EEPROM_HDR_T_2GHZ_DIS(_v)	Disable turbo for 2Ghz (?)
AR5K_EEPROM_HDR_T_2GHZ_DIS(_v)	Disable turbo for 2Ghz (?)
AR5K_EEPROM_HDR_T_5GHZ_DBM(_v)	Max turbo power for a/XR mode (eeprom_init)
AR5K_EEPROM_HDR_T_5GHZ_DBM(_v)	Max turbo power for a/XR mode (eeprom_init)
AR5K_EEPROM_HDR_T_5GHZ_DIS(_v)	Disable turbo for 5Ghz
AR5K_EEPROM_HDR_T_5GHZ_DIS(_v)	Disable turbo for 5Ghz
AR5K_EEPROM_HDR_XR2_DIS(_v)
AR5K_EEPROM_HDR_XR2_DIS(_v)
AR5K_EEPROM_HDR_XR5_DIS(_v)
AR5K_EEPROM_HDR_XR5_DIS(_v)
AR5K_EEPROM_HEAVY_CLIP_EN(_v)
AR5K_EEPROM_HEAVY_CLIP_EN(_v)
AR5K_EEPROM_I_GAIN
AR5K_EEPROM_I_GAIN
AR5K_EEPROM_INFO(_n)
AR5K_EEPROM_INFO(_n)
AR5K_EEPROM_INFO_BASE	EEPROM header
AR5K_EEPROM_INFO_BASE	EEPROM header
AR5K_EEPROM_INFO_CKSUM
AR5K_EEPROM_INFO_CKSUM
AR5K_EEPROM_INFO_MAX
AR5K_EEPROM_INFO_MAX
AR5K_EEPROM_IS_HB63	Talon detect
AR5K_EEPROM_IS_HB63	Talon detect
AR5K_EEPROM_JAP_11A_NEW_EN
AR5K_EEPROM_JAP_11A_NEW_EN
AR5K_EEPROM_JAP_U1EVEN_EN
AR5K_EEPROM_JAP_U1EVEN_EN
AR5K_EEPROM_JAP_U1ODD_EN
AR5K_EEPROM_JAP_U1ODD_EN
AR5K_EEPROM_JAP_U2_EN
AR5K_EEPROM_JAP_U2_EN
AR5K_EEPROM_KEY_CACHE_SIZE(_v)
AR5K_EEPROM_KEY_CACHE_SIZE(_v)
AR5K_EEPROM_MAGIC	EEPROM Magic number
AR5K_EEPROM_MAGIC	EEPROM Magic number
AR5K_EEPROM_MAGIC_5210	5210
AR5K_EEPROM_MAGIC_5210	5210
AR5K_EEPROM_MAGIC_5211	5211
AR5K_EEPROM_MAGIC_5211	5211
AR5K_EEPROM_MAGIC_5212	5212
AR5K_EEPROM_MAGIC_5212	5212
AR5K_EEPROM_MAGIC_VALUE	Default - found on EEPROM
AR5K_EEPROM_MAGIC_VALUE	Default - found on EEPROM
AR5K_EEPROM_MASK_R0(_v)
AR5K_EEPROM_MASK_R0(_v)
AR5K_EEPROM_MASK_R1(_v)
AR5K_EEPROM_MASK_R1(_v)
AR5K_EEPROM_MAX_CHAN
AR5K_EEPROM_MAX_CHAN
AR5K_EEPROM_MAX_CTLS
AR5K_EEPROM_MAX_CTLS
AR5K_EEPROM_MAX_QCU(_v)
AR5K_EEPROM_MAX_QCU(_v)
AR5K_EEPROM_MISC0
AR5K_EEPROM_MISC0
AR5K_EEPROM_MISC1
AR5K_EEPROM_MISC1
AR5K_EEPROM_MISC2
AR5K_EEPROM_MISC2
AR5K_EEPROM_MISC3
AR5K_EEPROM_MISC3
AR5K_EEPROM_MISC4
AR5K_EEPROM_MISC4
AR5K_EEPROM_MISC5
AR5K_EEPROM_MISC5
AR5K_EEPROM_MISC6
AR5K_EEPROM_MISC6
AR5K_EEPROM_MODE_11A
AR5K_EEPROM_MODE_11A
AR5K_EEPROM_MODE_11B
AR5K_EEPROM_MODE_11B
AR5K_EEPROM_MODE_11G
AR5K_EEPROM_MODE_11G
AR5K_EEPROM_MODES_11A(_v)
AR5K_EEPROM_MODES_11A(_v)
AR5K_EEPROM_MODES_11B(_v)
AR5K_EEPROM_MODES_11B(_v)
AR5K_EEPROM_MODES_11G(_v)
AR5K_EEPROM_MODES_11G(_v)
AR5K_EEPROM_N_2GHZ_CHAN
AR5K_EEPROM_N_2GHZ_CHAN
AR5K_EEPROM_N_2GHZ_CHAN_2413
AR5K_EEPROM_N_2GHZ_CHAN_2413
AR5K_EEPROM_N_2GHZ_CHAN_MAX
AR5K_EEPROM_N_2GHZ_CHAN_MAX
AR5K_EEPROM_N_5GHZ_CHAN
AR5K_EEPROM_N_5GHZ_CHAN
AR5K_EEPROM_N_CTLS(_v)
AR5K_EEPROM_N_CTLS(_v)
AR5K_EEPROM_N_EDGES
AR5K_EEPROM_N_EDGES
AR5K_EEPROM_N_INTERCEPT_10_2GHZ
AR5K_EEPROM_N_INTERCEPT_10_2GHZ
AR5K_EEPROM_N_INTERCEPT_10_5GHZ
AR5K_EEPROM_N_INTERCEPT_10_5GHZ
AR5K_EEPROM_N_INTERCEPTS
AR5K_EEPROM_N_INTERCEPTS
AR5K_EEPROM_N_IQ_CAL
AR5K_EEPROM_N_IQ_CAL
AR5K_EEPROM_N_MODES
AR5K_EEPROM_N_MODES
AR5K_EEPROM_N_OBDB
AR5K_EEPROM_N_OBDB
AR5K_EEPROM_N_PCDAC
AR5K_EEPROM_N_PCDAC
AR5K_EEPROM_N_PD_CURVES
AR5K_EEPROM_N_PD_CURVES
AR5K_EEPROM_N_PD_GAINS
AR5K_EEPROM_N_PD_GAINS
AR5K_EEPROM_N_PD_POINTS
AR5K_EEPROM_N_PD_POINTS
AR5K_EEPROM_N_PHASE_CAL
AR5K_EEPROM_N_PHASE_CAL
AR5K_EEPROM_N_POWER_LOC_11B
AR5K_EEPROM_N_POWER_LOC_11B
AR5K_EEPROM_N_POWER_LOC_11G
AR5K_EEPROM_N_POWER_LOC_11G
AR5K_EEPROM_N_PWR_POINTS_5111
AR5K_EEPROM_N_PWR_POINTS_5111
AR5K_EEPROM_N_TEST_FREQ
AR5K_EEPROM_N_TEST_FREQ
AR5K_EEPROM_N_XPD0_POINTS
AR5K_EEPROM_N_XPD0_POINTS
AR5K_EEPROM_N_XPD3_POINTS
AR5K_EEPROM_N_XPD3_POINTS
AR5K_EEPROM_NON_EDGE_M
AR5K_EEPROM_NON_EDGE_M
AR5K_EEPROM_OBDB_DIS
AR5K_EEPROM_OBDB_DIS
AR5K_EEPROM_OBDB0_2GHZ
AR5K_EEPROM_OBDB0_2GHZ
AR5K_EEPROM_OBDB1_2GHZ
AR5K_EEPROM_OBDB1_2GHZ
AR5K_EEPROM_OFF(_v, _v3_0, _v3_3)
AR5K_EEPROM_OFF(_v, _v3_0, _v3_3)
AR5K_EEPROM_PCDAC_M
AR5K_EEPROM_PCDAC_M
AR5K_EEPROM_PCDAC_START
AR5K_EEPROM_PCDAC_START
AR5K_EEPROM_PCDAC_STEP
AR5K_EEPROM_PCDAC_STEP
AR5K_EEPROM_PCDAC_STOP
AR5K_EEPROM_PCDAC_STOP
AR5K_EEPROM_POWER_M
AR5K_EEPROM_POWER_M
AR5K_EEPROM_POWER_MAX
AR5K_EEPROM_POWER_MAX
AR5K_EEPROM_POWER_MIN
AR5K_EEPROM_POWER_MIN
AR5K_EEPROM_POWER_STEP
AR5K_EEPROM_POWER_STEP
AR5K_EEPROM_POWER_TABLE_SIZE
AR5K_EEPROM_POWER_TABLE_SIZE
AR5K_EEPROM_PROTECT	EEPROM protect status
AR5K_EEPROM_PROTECT	EEPROM protect status
AR5K_EEPROM_PROTECT_RD_0_31	Read protection bit for offsets 0x0 - 0x1f
AR5K_EEPROM_PROTECT_RD_0_31	Read protection bit for offsets 0x0 - 0x1f
AR5K_EEPROM_PROTECT_RD_128_191	0x80 - 0xbf (regdom)
AR5K_EEPROM_PROTECT_RD_128_191	0x80 - 0xbf (regdom)
AR5K_EEPROM_PROTECT_RD_192_207	0xc0 - 0xcf
AR5K_EEPROM_PROTECT_RD_192_207	0xc0 - 0xcf
AR5K_EEPROM_PROTECT_RD_208_223	0xd0 - 0xdf
AR5K_EEPROM_PROTECT_RD_208_223	0xd0 - 0xdf
AR5K_EEPROM_PROTECT_RD_224_239	0xe0 - 0xef
AR5K_EEPROM_PROTECT_RD_224_239	0xe0 - 0xef
AR5K_EEPROM_PROTECT_RD_240_255	0xf0 - 0xff
AR5K_EEPROM_PROTECT_RD_240_255	0xf0 - 0xff
AR5K_EEPROM_PROTECT_RD_32_63	0x20 - 0x3f
AR5K_EEPROM_PROTECT_RD_32_63	0x20 - 0x3f
AR5K_EEPROM_PROTECT_RD_64_127	0x40 - 0x7f
AR5K_EEPROM_PROTECT_RD_64_127	0x40 - 0x7f
AR5K_EEPROM_PROTECT_WR_0_31	Write protection bit for offsets 0x0 - 0x1f
AR5K_EEPROM_PROTECT_WR_0_31	Write protection bit for offsets 0x0 - 0x1f
AR5K_EEPROM_PROTECT_WR_128_191
AR5K_EEPROM_PROTECT_WR_128_191
AR5K_EEPROM_PROTECT_WR_192_207
AR5K_EEPROM_PROTECT_WR_192_207
AR5K_EEPROM_PROTECT_WR_208_223
AR5K_EEPROM_PROTECT_WR_208_223
AR5K_EEPROM_PROTECT_WR_224_239
AR5K_EEPROM_PROTECT_WR_224_239
AR5K_EEPROM_PROTECT_WR_240_255
AR5K_EEPROM_PROTECT_WR_240_255
AR5K_EEPROM_PROTECT_WR_32_63
AR5K_EEPROM_PROTECT_WR_32_63
AR5K_EEPROM_PROTECT_WR_64_127
AR5K_EEPROM_PROTECT_WR_64_127
AR5K_EEPROM_READ(_o, _v)
AR5K_EEPROM_READ(_o, _v)
AR5K_EEPROM_READ_HDR(_o, _v)
AR5K_EEPROM_READ_HDR(_o, _v)
AR5K_EEPROM_REG_DOMAIN	EEPROM regdom
AR5K_EEPROM_REG_DOMAIN	EEPROM regdom
AR5K_EEPROM_RFKILL
AR5K_EEPROM_RFKILL
AR5K_EEPROM_RFKILL_GPIO_SEL
AR5K_EEPROM_RFKILL_GPIO_SEL
AR5K_EEPROM_RFKILL_GPIO_SEL
AR5K_EEPROM_RFKILL_GPIO_SEL
AR5K_EEPROM_RFKILL_GPIO_SEL_S
AR5K_EEPROM_RFKILL_GPIO_SEL_S
AR5K_EEPROM_RFKILL_GPIO_SEL_S
AR5K_EEPROM_RFKILL_GPIO_SEL_S
AR5K_EEPROM_RFKILL_POLARITY
AR5K_EEPROM_RFKILL_POLARITY
AR5K_EEPROM_RFKILL_POLARITY
AR5K_EEPROM_RFKILL_POLARITY
AR5K_EEPROM_RFKILL_POLARITY_S
AR5K_EEPROM_RFKILL_POLARITY_S
AR5K_EEPROM_RFKILL_POLARITY_S
AR5K_EEPROM_RFKILL_POLARITY_S
AR5K_EEPROM_RX_CHAIN_DIS
AR5K_EEPROM_RX_CHAIN_DIS
AR5K_EEPROM_SCALE_OC_DELTA(_x)
AR5K_EEPROM_SCALE_OC_DELTA(_x)
AR5K_EEPROM_STAT_5210	Register Address [5210]
AR5K_EEPROM_STAT_5210	Register Address [5210]
AR5K_EEPROM_STAT_5211	Register Address [5211+]
AR5K_EEPROM_STAT_5211	Register Address [5211+]
AR5K_EEPROM_STAT_RDDONE	EEPROM read successful
AR5K_EEPROM_STAT_RDDONE	EEPROM read successful
AR5K_EEPROM_STAT_RDERR	EEPROM read failed
AR5K_EEPROM_STAT_RDERR	EEPROM read failed
AR5K_EEPROM_STAT_WRDONE	EEPROM write successful
AR5K_EEPROM_STAT_WRDONE	EEPROM write successful
AR5K_EEPROM_STAT_WRERR	EEPROM write failed
AR5K_EEPROM_STAT_WRERR	EEPROM write failed
AR5K_EEPROM_STATUS
AR5K_EEPROM_STATUS
AR5K_EEPROM_TARGET_PWR_OFF_11A(_v)
AR5K_EEPROM_TARGET_PWR_OFF_11A(_v)
AR5K_EEPROM_TARGET_PWR_OFF_11B(_v)
AR5K_EEPROM_TARGET_PWR_OFF_11B(_v)
AR5K_EEPROM_TARGET_PWR_OFF_11G(_v)
AR5K_EEPROM_TARGET_PWR_OFF_11G(_v)
AR5K_EEPROM_TARGET_PWRSTART(_v)
AR5K_EEPROM_TARGET_PWRSTART(_v)
AR5K_EEPROM_TX_CHAIN_DIS
AR5K_EEPROM_TX_CHAIN_DIS
AR5K_EEPROM_VERSION	EEPROM Version
AR5K_EEPROM_VERSION	EEPROM Version
AR5K_EEPROM_VERSION_3_0	No idea what's going on before this version
AR5K_EEPROM_VERSION_3_0	No idea what's going on before this version
AR5K_EEPROM_VERSION_3_1	ob/db values for 2Ghz (ar5211_rfregs)
AR5K_EEPROM_VERSION_3_1	ob/db values for 2Ghz (ar5211_rfregs)
AR5K_EEPROM_VERSION_3_2	different frequency representation (eeprom_bin2freq)
AR5K_EEPROM_VERSION_3_2	different frequency representation (eeprom_bin2freq)
AR5K_EEPROM_VERSION_3_3	offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes)
AR5K_EEPROM_VERSION_3_3	offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes)
AR5K_EEPROM_VERSION_3_4	has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes)
AR5K_EEPROM_VERSION_3_4	has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes)
AR5K_EEPROM_VERSION_4_0	has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init)
AR5K_EEPROM_VERSION_4_0	has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init)
AR5K_EEPROM_VERSION_4_1	has ee_margin_tx_rx (eeprom_init)
AR5K_EEPROM_VERSION_4_1	has ee_margin_tx_rx (eeprom_init)
AR5K_EEPROM_VERSION_4_2	has ee_cck_ofdm_gain_delta (eeprom_init)
AR5K_EEPROM_VERSION_4_2	has ee_cck_ofdm_gain_delta (eeprom_init)
AR5K_EEPROM_VERSION_4_3	power calibration changes
AR5K_EEPROM_VERSION_4_3	power calibration changes
AR5K_EEPROM_VERSION_4_4
AR5K_EEPROM_VERSION_4_4
AR5K_EEPROM_VERSION_4_5
AR5K_EEPROM_VERSION_4_5
AR5K_EEPROM_VERSION_4_6	has ee_scaled_cck_delta
AR5K_EEPROM_VERSION_4_6	has ee_scaled_cck_delta
AR5K_EEPROM_VERSION_4_7	4007 ?
AR5K_EEPROM_VERSION_4_7	4007 ?
AR5K_EEPROM_VERSION_4_9	EAR futureproofing
AR5K_EEPROM_VERSION_4_9	EAR futureproofing
AR5K_EEPROM_VERSION_5_0	Has 2413 PDADC calibration etc
AR5K_EEPROM_VERSION_5_0	Has 2413 PDADC calibration etc
AR5K_EEPROM_VERSION_5_1	Has capability values
AR5K_EEPROM_VERSION_5_1	Has capability values
AR5K_EEPROM_VERSION_5_3	Has spur mitigation tables
AR5K_EEPROM_VERSION_5_3	Has spur mitigation tables
AR5K_ENABLE_QUEUE(_q)
AR5K_ENABLE_QUEUE(_q)
AR5K_FCS_FAIL
AR5K_FCS_FAIL
AR5K_FCS_FAIL_5210
AR5K_FCS_FAIL_5210
AR5K_FCS_FAIL_5211
AR5K_FCS_FAIL_5211
AR5K_FRAME_CTL_QOSM
AR5K_FRAME_CTL_QOSM
AR5K_GAIN_CCK_OFDM_GAIN_DELTA
AR5K_GAIN_CCK_OFDM_GAIN_DELTA
AR5K_GAIN_CCK_PROBE_CORR
AR5K_GAIN_CCK_PROBE_CORR
AR5K_GAIN_CHECK_ADJUST(_g)
AR5K_GAIN_CHECK_ADJUST(_g)
AR5K_GAIN_CRN_FIX_BITS_5111
AR5K_GAIN_CRN_FIX_BITS_5111
AR5K_GAIN_CRN_FIX_BITS_5112
AR5K_GAIN_CRN_FIX_BITS_5112
AR5K_GAIN_CRN_MAX_FIX_BITS
AR5K_GAIN_CRN_MAX_FIX_BITS
AR5K_GAIN_DYN_ADJUST_HI_MARGIN
AR5K_GAIN_DYN_ADJUST_HI_MARGIN
AR5K_GAIN_DYN_ADJUST_LO_MARGIN
AR5K_GAIN_DYN_ADJUST_LO_MARGIN
AR5K_GAIN_STEP_COUNT
AR5K_GAIN_STEP_COUNT
AR5K_GPIOCR	Register Address
AR5K_GPIOCR	Register Address
AR5K_GPIOCR_IN(n)	Mode 0 for pin n
AR5K_GPIOCR_IN(n)	Mode 0 for pin n
AR5K_GPIOCR_INT_ENA	Enable GPIO interrupt
AR5K_GPIOCR_INT_ENA	Enable GPIO interrupt
AR5K_GPIOCR_INT_SEL(n)	Interrupt for GPIO pin n
AR5K_GPIOCR_INT_SEL(n)	Interrupt for GPIO pin n
AR5K_GPIOCR_INT_SELH	Generate interrupt when pin is high
AR5K_GPIOCR_INT_SELH	Generate interrupt when pin is high
AR5K_GPIOCR_INT_SELL	Generate interrupt when pin is low
AR5K_GPIOCR_INT_SELL	Generate interrupt when pin is low
AR5K_GPIOCR_OUT(n)	Mode 3 for pin n
AR5K_GPIOCR_OUT(n)	Mode 3 for pin n
AR5K_GPIOCR_OUT0(n)	Mode 1 for pin n
AR5K_GPIOCR_OUT0(n)	Mode 1 for pin n
AR5K_GPIOCR_OUT1(n)	Mode 2 for pin n
AR5K_GPIOCR_OUT1(n)	Mode 2 for pin n
AR5K_GPIODI
AR5K_GPIODI
AR5K_GPIODI_M
AR5K_GPIODI_M
AR5K_GPIODO
AR5K_GPIODO
AR5K_HIGH_ID(_a)
AR5K_HIGH_ID(_a)
AR5K_IER	Register Address
AR5K_IER	Register Address
AR5K_IER_DISABLE	Disable card interrupts
AR5K_IER_DISABLE	Disable card interrupts
AR5K_IER_ENABLE	Enable card interrupts
AR5K_IER_ENABLE	Enable card interrupts
AR5K_IFS0
AR5K_IFS0
AR5K_IFS0_DIFS
AR5K_IFS0_DIFS
AR5K_IFS0_DIFS_S
AR5K_IFS0_DIFS_S
AR5K_IFS0_SIFS
AR5K_IFS0_SIFS
AR5K_IFS0_SIFS_S
AR5K_IFS0_SIFS_S
AR5K_IFS1
AR5K_IFS1
AR5K_IFS1_CS_EN
AR5K_IFS1_CS_EN
AR5K_IFS1_EIFS
AR5K_IFS1_EIFS
AR5K_IFS1_EIFS_S
AR5K_IFS1_EIFS_S
AR5K_IFS1_PIFS
AR5K_IFS1_PIFS
AR5K_IFS1_PIFS_S
AR5K_IFS1_PIFS_S
AR5K_IMR	Register Address [5210]
AR5K_IMR	Register Address [5210]
AR5K_IMR_BCNMISC	'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
AR5K_IMR_BCNMISC	'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
AR5K_IMR_BMISS	Beacon missed
AR5K_IMR_BMISS	Beacon missed
AR5K_IMR_BNR	Beacon not ready [5211+]
AR5K_IMR_BNR	Beacon not ready [5211+]
AR5K_IMR_BRSSI	Beacon rssi below threshold (?)
AR5K_IMR_BRSSI	Beacon rssi below threshold (?)
AR5K_IMR_DPERR	Det par Error (?) [5210]
AR5K_IMR_DPERR	Det par Error (?) [5210]
AR5K_IMR_GPIO	GPIO (rf kill)
AR5K_IMR_GPIO	GPIO (rf kill)
AR5K_IMR_HIUERR	Host Interface Unit error [5211+]
AR5K_IMR_HIUERR	Host Interface Unit error [5211+]
AR5K_IMR_MCABT	Master Cycle Abort [5210]
AR5K_IMR_MCABT	Master Cycle Abort [5210]
AR5K_IMR_MIB	Update MIB counters
AR5K_IMR_MIB	Update MIB counters
AR5K_IMR_QCBRORN	QCU CBR overrun (?) [5211+]
AR5K_IMR_QCBRORN	QCU CBR overrun (?) [5211+]
AR5K_IMR_QCBRURN	QCU CBR underrun (?) [5211+]
AR5K_IMR_QCBRURN	QCU CBR underrun (?) [5211+]
AR5K_IMR_QTRIG	QCU scheduling trigger [5211+]
AR5K_IMR_QTRIG	QCU scheduling trigger [5211+]
AR5K_IMR_RXCHIRP	CHIRP Received [5212+]
AR5K_IMR_RXCHIRP	CHIRP Received [5212+]
AR5K_IMR_RXDESC	RX descriptor request
AR5K_IMR_RXDESC	RX descriptor request
AR5K_IMR_RXDOPPLER	Doppler chirp received [5212+]
AR5K_IMR_RXDOPPLER	Doppler chirp received [5212+]
AR5K_IMR_RXEOL	Empty RX descriptor
AR5K_IMR_RXEOL	Empty RX descriptor
AR5K_IMR_RXERR	Receive error
AR5K_IMR_RXERR	Receive error
AR5K_IMR_RXKCM	RX Key cache miss
AR5K_IMR_RXKCM	RX Key cache miss
AR5K_IMR_RXNOFRM	No frame received (receive timeout)
AR5K_IMR_RXNOFRM	No frame received (receive timeout)
AR5K_IMR_RXOK	Frame successfuly recieved
AR5K_IMR_RXOK	Frame successfuly recieved
AR5K_IMR_RXORN	Receive FIFO overrun
AR5K_IMR_RXORN	Receive FIFO overrun
AR5K_IMR_RXPHY	PHY error
AR5K_IMR_RXPHY	PHY error
AR5K_IMR_SSERR	Signaled System Error [5210]
AR5K_IMR_SSERR	Signaled System Error [5210]
AR5K_IMR_SWBA	Software beacon alert
AR5K_IMR_SWBA	Software beacon alert
AR5K_IMR_SWI	Software interrupt
AR5K_IMR_SWI	Software interrupt
AR5K_IMR_TIM	[5211+]
AR5K_IMR_TIM	[5211+]
AR5K_IMR_TXDESC	TX descriptor request
AR5K_IMR_TXDESC	TX descriptor request
AR5K_IMR_TXEOL	Empty TX descriptor
AR5K_IMR_TXEOL	Empty TX descriptor
AR5K_IMR_TXERR	Transmit error
AR5K_IMR_TXERR	Transmit error
AR5K_IMR_TXNOFRM	No frame transmited (transmit timeout)
AR5K_IMR_TXNOFRM	No frame transmited (transmit timeout)
AR5K_IMR_TXOK	Frame successfuly transmited
AR5K_IMR_TXOK	Frame successfuly transmited
AR5K_IMR_TXURN	Transmit FIFO underrun
AR5K_IMR_TXURN	Transmit FIFO underrun
AR5K_INI_RFGAIN_2GHZ
AR5K_INI_RFGAIN_2GHZ
AR5K_INI_RFGAIN_5GHZ
AR5K_INI_RFGAIN_5GHZ
AR5K_INI_VAL_11A
AR5K_INI_VAL_11A
AR5K_INI_VAL_11A_TURBO
AR5K_INI_VAL_11A_TURBO
AR5K_INI_VAL_11B
AR5K_INI_VAL_11B
AR5K_INI_VAL_11G
AR5K_INI_VAL_11G
AR5K_INI_VAL_11G_TURBO
AR5K_INI_VAL_11G_TURBO
AR5K_INI_VAL_MAX
AR5K_INI_VAL_MAX
AR5K_INI_VAL_XR
AR5K_INI_VAL_XR
AR5K_INIT_ACK_CTS_TIMEOUT
AR5K_INIT_ACK_CTS_TIMEOUT
AR5K_INIT_ACK_CTS_TIMEOUT_TURBO
AR5K_INIT_ACK_CTS_TIMEOUT_TURBO
AR5K_INIT_CARR_SENSE_EN
AR5K_INIT_CARR_SENSE_EN
AR5K_INIT_CFG
AR5K_INIT_CFG
AR5K_INIT_CFG
AR5K_INIT_CFG
AR5K_INIT_CYCRSSI_THR1
AR5K_INIT_CYCRSSI_THR1
AR5K_INIT_EIFS
AR5K_INIT_EIFS
AR5K_INIT_EIFS_TURBO
AR5K_INIT_EIFS_TURBO
AR5K_INIT_LG_RETRY
AR5K_INIT_LG_RETRY
AR5K_INIT_PROG_IFS
AR5K_INIT_PROG_IFS
AR5K_INIT_PROG_IFS_TURBO
AR5K_INIT_PROG_IFS_TURBO
AR5K_INIT_PROTO_TIME_CNTRL
AR5K_INIT_PROTO_TIME_CNTRL
AR5K_INIT_PROTO_TIME_CNTRL_TURB
AR5K_INIT_PROTO_TIME_CNTRL_TURB
AR5K_INIT_SH_RETRY
AR5K_INIT_SH_RETRY
AR5K_INIT_SIFS
AR5K_INIT_SIFS
AR5K_INIT_SIFS_TURBO
AR5K_INIT_SIFS_TURBO
AR5K_INIT_SLG_RETRY
AR5K_INIT_SLG_RETRY
AR5K_INIT_SLOT_TIME
AR5K_INIT_SLOT_TIME
AR5K_INIT_SLOT_TIME_TURBO
AR5K_INIT_SLOT_TIME_TURBO
AR5K_INIT_SSH_RETRY
AR5K_INIT_SSH_RETRY
AR5K_INIT_TRANSMIT_LATENCY
AR5K_INIT_TRANSMIT_LATENCY
AR5K_INIT_TRANSMIT_LATENCY_TURB
AR5K_INIT_TRANSMIT_LATENCY_TURB
AR5K_INIT_TX_LATENCY
AR5K_INIT_TX_LATENCY
AR5K_INIT_TX_RETRY
AR5K_INIT_TX_RETRY
AR5K_INIT_USEC
AR5K_INIT_USEC
AR5K_INIT_USEC_32
AR5K_INIT_USEC_32
AR5K_INIT_USEC_TURBO
AR5K_INIT_USEC_TURBO
AR5K_INTPEND
AR5K_INTPEND
AR5K_INTPEND_M
AR5K_INTPEND_M
AR5K_ISR	Register Address [5210]
AR5K_ISR	Register Address [5210]
AR5K_ISR_BCNMISC	'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
AR5K_ISR_BCNMISC	'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
AR5K_ISR_BMISS	Beacon missed
AR5K_ISR_BMISS	Beacon missed
AR5K_ISR_BNR	Beacon not ready [5211+]
AR5K_ISR_BNR	Beacon not ready [5211+]
AR5K_ISR_BRSSI	Beacon rssi below threshold (?)
AR5K_ISR_BRSSI	Beacon rssi below threshold (?)
AR5K_ISR_DPERR	Det par Error (?) [5210]
AR5K_ISR_DPERR	Det par Error (?) [5210]
AR5K_ISR_GPIO	GPIO (rf kill)
AR5K_ISR_GPIO	GPIO (rf kill)
AR5K_ISR_HIUERR	Host Interface Unit error [5211+]
AR5K_ISR_HIUERR	Host Interface Unit error [5211+]
AR5K_ISR_MCABT	Master Cycle Abort [5210]
AR5K_ISR_MCABT	Master Cycle Abort [5210]
AR5K_ISR_MIB	Update MIB counters
AR5K_ISR_MIB	Update MIB counters
AR5K_ISR_QCBRORN	QCU CBR overrun [5211+]
AR5K_ISR_QCBRORN	QCU CBR overrun [5211+]
AR5K_ISR_QCBRURN	QCU CBR underrun [5211+]
AR5K_ISR_QCBRURN	QCU CBR underrun [5211+]
AR5K_ISR_QTRIG	QCU scheduling trigger [5211+]
AR5K_ISR_QTRIG	QCU scheduling trigger [5211+]
AR5K_ISR_RXCHIRP	CHIRP Received [5212+]
AR5K_ISR_RXCHIRP	CHIRP Received [5212+]
AR5K_ISR_RXDESC	RX descriptor request
AR5K_ISR_RXDESC	RX descriptor request
AR5K_ISR_RXDOPPLER	Doppler chirp received [5212+]
AR5K_ISR_RXDOPPLER	Doppler chirp received [5212+]
AR5K_ISR_RXEOL	Empty RX descriptor
AR5K_ISR_RXEOL	Empty RX descriptor
AR5K_ISR_RXERR	Receive error
AR5K_ISR_RXERR	Receive error
AR5K_ISR_RXKCM	RX Key cache miss
AR5K_ISR_RXKCM	RX Key cache miss
AR5K_ISR_RXNOFRM	No frame received (receive timeout)
AR5K_ISR_RXNOFRM	No frame received (receive timeout)
AR5K_ISR_RXOK	Frame successfuly recieved
AR5K_ISR_RXOK	Frame successfuly recieved
AR5K_ISR_RXORN	Receive FIFO overrun
AR5K_ISR_RXORN	Receive FIFO overrun
AR5K_ISR_RXPHY	PHY error
AR5K_ISR_RXPHY	PHY error
AR5K_ISR_SSERR	Signaled System Error [5210]
AR5K_ISR_SSERR	Signaled System Error [5210]
AR5K_ISR_SWBA	Software beacon alert
AR5K_ISR_SWBA	Software beacon alert
AR5K_ISR_SWI	Software interrupt
AR5K_ISR_SWI	Software interrupt
AR5K_ISR_TIM	[5211+]
AR5K_ISR_TIM	[5211+]
AR5K_ISR_TXDESC	TX descriptor request
AR5K_ISR_TXDESC	TX descriptor request
AR5K_ISR_TXEOL	Empty TX descriptor
AR5K_ISR_TXEOL	Empty TX descriptor
AR5K_ISR_TXERR	Transmit error
AR5K_ISR_TXERR	Transmit error
AR5K_ISR_TXNOFRM	No frame transmited (transmit timeout)
AR5K_ISR_TXNOFRM	No frame transmited (transmit timeout)
AR5K_ISR_TXOK	Frame successfuly transmited
AR5K_ISR_TXOK	Frame successfuly transmited
AR5K_ISR_TXURN	Transmit FIFO underrun
AR5K_ISR_TXURN	Transmit FIFO underrun
AR5K_KEYCACHE_SIZE
AR5K_KEYCACHE_SIZE
AR5K_KEYTABLE(_n)
AR5K_KEYTABLE(_n)
AR5K_KEYTABLE_0_5210
AR5K_KEYTABLE_0_5210
AR5K_KEYTABLE_0_5211
AR5K_KEYTABLE_0_5211
AR5K_KEYTABLE_5210(_n)
AR5K_KEYTABLE_5210(_n)
AR5K_KEYTABLE_5211(_n)
AR5K_KEYTABLE_5211(_n)
AR5K_KEYTABLE_ANTENNA	[5212+]
AR5K_KEYTABLE_ANTENNA	[5212+]
AR5K_KEYTABLE_MAC0(_n)
AR5K_KEYTABLE_MAC0(_n)
AR5K_KEYTABLE_MAC1(_n)
AR5K_KEYTABLE_MAC1(_n)
AR5K_KEYTABLE_MIC_OFFSET
AR5K_KEYTABLE_MIC_OFFSET
AR5K_KEYTABLE_OFF(_n, x)
AR5K_KEYTABLE_OFF(_n, x)
AR5K_KEYTABLE_SIZE
AR5K_KEYTABLE_SIZE
AR5K_KEYTABLE_SIZE_5210
AR5K_KEYTABLE_SIZE_5210
AR5K_KEYTABLE_SIZE_5211
AR5K_KEYTABLE_SIZE_5211
AR5K_KEYTABLE_TYPE(_n)
AR5K_KEYTABLE_TYPE(_n)
AR5K_KEYTABLE_TYPE_104
AR5K_KEYTABLE_TYPE_104
AR5K_KEYTABLE_TYPE_128
AR5K_KEYTABLE_TYPE_128
AR5K_KEYTABLE_TYPE_40
AR5K_KEYTABLE_TYPE_40
AR5K_KEYTABLE_TYPE_AES	[5211+]
AR5K_KEYTABLE_TYPE_AES	[5211+]
AR5K_KEYTABLE_TYPE_CCM	[5212+]
AR5K_KEYTABLE_TYPE_CCM	[5212+]
AR5K_KEYTABLE_TYPE_NULL	[5211+]
AR5K_KEYTABLE_TYPE_NULL	[5211+]
AR5K_KEYTABLE_TYPE_TKIP	[5212+]
AR5K_KEYTABLE_TYPE_TKIP	[5212+]
AR5K_KEYTABLE_VALID
AR5K_KEYTABLE_VALID
AR5K_LAST_TSTP
AR5K_LAST_TSTP
AR5K_LOW_ID(_a)
AR5K_LOW_ID(_a)
AR5K_MAX_GPIO
AR5K_MAX_GPIO
AR5K_MAX_RATES
AR5K_MAX_RATES
AR5K_MAX_RF_BANKS
AR5K_MAX_RF_BANKS
AR5K_MCAST_FILTER0
AR5K_MCAST_FILTER0
AR5K_MCAST_FILTER0_5210
AR5K_MCAST_FILTER0_5210
AR5K_MCAST_FILTER0_5211
AR5K_MCAST_FILTER0_5211
AR5K_MCAST_FILTER1
AR5K_MCAST_FILTER1
AR5K_MCAST_FILTER1_5210
AR5K_MCAST_FILTER1_5210
AR5K_MCAST_FILTER1_5211
AR5K_MCAST_FILTER1_5211
AR5K_MIBC	Register Address
AR5K_MIBC	Register Address
AR5K_MIBC_CMC	Clean MIB Counters
AR5K_MIBC_CMC	Clean MIB Counters
AR5K_MIBC_COW	Warn test indicator
AR5K_MIBC_COW	Warn test indicator
AR5K_MIBC_FMC	Freeze MIB Counters
AR5K_MIBC_FMC	Freeze MIB Counters
AR5K_MIBC_MCS	MIB counter strobe
AR5K_MIBC_MCS	MIB counter strobe
AR5K_MIC_QOS_CTL	Register Address
AR5K_MIC_QOS_CTL	Register Address
AR5K_MIC_QOS_CTL_MQ_EN	Enable MIC QoS
AR5K_MIC_QOS_CTL_MQ_EN	Enable MIC QoS
AR5K_MIC_QOS_CTL_OFF(_n)
AR5K_MIC_QOS_CTL_OFF(_n)
AR5K_MIC_QOS_SEL
AR5K_MIC_QOS_SEL
AR5K_MIC_QOS_SEL_OFF(_n)
AR5K_MIC_QOS_SEL_OFF(_n)
AR5K_MISC	Register Address
AR5K_MISC	Register Address
AR5K_MISC_DMA_OBS_M
AR5K_MISC_DMA_OBS_M
AR5K_MISC_DMA_OBS_S
AR5K_MISC_DMA_OBS_S
AR5K_MISC_LED_BLINK	[5210]
AR5K_MISC_LED_BLINK	[5210]
AR5K_MISC_LED_DECAY	[5210]
AR5K_MISC_LED_DECAY	[5210]
AR5K_MISC_MAC_OBS_LSB_M
AR5K_MISC_MAC_OBS_LSB_M
AR5K_MISC_MAC_OBS_LSB_S
AR5K_MISC_MAC_OBS_LSB_S
AR5K_MISC_MAC_OBS_MSB_M
AR5K_MISC_MAC_OBS_MSB_M
AR5K_MISC_MAC_OBS_MSB_S
AR5K_MISC_MAC_OBS_MSB_S
AR5K_MISC_MISC_OBS_M
AR5K_MISC_MISC_OBS_M
AR5K_MISC_MISC_OBS_S
AR5K_MISC_MISC_OBS_S
AR5K_MISC_MODE	Register Address
AR5K_MISC_MODE	Register Address
AR5K_MISC_MODE_ACKSIFS_MEM	ACK SIFS memory (?)
AR5K_MISC_MODE_ACKSIFS_MEM	ACK SIFS memory (?)
AR5K_MISC_MODE_COMBINED_MIC	use rx/tx MIC key
AR5K_MISC_MODE_COMBINED_MIC	use rx/tx MIC key
AR5K_MISC_MODE_FBSSID_MATCH	Force BSSID match
AR5K_MISC_MODE_FBSSID_MATCH	Force BSSID match
AR5K_NAV
AR5K_NAV
AR5K_NAV_5210
AR5K_NAV_5210
AR5K_NAV_5211
AR5K_NAV_5211
AR5K_NODCU_RETRY_LMT	Register Address
AR5K_NODCU_RETRY_LMT	Register Address
AR5K_NODCU_RETRY_LMT_CW_MIN	Minimum contention window mask
AR5K_NODCU_RETRY_LMT_CW_MIN	Minimum contention window mask
AR5K_NODCU_RETRY_LMT_CW_MIN_S
AR5K_NODCU_RETRY_LMT_CW_MIN_S
AR5K_NODCU_RETRY_LMT_LG_RETRY	Long retry mask
AR5K_NODCU_RETRY_LMT_LG_RETRY	Long retry mask
AR5K_NODCU_RETRY_LMT_LG_RETRY_S
AR5K_NODCU_RETRY_LMT_LG_RETRY_S
AR5K_NODCU_RETRY_LMT_SH_RETRY	Short retry limit mask
AR5K_NODCU_RETRY_LMT_SH_RETRY	Short retry limit mask
AR5K_NODCU_RETRY_LMT_SH_RETRY_S
AR5K_NODCU_RETRY_LMT_SH_RETRY_S
AR5K_NODCU_RETRY_LMT_SLG_RETRY	Station long retry limit mask
AR5K_NODCU_RETRY_LMT_SLG_RETRY	Station long retry limit mask
AR5K_NODCU_RETRY_LMT_SLG_RETRY_
AR5K_NODCU_RETRY_LMT_SLG_RETRY_
AR5K_NODCU_RETRY_LMT_SSH_RETRY	Station short retry limit mask
AR5K_NODCU_RETRY_LMT_SSH_RETRY	Station short retry limit mask
AR5K_NODCU_RETRY_LMT_SSH_RETRY_
AR5K_NODCU_RETRY_LMT_SSH_RETRY_
AR5K_NOQCU_TXDP0	Queue 0 - data
AR5K_NOQCU_TXDP0	Queue 0 - data
AR5K_NOQCU_TXDP1	Queue 1 - beacons
AR5K_NOQCU_TXDP1	Queue 1 - beacons
AR5K_NUM_GPIO
AR5K_NUM_GPIO
AR5K_OFDM_FIL_CNT
AR5K_OFDM_FIL_CNT
AR5K_PCICFG	Register Address
AR5K_PCICFG	Register Address
AR5K_PCICFG_BUS_SEL	Mask for "bus select" [5211+] (?)
AR5K_PCICFG_BUS_SEL	Mask for "bus select" [5211+] (?)
AR5K_PCICFG_CBEFIX_DIS	Disable CBE fix
AR5K_PCICFG_CBEFIX_DIS	Disable CBE fix
AR5K_PCICFG_CLKRUNEN	CLKRUN enable [5211+]
AR5K_PCICFG_CLKRUNEN	CLKRUN enable [5211+]
AR5K_PCICFG_EEAE	Eeprom access enable [5210]
AR5K_PCICFG_EEAE	Eeprom access enable [5210]
AR5K_PCICFG_EESIZE	Mask for EEPROM size [5211+]
AR5K_PCICFG_EESIZE	Mask for EEPROM size [5211+]
AR5K_PCICFG_EESIZE_16K	16K
AR5K_PCICFG_EESIZE_16K	16K
AR5K_PCICFG_EESIZE_4K	4K
AR5K_PCICFG_EESIZE_4K	4K
AR5K_PCICFG_EESIZE_8K	8K
AR5K_PCICFG_EESIZE_8K	8K
AR5K_PCICFG_EESIZE_FAIL	Failed to get size [5211+]
AR5K_PCICFG_EESIZE_FAIL	Failed to get size [5211+]
AR5K_PCICFG_EESIZE_S
AR5K_PCICFG_EESIZE_S
AR5K_PCICFG_LED	Led status [5211+]
AR5K_PCICFG_LED	Led status [5211+]
AR5K_PCICFG_LED_ASSOC	Associated
AR5K_PCICFG_LED_ASSOC	Associated
AR5K_PCICFG_LED_BCTL	Led blink (?) [5210]
AR5K_PCICFG_LED_BCTL	Led blink (?) [5210]
AR5K_PCICFG_LED_NONE	Default [5211+]
AR5K_PCICFG_LED_NONE	Default [5211+]
AR5K_PCICFG_LED_PEND	Scan / Auth pending
AR5K_PCICFG_LED_PEND	Scan / Auth pending
AR5K_PCICFG_LEDBLINK	Led blink rate
AR5K_PCICFG_LEDBLINK	Led blink rate
AR5K_PCICFG_LEDBLINK_S
AR5K_PCICFG_LEDBLINK_S
AR5K_PCICFG_LEDMODE	Ledmode [5211+]
AR5K_PCICFG_LEDMODE	Ledmode [5211+]
AR5K_PCICFG_LEDMODE_PROM	Default mode (blink on any traffic) [5211+]
AR5K_PCICFG_LEDMODE_PROM	Default mode (blink on any traffic) [5211+]
AR5K_PCICFG_LEDMODE_PROP	Blink on standard traffic [5211+]
AR5K_PCICFG_LEDMODE_PROP	Blink on standard traffic [5211+]
AR5K_PCICFG_LEDMODE_PWR	Some other blinking mode (?) [5211+]
AR5K_PCICFG_LEDMODE_PWR	Some other blinking mode (?) [5211+]
AR5K_PCICFG_LEDMODE_RAND	Random blinking (?) [5211+]
AR5K_PCICFG_LEDMODE_RAND	Random blinking (?) [5211+]
AR5K_PCICFG_LEDSLOW	Slowest led blink rate [5211+]
AR5K_PCICFG_LEDSLOW	Slowest led blink rate [5211+]
AR5K_PCICFG_LEDSTATE
AR5K_PCICFG_LEDSTATE
AR5K_PCICFG_RETRY_FIX	Enable pci core retry fix
AR5K_PCICFG_RETRY_FIX	Enable pci core retry fix
AR5K_PCICFG_SL_INPEN	Sleep even whith pending interrupts
AR5K_PCICFG_SL_INPEN	Sleep even whith pending interrupts
AR5K_PCICFG_SL_INTEN	Enable interrupts when asleep
AR5K_PCICFG_SL_INTEN	Enable interrupts when asleep
AR5K_PCICFG_SLEEP_CLOCK_EN	Enable sleep clock
AR5K_PCICFG_SLEEP_CLOCK_EN	Enable sleep clock
AR5K_PCICFG_SLEEP_CLOCK_RATE	Sleep clock rate
AR5K_PCICFG_SLEEP_CLOCK_RATE	Sleep clock rate
AR5K_PCICFG_SLEEP_CLOCK_RATE_S
AR5K_PCICFG_SLEEP_CLOCK_RATE_S
AR5K_PCICFG_SPWR_DN	Mask for power status
AR5K_PCICFG_SPWR_DN	Mask for power status
AR5K_PCIE_PM_CTL	Register address
AR5K_PCIE_PM_CTL	Register address
AR5K_PCIE_PM_CTL_AUX_PWR_DET	Aux power detect
AR5K_PCIE_PM_CTL_AUX_PWR_DET	Aux power detect
AR5K_PCIE_PM_CTL_L0_L0S_CLEAR	Clear L0 and L0S counters
AR5K_PCIE_PM_CTL_L0_L0S_CLEAR	Clear L0 and L0S counters
AR5K_PCIE_PM_CTL_L0_L0S_EN	Start L0 nd L0S counters
AR5K_PCIE_PM_CTL_L0_L0S_EN	Start L0 nd L0S counters
AR5K_PCIE_PM_CTL_L1_WHEN_D2	enable PCIe core enter L1
AR5K_PCIE_PM_CTL_L1_WHEN_D2	enable PCIe core enter L1
AR5K_PCIE_PM_CTL_LDRESET_EN	Enable reset when link goes
AR5K_PCIE_PM_CTL_LDRESET_EN	Enable reset when link goes
AR5K_PCIE_PM_CTL_PME_CLEAR	Clear PME
AR5K_PCIE_PM_CTL_PME_CLEAR	Clear PME
AR5K_PCIE_PM_CTL_PME_EN	PME Enable
AR5K_PCIE_PM_CTL_PME_EN	PME Enable
AR5K_PCIE_PM_CTL_PSM_D0
AR5K_PCIE_PM_CTL_PSM_D0
AR5K_PCIE_PM_CTL_PSM_D1
AR5K_PCIE_PM_CTL_PSM_D1
AR5K_PCIE_PM_CTL_PSM_D2
AR5K_PCIE_PM_CTL_PSM_D2
AR5K_PCIE_PM_CTL_PSM_D3
AR5K_PCIE_PM_CTL_PSM_D3
AR5K_PCIE_SERDES
AR5K_PCIE_SERDES
AR5K_PCIE_SERDES_RESET
AR5K_PCIE_SERDES_RESET
AR5K_PCIE_WAEN
AR5K_PCIE_WAEN
AR5K_PCU_MAX
AR5K_PCU_MAX
AR5K_PCU_MIN
AR5K_PCU_MIN
AR5K_PHY(_n)
AR5K_PHY(_n)
AR5K_PHY_ACT	Register Address
AR5K_PHY_ACT	Register Address
AR5K_PHY_ACT_DISABLE	Deactivate PHY
AR5K_PHY_ACT_DISABLE	Deactivate PHY
AR5K_PHY_ACT_ENABLE	Activate PHY
AR5K_PHY_ACT_ENABLE	Activate PHY
AR5K_PHY_ADC_CTL
AR5K_PHY_ADC_CTL
AR5K_PHY_ADC_CTL_INBUFGAIN_OFF
AR5K_PHY_ADC_CTL_INBUFGAIN_OFF
AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_
AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_
AR5K_PHY_ADC_CTL_INBUFGAIN_ON
AR5K_PHY_ADC_CTL_INBUFGAIN_ON
AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S
AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S
AR5K_PHY_ADC_CTL_PWD_ADC_OFF
AR5K_PHY_ADC_CTL_PWD_ADC_OFF
AR5K_PHY_ADC_CTL_PWD_BAND_GAP_O
AR5K_PHY_ADC_CTL_PWD_BAND_GAP_O
AR5K_PHY_ADC_CTL_PWD_DAC_OFF
AR5K_PHY_ADC_CTL_PWD_DAC_OFF
AR5K_PHY_ADC_TEST
AR5K_PHY_ADC_TEST
AR5K_PHY_ADC_TEST_I
AR5K_PHY_ADC_TEST_I
AR5K_PHY_ADC_TEST_Q
AR5K_PHY_ADC_TEST_Q
AR5K_PHY_ADCSAT
AR5K_PHY_ADCSAT
AR5K_PHY_ADCSAT_ICNT
AR5K_PHY_ADCSAT_ICNT
AR5K_PHY_ADCSAT_ICNT_S
AR5K_PHY_ADCSAT_ICNT_S
AR5K_PHY_ADCSAT_THR
AR5K_PHY_ADCSAT_THR
AR5K_PHY_ADCSAT_THR_S
AR5K_PHY_ADCSAT_THR_S
AR5K_PHY_AGC	Register Address
AR5K_PHY_AGC	Register Address
AR5K_PHY_AGC_DISABLE	Disable AGC to A2 (?)
AR5K_PHY_AGC_DISABLE	Disable AGC to A2 (?)
AR5K_PHY_AGCCOARSE	Register Address
AR5K_PHY_AGCCOARSE	Register Address
AR5K_PHY_AGCCOARSE_HI	AGC Coarse high
AR5K_PHY_AGCCOARSE_HI	AGC Coarse high
AR5K_PHY_AGCCOARSE_HI_S
AR5K_PHY_AGCCOARSE_HI_S
AR5K_PHY_AGCCOARSE_LO	AGC Coarse low
AR5K_PHY_AGCCOARSE_LO	AGC Coarse low
AR5K_PHY_AGCCOARSE_LO_S
AR5K_PHY_AGCCOARSE_LO_S
AR5K_PHY_AGCCTL	Register address
AR5K_PHY_AGCCTL	Register address
AR5K_PHY_AGCCTL_CAL	Enable PHY calibration
AR5K_PHY_AGCCTL_CAL	Enable PHY calibration
AR5K_PHY_AGCCTL_NF	Enable Noise Floor calibration
AR5K_PHY_AGCCTL_NF	Enable Noise Floor calibration
AR5K_PHY_AGCCTL_NF_EN	Enable nf calibration to happen (?)
AR5K_PHY_AGCCTL_NF_EN	Enable nf calibration to happen (?)
AR5K_PHY_AGCCTL_NF_NOUPDATE	Don't update nf automaticaly
AR5K_PHY_AGCCTL_NF_NOUPDATE	Don't update nf automaticaly
AR5K_PHY_ANT_CTL	Register Address
AR5K_PHY_ANT_CTL	Register Address
AR5K_PHY_ANT_CTL_HITUNE5	Hitune5 (?)
AR5K_PHY_ANT_CTL_HITUNE5	Hitune5 (?)
AR5K_PHY_ANT_CTL_SECTORED_ANT	Sectored Antenna
AR5K_PHY_ANT_CTL_SECTORED_ANT	Sectored Antenna
AR5K_PHY_ANT_CTL_SWTABLE_IDLE	Switch table idle (?)
AR5K_PHY_ANT_CTL_SWTABLE_IDLE	Switch table idle (?)
AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S
AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S
AR5K_PHY_ANT_CTL_TXRX_EN	Enable TX/RX (?)
AR5K_PHY_ANT_CTL_TXRX_EN	Enable TX/RX (?)
AR5K_PHY_ANT_SWITCH_TABLE_0
AR5K_PHY_ANT_SWITCH_TABLE_0
AR5K_PHY_ANT_SWITCH_TABLE_1
AR5K_PHY_ANT_SWITCH_TABLE_1
AR5K_PHY_BAD_TX_RATE
AR5K_PHY_BAD_TX_RATE
AR5K_PHY_BASE
AR5K_PHY_BASE
AR5K_PHY_BIN_MASK_1
AR5K_PHY_BIN_MASK_1
AR5K_PHY_BIN_MASK_2
AR5K_PHY_BIN_MASK_2
AR5K_PHY_BIN_MASK_3
AR5K_PHY_BIN_MASK_3
AR5K_PHY_BIN_MASK_CTL
AR5K_PHY_BIN_MASK_CTL
AR5K_PHY_BIN_MASK_CTL_MASK_4
AR5K_PHY_BIN_MASK_CTL_MASK_4
AR5K_PHY_BIN_MASK_CTL_MASK_4_S
AR5K_PHY_BIN_MASK_CTL_MASK_4_S
AR5K_PHY_BIN_MASK_CTL_RATE
AR5K_PHY_BIN_MASK_CTL_RATE
AR5K_PHY_BIN_MASK_CTL_RATE_S
AR5K_PHY_BIN_MASK_CTL_RATE_S
AR5K_PHY_BIN_MASK2_1
AR5K_PHY_BIN_MASK2_1
AR5K_PHY_BIN_MASK2_2
AR5K_PHY_BIN_MASK2_2
AR5K_PHY_BIN_MASK2_3
AR5K_PHY_BIN_MASK2_3
AR5K_PHY_BIN_MASK2_4
AR5K_PHY_BIN_MASK2_4
AR5K_PHY_BIN_MASK2_4_MASK_4
AR5K_PHY_BIN_MASK2_4_MASK_4
AR5K_PHY_BIN_MASK2_4_MASK_4_S
AR5K_PHY_BIN_MASK2_4_MASK_4_S
AR5K_PHY_BLUETOOTH
AR5K_PHY_BLUETOOTH
AR5K_PHY_CCK_CROSSCORR
AR5K_PHY_CCK_CROSSCORR
AR5K_PHY_CCK_CROSSCORR_WEAK_SIG
AR5K_PHY_CCK_CROSSCORR_WEAK_SIG
AR5K_PHY_CCK_CROSSCORR_WEAK_SIG
AR5K_PHY_CCK_CROSSCORR_WEAK_SIG
AR5K_PHY_CCK_RX_CTL_4
AR5K_PHY_CCK_RX_CTL_4
AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_
AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_
AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_
AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_
AR5K_PHY_CCKTXCTK_DAC_SCALE
AR5K_PHY_CCKTXCTK_DAC_SCALE
AR5K_PHY_CCKTXCTL
AR5K_PHY_CCKTXCTL
AR5K_PHY_CCKTXCTL_JAPAN
AR5K_PHY_CCKTXCTL_JAPAN
AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS
AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS
AR5K_PHY_CCKTXCTL_WORLD
AR5K_PHY_CCKTXCTL_WORLD
AR5K_PHY_CHAN_STATUS
AR5K_PHY_CHAN_STATUS
AR5K_PHY_CHAN_STATUS_BT_ACT
AR5K_PHY_CHAN_STATUS_BT_ACT
AR5K_PHY_CHAN_STATUS_RX_CLR_MAC
AR5K_PHY_CHAN_STATUS_RX_CLR_MAC
AR5K_PHY_CHAN_STATUS_RX_CLR_PAP
AR5K_PHY_CHAN_STATUS_RX_CLR_PAP
AR5K_PHY_CHAN_STATUS_RX_CLR_RAW
AR5K_PHY_CHAN_STATUS_RX_CLR_RAW
AR5K_PHY_CHIP_ID
AR5K_PHY_CHIP_ID
AR5K_PHY_CTL	Register Address
AR5K_PHY_CTL	Register Address
AR5K_PHY_CTL_GEN_SCRAMBLER	Generate scrambler
AR5K_PHY_CTL_GEN_SCRAMBLER	Generate scrambler
AR5K_PHY_CTL_LATE_TX_SIG_SYM	Late tx signal symbol (?)
AR5K_PHY_CTL_LATE_TX_SIG_SYM	Late tx signal symbol (?)
AR5K_PHY_CTL_LOW_FREQ_SLE_EN	Enable low freq sleep
AR5K_PHY_CTL_LOW_FREQ_SLE_EN	Enable low freq sleep
AR5K_PHY_CTL_RX_ANT_SEL	RX antenna select
AR5K_PHY_CTL_RX_ANT_SEL	RX antenna select
AR5K_PHY_CTL_RX_ANT_STATIC	Static RX antenna
AR5K_PHY_CTL_RX_ANT_STATIC	Static RX antenna
AR5K_PHY_CTL_RX_DRAIN_RATE	RX drain rate (?)
AR5K_PHY_CTL_RX_DRAIN_RATE	RX drain rate (?)
AR5K_PHY_CTL_TX_ANT_SEL	TX antenna select
AR5K_PHY_CTL_TX_ANT_SEL	TX antenna select
AR5K_PHY_CTL_TX_ANT_STATIC	Static TX antenna
AR5K_PHY_CTL_TX_ANT_STATIC	Static TX antenna
AR5K_PHY_CURRENT_RSSI
AR5K_PHY_CURRENT_RSSI
AR5K_PHY_DAC_TEST
AR5K_PHY_DAC_TEST
AR5K_PHY_DAC_TEST_I
AR5K_PHY_DAC_TEST_I
AR5K_PHY_DAC_TEST_Q
AR5K_PHY_DAC_TEST_Q
AR5K_PHY_DAG_CCK_CTL
AR5K_PHY_DAG_CCK_CTL
AR5K_PHY_DAG_CCK_CTL_EN_RSSI_TH
AR5K_PHY_DAG_CCK_CTL_EN_RSSI_TH
AR5K_PHY_DAG_CCK_CTL_RSSI_THR
AR5K_PHY_DAG_CCK_CTL_RSSI_THR
AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S
AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S
AR5K_PHY_DESIRED_SIZE	Register Address
AR5K_PHY_DESIRED_SIZE	Register Address
AR5K_PHY_DESIRED_SIZE_ADC	ADC desired size
AR5K_PHY_DESIRED_SIZE_ADC	ADC desired size
AR5K_PHY_DESIRED_SIZE_ADC_S
AR5K_PHY_DESIRED_SIZE_ADC_S
AR5K_PHY_DESIRED_SIZE_PGA	PGA desired size
AR5K_PHY_DESIRED_SIZE_PGA	PGA desired size
AR5K_PHY_DESIRED_SIZE_PGA_S
AR5K_PHY_DESIRED_SIZE_PGA_S
AR5K_PHY_DESIRED_SIZE_TOT	Total desired size
AR5K_PHY_DESIRED_SIZE_TOT	Total desired size
AR5K_PHY_DESIRED_SIZE_TOT_S
AR5K_PHY_DESIRED_SIZE_TOT_S
AR5K_PHY_ERR_FIL
AR5K_PHY_ERR_FIL
AR5K_PHY_ERR_FIL_CCK	CCK false detect (ANI)
AR5K_PHY_ERR_FIL_CCK	CCK false detect (ANI)
AR5K_PHY_ERR_FIL_OFDM	OFDM false detect (ANI)
AR5K_PHY_ERR_FIL_OFDM	OFDM false detect (ANI)
AR5K_PHY_ERR_FIL_RADAR	Radar signal
AR5K_PHY_ERR_FIL_RADAR	Radar signal
AR5K_PHY_FAST_ADC
AR5K_PHY_FAST_ADC
AR5K_PHY_FAST_ANT_DIV
AR5K_PHY_FAST_ANT_DIV
AR5K_PHY_FAST_ANT_DIV_EN
AR5K_PHY_FAST_ANT_DIV_EN
AR5K_PHY_FRAME_CTL
AR5K_PHY_FRAME_CTL
AR5K_PHY_FRAME_CTL_5210
AR5K_PHY_FRAME_CTL_5210
AR5K_PHY_FRAME_CTL_5211
AR5K_PHY_FRAME_CTL_5211
AR5K_PHY_FRAME_CTL_EMU
AR5K_PHY_FRAME_CTL_EMU
AR5K_PHY_FRAME_CTL_EMU_S
AR5K_PHY_FRAME_CTL_EMU_S
AR5K_PHY_FRAME_CTL_ILLLEN_ERR	Illegal length
AR5K_PHY_FRAME_CTL_ILLLEN_ERR	Illegal length
AR5K_PHY_FRAME_CTL_ILLRATE_ERR	Illegal rate
AR5K_PHY_FRAME_CTL_ILLRATE_ERR	Illegal rate
AR5K_PHY_FRAME_CTL_INI
AR5K_PHY_FRAME_CTL_INI
AR5K_PHY_FRAME_CTL_PARITY_ERR	Parity error
AR5K_PHY_FRAME_CTL_PARITY_ERR	Parity error
AR5K_PHY_FRAME_CTL_PREP_CHINFO	Prepend chan info
AR5K_PHY_FRAME_CTL_PREP_CHINFO	Prepend chan info
AR5K_PHY_FRAME_CTL_SERVICE_ERR
AR5K_PHY_FRAME_CTL_SERVICE_ERR
AR5K_PHY_FRAME_CTL_TIMING_ERR	PHY timing error
AR5K_PHY_FRAME_CTL_TIMING_ERR	PHY timing error
AR5K_PHY_FRAME_CTL_TX_CLIP	Mask for tx clip (?)
AR5K_PHY_FRAME_CTL_TX_CLIP	Mask for tx clip (?)
AR5K_PHY_FRAME_CTL_TX_CLIP_S
AR5K_PHY_FRAME_CTL_TX_CLIP_S
AR5K_PHY_FRAME_CTL_TXURN_ERR	TX underrun
AR5K_PHY_FRAME_CTL_TXURN_ERR	TX underrun
AR5K_PHY_GAIN	Register Address
AR5K_PHY_GAIN	Register Address
AR5K_PHY_GAIN_2GHZ
AR5K_PHY_GAIN_2GHZ
AR5K_PHY_GAIN_2GHZ_INI_5111
AR5K_PHY_GAIN_2GHZ_INI_5111
AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX
AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX
AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_
AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_
AR5K_PHY_GAIN_OFFSET	Register Address
AR5K_PHY_GAIN_OFFSET	Register Address
AR5K_PHY_GAIN_OFFSET_RXTX_FLAG	RX-TX flag (?)
AR5K_PHY_GAIN_OFFSET_RXTX_FLAG	RX-TX flag (?)
AR5K_PHY_GAIN_TXRX_ATTEN	TX-RX Attenuation
AR5K_PHY_GAIN_TXRX_ATTEN	TX-RX Attenuation
AR5K_PHY_GAIN_TXRX_ATTEN_S
AR5K_PHY_GAIN_TXRX_ATTEN_S
AR5K_PHY_GAIN_TXRX_RF_MAX
AR5K_PHY_GAIN_TXRX_RF_MAX
AR5K_PHY_GAIN_TXRX_RF_MAX_S
AR5K_PHY_GAIN_TXRX_RF_MAX_S
AR5K_PHY_HEAVY_CLIP_ENABLE
AR5K_PHY_HEAVY_CLIP_ENABLE
AR5K_PHY_IQ	Register Address
AR5K_PHY_IQ	Register Address
AR5K_PHY_IQ_CAL_NUM_LOG_MAX	Mask for max number of samples in log scale
AR5K_PHY_IQ_CAL_NUM_LOG_MAX	Mask for max number of samples in log scale
AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S
AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S
AR5K_PHY_IQ_CHAN_MASK_EN	Enable channel mask (?)
AR5K_PHY_IQ_CHAN_MASK_EN	Enable channel mask (?)
AR5K_PHY_IQ_CORR_ENABLE	Enable i/q correction
AR5K_PHY_IQ_CORR_ENABLE	Enable i/q correction
AR5K_PHY_IQ_CORR_Q_I_COFF	Mask for i correction info
AR5K_PHY_IQ_CORR_Q_I_COFF	Mask for i correction info
AR5K_PHY_IQ_CORR_Q_I_COFF_S
AR5K_PHY_IQ_CORR_Q_I_COFF_S
AR5K_PHY_IQ_CORR_Q_Q_COFF	Mask for q correction info
AR5K_PHY_IQ_CORR_Q_Q_COFF	Mask for q correction info
AR5K_PHY_IQ_EARLY_TRIG_THR	Early trigger threshold (?) (field)
AR5K_PHY_IQ_EARLY_TRIG_THR	Early trigger threshold (?) (field)
AR5K_PHY_IQ_PILOT_MASK_EN	Enable pilot mask (?)
AR5K_PHY_IQ_PILOT_MASK_EN	Enable pilot mask (?)
AR5K_PHY_IQ_RUN	Run i/q calibration
AR5K_PHY_IQ_RUN	Run i/q calibration
AR5K_PHY_IQ_SPUR_FILT_EN	Enable spur filter
AR5K_PHY_IQ_SPUR_FILT_EN	Enable spur filter
AR5K_PHY_IQ_SPUR_RSSI_EN	Enable spur rssi
AR5K_PHY_IQ_SPUR_RSSI_EN	Enable spur rssi
AR5K_PHY_IQ_USE_PT_DF	Use pilot track df (?)
AR5K_PHY_IQ_USE_PT_DF	Use pilot track df (?)
AR5K_PHY_IQRES_CAL_CORR	I/Q Correlation
AR5K_PHY_IQRES_CAL_CORR	I/Q Correlation
AR5K_PHY_IQRES_CAL_PWR_I	I (Inphase) power value
AR5K_PHY_IQRES_CAL_PWR_I	I (Inphase) power value
AR5K_PHY_IQRES_CAL_PWR_Q	Q (Quadrature) power value
AR5K_PHY_IQRES_CAL_PWR_Q	Q (Quadrature) power value
AR5K_PHY_MAX_RX_LEN
AR5K_PHY_MAX_RX_LEN
AR5K_PHY_MODE	Register Address
AR5K_PHY_MODE	Register Address
AR5K_PHY_MODE_FREQ	Freq mode bit
AR5K_PHY_MODE_FREQ	Freq mode bit
AR5K_PHY_MODE_FREQ_2GHZ
AR5K_PHY_MODE_FREQ_2GHZ
AR5K_PHY_MODE_FREQ_5GHZ
AR5K_PHY_MODE_FREQ_5GHZ
AR5K_PHY_MODE_HALF_RATE	Enable Half rate (test)
AR5K_PHY_MODE_HALF_RATE	Enable Half rate (test)
AR5K_PHY_MODE_MOD	PHY Modulation bit
AR5K_PHY_MODE_MOD	PHY Modulation bit
AR5K_PHY_MODE_MOD_CCK
AR5K_PHY_MODE_MOD_CCK
AR5K_PHY_MODE_MOD_DYN	Enable Dynamic OFDM/CCK mode [5112+]
AR5K_PHY_MODE_MOD_DYN	Enable Dynamic OFDM/CCK mode [5112+]
AR5K_PHY_MODE_MOD_OFDM
AR5K_PHY_MODE_MOD_OFDM
AR5K_PHY_MODE_QUARTER_RATE	Enable Quarter rat (test)
AR5K_PHY_MODE_QUARTER_RATE	Enable Quarter rat (test)
AR5K_PHY_MODE_RAD	[5212+]
AR5K_PHY_MODE_RAD	[5212+]
AR5K_PHY_MODE_RAD_RF5111
AR5K_PHY_MODE_RAD_RF5111
AR5K_PHY_MODE_RAD_RF5112
AR5K_PHY_MODE_RAD_RF5112
AR5K_PHY_MODE_XR	Enable XR mode [5112+]
AR5K_PHY_MODE_XR	Enable XR mode [5112+]
AR5K_PHY_NF	Register address
AR5K_PHY_NF	Register address
AR5K_PHY_NF_ACTIVE	Noise floor calibration still active
AR5K_PHY_NF_ACTIVE	Noise floor calibration still active
AR5K_PHY_NF_AVAL(_n)
AR5K_PHY_NF_AVAL(_n)
AR5K_PHY_NF_M	Noise floor mask
AR5K_PHY_NF_M	Noise floor mask
AR5K_PHY_NF_MINCCA_PWR	???
AR5K_PHY_NF_MINCCA_PWR	???
AR5K_PHY_NF_MINCCA_PWR_S
AR5K_PHY_NF_MINCCA_PWR_S
AR5K_PHY_NF_RVAL(_n)
AR5K_PHY_NF_RVAL(_n)
AR5K_PHY_NF_SVAL(_n)
AR5K_PHY_NF_SVAL(_n)
AR5K_PHY_NF_THRESH62	Thresh62 -check ANI patent- (field)
AR5K_PHY_NF_THRESH62	Thresh62 -check ANI patent- (field)
AR5K_PHY_NF_THRESH62_S
AR5K_PHY_NF_THRESH62_S
AR5K_PHY_NFTHRES
AR5K_PHY_NFTHRES
AR5K_PHY_OFDM_SELFCORR	Register Address
AR5K_PHY_OFDM_SELFCORR	Register Address
AR5K_PHY_OFDM_SELFCORR_CYPWR_TH	Enable cyclic RSSI thr 1
AR5K_PHY_OFDM_SELFCORR_CYPWR_TH	Mask for Cyclic RSSI threshold 1
AR5K_PHY_OFDM_SELFCORR_CYPWR_TH
AR5K_PHY_OFDM_SELFCORR_CYPWR_TH	Cyclic RSSI threshold 3 (field) (?)
AR5K_PHY_OFDM_SELFCORR_CYPWR_TH	Enable cyclic RSSI thr 1
AR5K_PHY_OFDM_SELFCORR_CYPWR_TH	Mask for Cyclic RSSI threshold 1
AR5K_PHY_OFDM_SELFCORR_CYPWR_TH
AR5K_PHY_OFDM_SELFCORR_CYPWR_TH	Cyclic RSSI threshold 3 (field) (?)
AR5K_PHY_OFDM_SELFCORR_LSCTHR_H	Long sc threshold hi rssi (?)
AR5K_PHY_OFDM_SELFCORR_LSCTHR_H	Long sc threshold hi rssi (?)
AR5K_PHY_OFDM_SELFCORR_RSSI_1AT	Enable 1A RSSI threshold (?)
AR5K_PHY_OFDM_SELFCORR_RSSI_1AT	1A RSSI threshold (field) (?)
AR5K_PHY_OFDM_SELFCORR_RSSI_1AT	Enable 1A RSSI threshold (?)
AR5K_PHY_OFDM_SELFCORR_RSSI_1AT	1A RSSI threshold (field) (?)
AR5K_PHY_PA_CTL	Register Address
AR5K_PHY_PA_CTL	Register Address
AR5K_PHY_PA_CTL_XPA_A_EN	Enable XPA A
AR5K_PHY_PA_CTL_XPA_A_EN	Enable XPA A
AR5K_PHY_PA_CTL_XPA_A_HI	XPA A high (?)
AR5K_PHY_PA_CTL_XPA_A_HI	XPA A high (?)
AR5K_PHY_PA_CTL_XPA_B_EN	Enable XPA B
AR5K_PHY_PA_CTL_XPA_B_EN	Enable XPA B
AR5K_PHY_PA_CTL_XPA_B_HI	XPA B high (?)
AR5K_PHY_PA_CTL_XPA_B_HI	XPA B high (?)
AR5K_PHY_PAPD_I(_n)
AR5K_PHY_PAPD_I(_n)
AR5K_PHY_PAPD_I_BASE
AR5K_PHY_PAPD_I_BASE
AR5K_PHY_PAPD_PROBE
AR5K_PHY_PAPD_PROBE
AR5K_PHY_PAPD_PROBE_COMP_GAIN
AR5K_PHY_PAPD_PROBE_COMP_GAIN
AR5K_PHY_PAPD_PROBE_GAINF
AR5K_PHY_PAPD_PROBE_GAINF
AR5K_PHY_PAPD_PROBE_GAINF_S
AR5K_PHY_PAPD_PROBE_GAINF_S
AR5K_PHY_PAPD_PROBE_INI_5111	[5212+]
AR5K_PHY_PAPD_PROBE_INI_5111	[5212+]
AR5K_PHY_PAPD_PROBE_INI_5112	[5212+]
AR5K_PHY_PAPD_PROBE_INI_5112	[5212+]
AR5K_PHY_PAPD_PROBE_PCDAC_BIAS
AR5K_PHY_PAPD_PROBE_PCDAC_BIAS
AR5K_PHY_PAPD_PROBE_PREDIST_EN
AR5K_PHY_PAPD_PROBE_PREDIST_EN
AR5K_PHY_PAPD_PROBE_SH_HI_PAR
AR5K_PHY_PAPD_PROBE_SH_HI_PAR
AR5K_PHY_PAPD_PROBE_TX_NEXT
AR5K_PHY_PAPD_PROBE_TX_NEXT
AR5K_PHY_PAPD_PROBE_TXPOWER
AR5K_PHY_PAPD_PROBE_TXPOWER
AR5K_PHY_PAPD_PROBE_TXPOWER_S
AR5K_PHY_PAPD_PROBE_TXPOWER_S
AR5K_PHY_PAPD_PROBE_TYPE	[5112+]
AR5K_PHY_PAPD_PROBE_TYPE	[5112+]
AR5K_PHY_PAPD_PROBE_TYPE_CCK
AR5K_PHY_PAPD_PROBE_TYPE_CCK
AR5K_PHY_PAPD_PROBE_TYPE_OFDM
AR5K_PHY_PAPD_PROBE_TYPE_OFDM
AR5K_PHY_PAPD_PROBE_TYPE_S
AR5K_PHY_PAPD_PROBE_TYPE_S
AR5K_PHY_PAPD_PROBE_TYPE_XR
AR5K_PHY_PAPD_PROBE_TYPE_XR
AR5K_PHY_PCDAC_TXPOWER(_n)
AR5K_PHY_PCDAC_TXPOWER(_n)
AR5K_PHY_PCDAC_TXPOWER_BASE
AR5K_PHY_PCDAC_TXPOWER_BASE
AR5K_PHY_PDADC_TXPOWER(_n)
AR5K_PHY_PDADC_TXPOWER(_n)
AR5K_PHY_PDADC_TXPOWER_BASE
AR5K_PHY_PDADC_TXPOWER_BASE
AR5K_PHY_PLL
AR5K_PHY_PLL
AR5K_PHY_PLL_20MHZ	For half rate (?)
AR5K_PHY_PLL_20MHZ	For half rate (?)
AR5K_PHY_PLL_40MHZ
AR5K_PHY_PLL_40MHZ
AR5K_PHY_PLL_40MHZ_5211
AR5K_PHY_PLL_40MHZ_5211
AR5K_PHY_PLL_40MHZ_5212
AR5K_PHY_PLL_40MHZ_5212
AR5K_PHY_PLL_40MHZ_5413
AR5K_PHY_PLL_40MHZ_5413
AR5K_PHY_PLL_44MHZ
AR5K_PHY_PLL_44MHZ
AR5K_PHY_PLL_44MHZ_5211
AR5K_PHY_PLL_44MHZ_5211
AR5K_PHY_PLL_44MHZ_5212
AR5K_PHY_PLL_44MHZ_5212
AR5K_PHY_PLL_HALF_RATE
AR5K_PHY_PLL_HALF_RATE
AR5K_PHY_PLL_QUARTER_RATE
AR5K_PHY_PLL_QUARTER_RATE
AR5K_PHY_PLL_RF5111
AR5K_PHY_PLL_RF5111
AR5K_PHY_PLL_RF5112
AR5K_PHY_PLL_RF5112
AR5K_PHY_PTAT
AR5K_PHY_PTAT
AR5K_PHY_RADAR
AR5K_PHY_RADAR
AR5K_PHY_RADAR_DISABLE
AR5K_PHY_RADAR_DISABLE
AR5K_PHY_RADAR_ENABLE
AR5K_PHY_RADAR_ENABLE
AR5K_PHY_RADAR_FIRPWR_THR	Finite Impulse Response
AR5K_PHY_RADAR_FIRPWR_THR	Finite Impulse Response
AR5K_PHY_RADAR_FIRPWR_THRS
AR5K_PHY_RADAR_FIRPWR_THRS
AR5K_PHY_RADAR_INBANDTHR	Inband threshold
AR5K_PHY_RADAR_INBANDTHR	Inband threshold
AR5K_PHY_RADAR_INBANDTHR_S
AR5K_PHY_RADAR_INBANDTHR_S
AR5K_PHY_RADAR_PHEIGHT_THR	Pulse height threshold
AR5K_PHY_RADAR_PHEIGHT_THR	Pulse height threshold
AR5K_PHY_RADAR_PHEIGHT_THR_S
AR5K_PHY_RADAR_PHEIGHT_THR_S
AR5K_PHY_RADAR_PRSSI_THR	Pulse RSSI/SNR threshold
AR5K_PHY_RADAR_PRSSI_THR	Pulse RSSI/SNR threshold
AR5K_PHY_RADAR_PRSSI_THR_S
AR5K_PHY_RADAR_PRSSI_THR_S
AR5K_PHY_RADAR_RSSI_THR	Radar RSSI/SNR threshold.
AR5K_PHY_RADAR_RSSI_THR	Radar RSSI/SNR threshold.
AR5K_PHY_RADAR_RSSI_THR_S
AR5K_PHY_RADAR_RSSI_THR_S
AR5K_PHY_READ(ah, _reg)
AR5K_PHY_READ(ah, _reg)
AR5K_PHY_RESTART	restart
AR5K_PHY_RESTART	restart
AR5K_PHY_RESTART_DIV_GC	Fast diversity gc_limit (?)
AR5K_PHY_RESTART_DIV_GC	Fast diversity gc_limit (?)
AR5K_PHY_RESTART_DIV_GC_S
AR5K_PHY_RESTART_DIV_GC_S
AR5K_PHY_RF_CTL2	Register Address
AR5K_PHY_RF_CTL2	Register Address
AR5K_PHY_RF_CTL2_TXF2TXD_START	TX frame to TX data start
AR5K_PHY_RF_CTL2_TXF2TXD_START	TX frame to TX data start
AR5K_PHY_RF_CTL2_TXF2TXD_START_
AR5K_PHY_RF_CTL2_TXF2TXD_START_
AR5K_PHY_RF_CTL3	Register Address
AR5K_PHY_RF_CTL3	Register Address
AR5K_PHY_RF_CTL3_TXE2XLNA_ON	TX end to XLNA on
AR5K_PHY_RF_CTL3_TXE2XLNA_ON	TX end to XLNA on
AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S
AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S
AR5K_PHY_RF_CTL4	Register Address
AR5K_PHY_RF_CTL4	Register Address
AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF	TX end to XPA A off (field)
AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF	TX end to XPA A off (field)
AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF	TX end to XPA B off (field)
AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF	TX end to XPA B off (field)
AR5K_PHY_RF_CTL4_TXF2XPA_A_ON	TX frame to XPA A on (field)
AR5K_PHY_RF_CTL4_TXF2XPA_A_ON	TX frame to XPA A on (field)
AR5K_PHY_RF_CTL4_TXF2XPA_B_ON	TX frame to XPA B on (field)
AR5K_PHY_RF_CTL4_TXF2XPA_B_ON	TX frame to XPA B on (field)
AR5K_PHY_RFBUS_GRANT
AR5K_PHY_RFBUS_GRANT
AR5K_PHY_RFBUS_GRANT_OK
AR5K_PHY_RFBUS_GRANT_OK
AR5K_PHY_RFBUS_REQ
AR5K_PHY_RFBUS_REQ
AR5K_PHY_RFBUS_REQ_REQUEST
AR5K_PHY_RFBUS_REQ_REQUEST
AR5K_PHY_RFSTG
AR5K_PHY_RFSTG
AR5K_PHY_RFSTG_DISABLE
AR5K_PHY_RFSTG_DISABLE
AR5K_PHY_RX_DELAY	Register Address
AR5K_PHY_RX_DELAY	Register Address
AR5K_PHY_RX_DELAY_M	Mask for RX activate to receive delay (/100ns)
AR5K_PHY_RX_DELAY_M	Mask for RX activate to receive delay (/100ns)
AR5K_PHY_SCAL
AR5K_PHY_SCAL
AR5K_PHY_SCAL_32MHZ
AR5K_PHY_SCAL_32MHZ
AR5K_PHY_SCAL_32MHZ_2417
AR5K_PHY_SCAL_32MHZ_2417
AR5K_PHY_SCAL_32MHZ_HB63
AR5K_PHY_SCAL_32MHZ_HB63
AR5K_PHY_SCLOCK
AR5K_PHY_SCLOCK
AR5K_PHY_SCLOCK_32MHZ
AR5K_PHY_SCLOCK_32MHZ
AR5K_PHY_SCR
AR5K_PHY_SCR
AR5K_PHY_SDELAY
AR5K_PHY_SDELAY
AR5K_PHY_SDELAY_32MHZ
AR5K_PHY_SDELAY_32MHZ
AR5K_PHY_SETTLING	Register Address
AR5K_PHY_SETTLING	Register Address
AR5K_PHY_SETTLING_AGC	AGC settling time
AR5K_PHY_SETTLING_AGC	AGC settling time
AR5K_PHY_SETTLING_AGC_S
AR5K_PHY_SETTLING_AGC_S
AR5K_PHY_SETTLING_SWITCH	Switch settlig time
AR5K_PHY_SETTLING_SWITCH	Switch settlig time
AR5K_PHY_SETTLING_SWITCH_S
AR5K_PHY_SETTLING_SWITCH_S
AR5K_PHY_SHIFT_2GHZ	Used to access 2GHz radios
AR5K_PHY_SHIFT_2GHZ	Used to access 2GHz radios
AR5K_PHY_SHIFT_5GHZ	Used to access 5GHz radios (default)
AR5K_PHY_SHIFT_5GHZ	Used to access 5GHz radios (default)
AR5K_PHY_SIG	Register Address
AR5K_PHY_SIG	Register Address
AR5K_PHY_SIG_FIRPWR	FIPWR
AR5K_PHY_SIG_FIRPWR	FIPWR
AR5K_PHY_SIG_FIRPWR_S
AR5K_PHY_SIG_FIRPWR_S
AR5K_PHY_SIG_FIRSTEP	FIRSTEP
AR5K_PHY_SIG_FIRSTEP	FIRSTEP
AR5K_PHY_SIG_FIRSTEP_S
AR5K_PHY_SIG_FIRSTEP_S
AR5K_PHY_SIGMA_DELTA
AR5K_PHY_SIGMA_DELTA
AR5K_PHY_SIGMA_DELTA_ADC_CLIP
AR5K_PHY_SIGMA_DELTA_ADC_CLIP
AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S
AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S
AR5K_PHY_SIGMA_DELTA_ADC_SEL
AR5K_PHY_SIGMA_DELTA_ADC_SEL
AR5K_PHY_SIGMA_DELTA_ADC_SEL_S
AR5K_PHY_SIGMA_DELTA_ADC_SEL_S
AR5K_PHY_SIGMA_DELTA_FILT1
AR5K_PHY_SIGMA_DELTA_FILT1
AR5K_PHY_SIGMA_DELTA_FILT1_S
AR5K_PHY_SIGMA_DELTA_FILT1_S
AR5K_PHY_SIGMA_DELTA_FILT2
AR5K_PHY_SIGMA_DELTA_FILT2
AR5K_PHY_SIGMA_DELTA_FILT2_S
AR5K_PHY_SIGMA_DELTA_FILT2_S
AR5K_PHY_SLMT
AR5K_PHY_SLMT
AR5K_PHY_SLMT_32MHZ
AR5K_PHY_SLMT_32MHZ
AR5K_PHY_SPENDING
AR5K_PHY_SPENDING
AR5K_PHY_SPUR_PWR	Register Address
AR5K_PHY_SPUR_PWR	Register Address
AR5K_PHY_SPUR_PWR_FILT	Power with SPUR removed (field)
AR5K_PHY_SPUR_PWR_FILT	Power with SPUR removed (field)
AR5K_PHY_SPUR_PWR_I	SPUR Power estimate for I (field)
AR5K_PHY_SPUR_PWR_I	SPUR Power estimate for I (field)
AR5K_PHY_SPUR_PWR_Q	SPUR Power estimate for Q (field)
AR5K_PHY_SPUR_PWR_Q	SPUR Power estimate for Q (field)
AR5K_PHY_TIMING_10
AR5K_PHY_TIMING_10
AR5K_PHY_TIMING_10_PILOT_MASK_2
AR5K_PHY_TIMING_10_PILOT_MASK_2
AR5K_PHY_TIMING_10_PILOT_MASK_2
AR5K_PHY_TIMING_10_PILOT_MASK_2
AR5K_PHY_TIMING_11	Register address
AR5K_PHY_TIMING_11	Register address
AR5K_PHY_TIMING_11_SPUR_DELTA_P	Spur delta phase
AR5K_PHY_TIMING_11_SPUR_DELTA_P
AR5K_PHY_TIMING_11_SPUR_DELTA_P	Spur delta phase
AR5K_PHY_TIMING_11_SPUR_DELTA_P
AR5K_PHY_TIMING_11_SPUR_FREQ_SD	Freq sigma delta
AR5K_PHY_TIMING_11_SPUR_FREQ_SD
AR5K_PHY_TIMING_11_SPUR_FREQ_SD	Freq sigma delta
AR5K_PHY_TIMING_11_SPUR_FREQ_SD
AR5K_PHY_TIMING_11_USE_SPUR_IN_	Spur filter in AGC detector
AR5K_PHY_TIMING_11_USE_SPUR_IN_	Spur filter in OFDM self correlator
AR5K_PHY_TIMING_11_USE_SPUR_IN_	Spur filter in AGC detector
AR5K_PHY_TIMING_11_USE_SPUR_IN_	Spur filter in OFDM self correlator
AR5K_PHY_TIMING_3
AR5K_PHY_TIMING_3
AR5K_PHY_TIMING_3_DSC_EXP
AR5K_PHY_TIMING_3_DSC_EXP
AR5K_PHY_TIMING_3_DSC_EXP_S
AR5K_PHY_TIMING_3_DSC_EXP_S
AR5K_PHY_TIMING_3_DSC_MAN
AR5K_PHY_TIMING_3_DSC_MAN
AR5K_PHY_TIMING_3_DSC_MAN_S
AR5K_PHY_TIMING_3_DSC_MAN_S
AR5K_PHY_TIMING_7
AR5K_PHY_TIMING_7
AR5K_PHY_TIMING_8
AR5K_PHY_TIMING_8
AR5K_PHY_TIMING_8_PILOT_MASK_2
AR5K_PHY_TIMING_8_PILOT_MASK_2
AR5K_PHY_TIMING_8_PILOT_MASK_2_
AR5K_PHY_TIMING_8_PILOT_MASK_2_
AR5K_PHY_TIMING_9
AR5K_PHY_TIMING_9
AR5K_PHY_TPC_RG1
AR5K_PHY_TPC_RG1
AR5K_PHY_TPC_RG1_NUM_PD_GAIN
AR5K_PHY_TPC_RG1_NUM_PD_GAIN
AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S
AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S
AR5K_PHY_TPC_RG1_PDGAIN_1
AR5K_PHY_TPC_RG1_PDGAIN_1
AR5K_PHY_TPC_RG1_PDGAIN_1_S
AR5K_PHY_TPC_RG1_PDGAIN_1_S
AR5K_PHY_TPC_RG1_PDGAIN_2
AR5K_PHY_TPC_RG1_PDGAIN_2
AR5K_PHY_TPC_RG1_PDGAIN_2_S
AR5K_PHY_TPC_RG1_PDGAIN_2_S
AR5K_PHY_TPC_RG1_PDGAIN_3
AR5K_PHY_TPC_RG1_PDGAIN_3
AR5K_PHY_TPC_RG1_PDGAIN_3_S
AR5K_PHY_TPC_RG1_PDGAIN_3_S
AR5K_PHY_TPC_RG5
AR5K_PHY_TPC_RG5
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA
AR5K_PHY_TPC_RG5_PD_GAIN_OVERLA
AR5K_PHY_TPC_RG5_PD_GAIN_OVERLA
AR5K_PHY_TPC_RG5_PD_GAIN_OVERLA
AR5K_PHY_TPC_RG5_PD_GAIN_OVERLA
AR5K_PHY_TST1
AR5K_PHY_TST1
AR5K_PHY_TST1_TXHOLD	Set tx hold (?)
AR5K_PHY_TST1_TXHOLD	Set tx hold (?)
AR5K_PHY_TST1_TXSRC_ALT	Set input to tsdac (?)
AR5K_PHY_TST1_TXSRC_ALT	Set input to tsdac (?)
AR5K_PHY_TST1_TXSRC_ALT_S
AR5K_PHY_TST1_TXSRC_ALT_S
AR5K_PHY_TST1_TXSRC_SRC	Used with bit 7 (?)
AR5K_PHY_TST1_TXSRC_SRC	Used with bit 7 (?)
AR5K_PHY_TST1_TXSRC_SRC_S
AR5K_PHY_TST1_TXSRC_SRC_S
AR5K_PHY_TST2	Register Address
AR5K_PHY_TST2	Register Address
AR5K_PHY_TST2_ADC_OBS_SEL	ADC OBS Select (field ?)
AR5K_PHY_TST2_ADC_OBS_SEL	ADC OBS Select (field ?)
AR5K_PHY_TST2_AGC_OBS_SEL_3	AGC OBS Select 3 (?)
AR5K_PHY_TST2_AGC_OBS_SEL_3	AGC OBS Select 3 (?)
AR5K_PHY_TST2_ALT_RFDATA	Alternate RFDATA (5-2GHz switch ?)
AR5K_PHY_TST2_ALT_RFDATA	Alternate RFDATA (5-2GHz switch ?)
AR5K_PHY_TST2_BBB_OBS_SEL	BB OBS Select (field ?)
AR5K_PHY_TST2_BBB_OBS_SEL	BB OBS Select (field ?)
AR5K_PHY_TST2_CBUS_MODE	Cardbus mode (?)
AR5K_PHY_TST2_CBUS_MODE	Cardbus mode (?)
AR5K_PHY_TST2_CHANCOR_DUMP_EN	Enable Chancor dump (?)
AR5K_PHY_TST2_CHANCOR_DUMP_EN	Enable Chancor dump (?)
AR5K_PHY_TST2_CLK32	CLK_OUT is CLK32 (32Khz external)
AR5K_PHY_TST2_CLK32	CLK_OUT is CLK32 (32Khz external)
AR5K_PHY_TST2_EVEN_CHANCOR_DUMP	Even Chancor dump (?)
AR5K_PHY_TST2_EVEN_CHANCOR_DUMP	Even Chancor dump (?)
AR5K_PHY_TST2_FORCE_AGC_CLR	Force AGC clear (?)
AR5K_PHY_TST2_FORCE_AGC_CLR	Force AGC clear (?)
AR5K_PHY_TST2_MINI_OBS_EN	Enable mini OBS (?)
AR5K_PHY_TST2_MINI_OBS_EN	Enable mini OBS (?)
AR5K_PHY_TST2_RFSILENT_EN	Enable RFSILENT
AR5K_PHY_TST2_RFSILENT_EN	Enable RFSILENT
AR5K_PHY_TST2_RX_CLR_SEL	RX Clear Select (?)
AR5K_PHY_TST2_RX_CLR_SEL	RX Clear Select (?)
AR5K_PHY_TST2_RX2_IS_RX5_INV	2GHz rx path is the 5GHz path inverted (?)
AR5K_PHY_TST2_RX2_IS_RX5_INV	2GHz rx path is the 5GHz path inverted (?)
AR5K_PHY_TST2_SLOW_CLK160	Slow CLK160 (?)
AR5K_PHY_TST2_SLOW_CLK160	Slow CLK160 (?)
AR5K_PHY_TST2_TRIG	Trigger (?)
AR5K_PHY_TST2_TRIG	Trigger (?)
AR5K_PHY_TST2_TRIG_SEL	Trigger select (?)
AR5K_PHY_TST2_TRIG_SEL	Trigger select (?)
AR5K_PHY_TURBO	Register Address
AR5K_PHY_TURBO	Register Address
AR5K_PHY_TURBO_MIMO	Set turbo for mimo mimo
AR5K_PHY_TURBO_MIMO	Set turbo for mimo mimo
AR5K_PHY_TURBO_MODE	Enable turbo mode
AR5K_PHY_TURBO_MODE	Enable turbo mode
AR5K_PHY_TURBO_SHORT	Set short symbols to turbo mode
AR5K_PHY_TURBO_SHORT	Set short symbols to turbo mode
AR5K_PHY_TX_PWR_ADJ
AR5K_PHY_TX_PWR_ADJ
AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE
AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE
AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE
AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE
AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I
AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I
AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I
AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I
AR5K_PHY_TXPOWER_RATE_MAX
AR5K_PHY_TXPOWER_RATE_MAX
AR5K_PHY_TXPOWER_RATE_MAX_TPC_E
AR5K_PHY_TXPOWER_RATE_MAX_TPC_E
AR5K_PHY_TXPOWER_RATE1
AR5K_PHY_TXPOWER_RATE1
AR5K_PHY_TXPOWER_RATE2
AR5K_PHY_TXPOWER_RATE2
AR5K_PHY_TXPOWER_RATE3
AR5K_PHY_TXPOWER_RATE3
AR5K_PHY_TXPOWER_RATE4
AR5K_PHY_TXPOWER_RATE4
AR5K_PHY_WARM_RESET
AR5K_PHY_WARM_RESET
AR5K_PHY_WEAK_OFDM_HIGH_THR
AR5K_PHY_WEAK_OFDM_HIGH_THR
AR5K_PHY_WEAK_OFDM_HIGH_THR_M1
AR5K_PHY_WEAK_OFDM_HIGH_THR_M1
AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_
AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_
AR5K_PHY_WEAK_OFDM_LOW_THR
AR5K_PHY_WEAK_OFDM_LOW_THR
AR5K_PHY_WEAK_OFDM_LOW_THR_M1
AR5K_PHY_WEAK_OFDM_LOW_THR_M1
AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S
AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S
AR5K_PHY_WEAK_OFDM_LOW_THR_M2
AR5K_PHY_WEAK_OFDM_LOW_THR_M2
AR5K_PHY_WEAK_OFDM_LOW_THR_M2_C
AR5K_PHY_WEAK_OFDM_LOW_THR_M2_C
AR5K_PHY_WEAK_OFDM_LOW_THR_M2_C
AR5K_PHY_WEAK_OFDM_LOW_THR_M2_C
AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S
AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S
AR5K_PHY_WEAK_OFDM_LOW_THR_SELF
AR5K_PHY_WEAK_OFDM_LOW_THR_SELF
AR5K_PHY_WRITE(ah, _reg, _val)
AR5K_PHY_WRITE(ah, _reg, _val)
AR5K_PHYERR_CNT1
AR5K_PHYERR_CNT1
AR5K_PHYERR_CNT1_MASK
AR5K_PHYERR_CNT1_MASK
AR5K_PHYERR_CNT2
AR5K_PHYERR_CNT2
AR5K_PHYERR_CNT2_MASK
AR5K_PHYERR_CNT2_MASK
AR5K_PIMR	Register Address [5211+]
AR5K_PIMR	Register Address [5211+]
AR5K_PISR	Register Address [5211+]
AR5K_PISR	Register Address [5211+]
AR5K_PROFCNT_CYCLE	Cycle count (?)
AR5K_PROFCNT_CYCLE	Cycle count (?)
AR5K_PROFCNT_RX	Rx count
AR5K_PROFCNT_RX	Rx count
AR5K_PROFCNT_RXCLR	Clear Rx count
AR5K_PROFCNT_RXCLR	Clear Rx count
AR5K_PROFCNT_TX	Tx count
AR5K_PROFCNT_TX	Tx count
AR5K_Q_DISABLE_BITS(_reg, _queue)
AR5K_Q_DISABLE_BITS(_reg, _queue)
AR5K_Q_ENABLE_BITS(_reg, _queue)
AR5K_Q_ENABLE_BITS(_reg, _queue)
AR5K_QCU_CBB_ADDR
AR5K_QCU_CBB_ADDR
AR5K_QCU_CBB_ADDR_S
AR5K_QCU_CBB_ADDR_S
AR5K_QCU_CBB_SELECT
AR5K_QCU_CBB_SELECT
AR5K_QCU_CBCFG
AR5K_QCU_CBCFG
AR5K_QCU_CBRCFG_BASE	Register Address - Queue0 CBRCFG
AR5K_QCU_CBRCFG_BASE	Register Address - Queue0 CBRCFG
AR5K_QCU_CBRCFG_INTVAL	CBR Interval mask
AR5K_QCU_CBRCFG_INTVAL	CBR Interval mask
AR5K_QCU_CBRCFG_INTVAL_S
AR5K_QCU_CBRCFG_INTVAL_S
AR5K_QCU_CBRCFG_ORN_THRES	CBR overrun threshold mask
AR5K_QCU_CBRCFG_ORN_THRES	CBR overrun threshold mask
AR5K_QCU_CBRCFG_ORN_THRES_S
AR5K_QCU_CBRCFG_ORN_THRES_S
AR5K_QCU_GLOBAL_READ(_r, _q)
AR5K_QCU_GLOBAL_READ(_r, _q)
AR5K_QCU_GLOBAL_WRITE(_r, _q)
AR5K_QCU_GLOBAL_WRITE(_r, _q)
AR5K_QCU_MISC_BASE	Register Address -Queue0 MISC
AR5K_QCU_MISC_BASE	Register Address -Queue0 MISC
AR5K_QCU_MISC_BCN_ENABLE	Enable Beacon use
AR5K_QCU_MISC_BCN_ENABLE	Enable Beacon use
AR5K_QCU_MISC_CBR_RESET_CNT	CBR threshold (counter) reset
AR5K_QCU_MISC_CBR_RESET_CNT	CBR threshold (counter) reset
AR5K_QCU_MISC_CBR_THRES_ENABLE	CBR expired threshold enabled
AR5K_QCU_MISC_CBR_THRES_ENABLE	CBR expired threshold enabled
AR5K_QCU_MISC_CBREXP_BCN_DIS	Disable CBR expired counter (beacon queue)
AR5K_QCU_MISC_CBREXP_BCN_DIS	Disable CBR expired counter (beacon queue)
AR5K_QCU_MISC_CBREXP_DIS	Disable CBR expired counter (normal queue)
AR5K_QCU_MISC_CBREXP_DIS	Disable CBR expired counter (normal queue)
AR5K_QCU_MISC_DCU_CMP_EN	Enable frame compression
AR5K_QCU_MISC_DCU_CMP_EN	Enable frame compression
AR5K_QCU_MISC_DCU_EARLY	DCU early termination
AR5K_QCU_MISC_DCU_EARLY	DCU early termination
AR5K_QCU_MISC_FRSHED_ASAP	ASAP
AR5K_QCU_MISC_FRSHED_ASAP	ASAP
AR5K_QCU_MISC_FRSHED_BCN_SENT_G	Beacon sent gated
AR5K_QCU_MISC_FRSHED_BCN_SENT_G	Beacon sent gated
AR5K_QCU_MISC_FRSHED_CBR	Constant Bit Rate
AR5K_QCU_MISC_FRSHED_CBR	Constant Bit Rate
AR5K_QCU_MISC_FRSHED_DBA_GT	DMA Beacon alert gated
AR5K_QCU_MISC_FRSHED_DBA_GT	DMA Beacon alert gated
AR5K_QCU_MISC_FRSHED_M	Frame sheduling mask
AR5K_QCU_MISC_FRSHED_M	Frame sheduling mask
AR5K_QCU_MISC_FRSHED_TIM_GT	TIMT gated
AR5K_QCU_MISC_FRSHED_TIM_GT	TIMT gated
AR5K_QCU_MISC_ONESHOT_ENABLE	Oneshot enable
AR5K_QCU_MISC_ONESHOT_ENABLE	Oneshot enable
AR5K_QCU_MISC_RDY_VEOL_POLICY	TXE reset when RDYTIME expired or VEOL
AR5K_QCU_MISC_RDY_VEOL_POLICY	TXE reset when RDYTIME expired or VEOL
AR5K_QCU_ONESHOTARM_CLEAR	Register Address -QCU "one shot arm clear (?)"
AR5K_QCU_ONESHOTARM_CLEAR	Register Address -QCU "one shot arm clear (?)"
AR5K_QCU_ONESHOTARM_CLEAR_M
AR5K_QCU_ONESHOTARM_CLEAR_M
AR5K_QCU_ONESHOTARM_SET	Register Address -QCU "one shot arm set (?)"
AR5K_QCU_ONESHOTARM_SET	Register Address -QCU "one shot arm set (?)"
AR5K_QCU_ONESHOTARM_SET_M
AR5K_QCU_ONESHOTARM_SET_M
AR5K_QCU_RDYTIMECFG_BASE	Register Address - Queue0 RDYTIMECFG
AR5K_QCU_RDYTIMECFG_BASE	Register Address - Queue0 RDYTIMECFG
AR5K_QCU_RDYTIMECFG_ENABLE	Ready time enable mask
AR5K_QCU_RDYTIMECFG_ENABLE	Ready time enable mask
AR5K_QCU_RDYTIMECFG_INTVAL	Ready time interval mask
AR5K_QCU_RDYTIMECFG_INTVAL	Ready time interval mask
AR5K_QCU_RDYTIMECFG_INTVAL_S
AR5K_QCU_RDYTIMECFG_INTVAL_S
AR5K_QCU_RDYTIMESHDN
AR5K_QCU_RDYTIMESHDN
AR5K_QCU_RDYTIMESHDN_M
AR5K_QCU_RDYTIMESHDN_M
AR5K_QCU_SLEEP_MASK
AR5K_QCU_SLEEP_MASK
AR5K_QCU_STS_BASE	Register Address - Queue0 STS
AR5K_QCU_STS_BASE	Register Address - Queue0 STS
AR5K_QCU_STS_CBREXPCNT	CBR expired counter
AR5K_QCU_STS_CBREXPCNT	CBR expired counter
AR5K_QCU_STS_FRMPENDCNT	Frames pending counter
AR5K_QCU_STS_FRMPENDCNT	Frames pending counter
AR5K_QCU_TXD
AR5K_QCU_TXD
AR5K_QCU_TXDP_BASE	Register Address - Queue0 TXDP
AR5K_QCU_TXDP_BASE	Register Address - Queue0 TXDP
AR5K_QCU_TXE
AR5K_QCU_TXE
AR5K_QCUDCU_CLKGT	Register Address (?)
AR5K_QCUDCU_CLKGT	Register Address (?)
AR5K_QCUDCU_CLKGT_DCU	Mask for DCU clock
AR5K_QCUDCU_CLKGT_DCU	Mask for DCU clock
AR5K_QCUDCU_CLKGT_QCU	Mask for QCU clock
AR5K_QCUDCU_CLKGT_QCU	Mask for QCU clock
AR5K_QOS_NOACK	Register Address
AR5K_QOS_NOACK	Register Address
AR5K_QOS_NOACK_2BIT_VALUES	???
AR5K_QOS_NOACK_2BIT_VALUES	???
AR5K_QOS_NOACK_2BIT_VALUES_S
AR5K_QOS_NOACK_2BIT_VALUES_S
AR5K_QOS_NOACK_BIT_OFFSET	???
AR5K_QOS_NOACK_BIT_OFFSET	???
AR5K_QOS_NOACK_BIT_OFFSET_S
AR5K_QOS_NOACK_BIT_OFFSET_S
AR5K_QOS_NOACK_BYTE_OFFSET	???
AR5K_QOS_NOACK_BYTE_OFFSET	???
AR5K_QOS_NOACK_BYTE_OFFSET_S
AR5K_QOS_NOACK_BYTE_OFFSET_S
AR5K_QUEUE_CBRCFG(_q)
AR5K_QUEUE_CBRCFG(_q)
AR5K_QUEUE_DCU_SEQNUM(_q)
AR5K_QUEUE_DCU_SEQNUM(_q)
AR5K_QUEUE_DFS_CHANNEL_TIME(_q)
AR5K_QUEUE_DFS_CHANNEL_TIME(_q)
AR5K_QUEUE_DFS_LOCAL_IFS(_q)
AR5K_QUEUE_DFS_LOCAL_IFS(_q)
AR5K_QUEUE_DFS_MISC(_q)
AR5K_QUEUE_DFS_MISC(_q)
AR5K_QUEUE_DFS_RETRY_LIMIT(_q)
AR5K_QUEUE_DFS_RETRY_LIMIT(_q)
AR5K_QUEUE_DISABLED(_q)
AR5K_QUEUE_DISABLED(_q)
AR5K_QUEUE_ENABLED(_q)
AR5K_QUEUE_ENABLED(_q)
AR5K_QUEUE_MISC(_q)
AR5K_QUEUE_MISC(_q)
AR5K_QUEUE_QCUMASK(_q)
AR5K_QUEUE_QCUMASK(_q)
AR5K_QUEUE_RDYTIMECFG(_q)
AR5K_QUEUE_RDYTIMECFG(_q)
AR5K_QUEUE_REG(_r, _q)
AR5K_QUEUE_REG(_r, _q)
AR5K_QUEUE_STATUS(_q)
AR5K_QUEUE_STATUS(_q)
AR5K_QUEUE_TXDP(_q)
AR5K_QUEUE_TXDP(_q)
AR5K_QUIET_CTL1	Register Address
AR5K_QUIET_CTL1	Register Address
AR5K_QUIET_CTL1_ACK_CTS_EN	Send ACK/CTS during quiet period
AR5K_QUIET_CTL1_ACK_CTS_EN	Send ACK/CTS during quiet period
AR5K_QUIET_CTL1_NEXT_QT_TSF	Next quiet period TSF (TU)
AR5K_QUIET_CTL1_NEXT_QT_TSF	Next quiet period TSF (TU)
AR5K_QUIET_CTL1_NEXT_QT_TSF_S
AR5K_QUIET_CTL1_NEXT_QT_TSF_S
AR5K_QUIET_CTL1_QT_EN	Enable quiet period
AR5K_QUIET_CTL1_QT_EN	Enable quiet period
AR5K_QUIET_CTL2	Register Address
AR5K_QUIET_CTL2	Register Address
AR5K_QUIET_CTL2_QT_DUR	Mask for quiet period duration
AR5K_QUIET_CTL2_QT_DUR	Mask for quiet period duration
AR5K_QUIET_CTL2_QT_DUR_S
AR5K_QUIET_CTL2_QT_DUR_S
AR5K_QUIET_CTL2_QT_PER	Mask for quiet period periodicity
AR5K_QUIET_CTL2_QT_PER	Mask for quiet period periodicity
AR5K_QUIET_CTL2_QT_PER_S
AR5K_QUIET_CTL2_QT_PER_S
AR5K_RAC_PISR	Read and clear PISR
AR5K_RAC_PISR	Read and clear PISR
AR5K_RAC_SISR0	Read and clear SISR0
AR5K_RAC_SISR0	Read and clear SISR0
AR5K_RAC_SISR1	Read and clear SISR1
AR5K_RAC_SISR1	Read and clear SISR1
AR5K_RAC_SISR2	Read and clear SISR2
AR5K_RAC_SISR2	Read and clear SISR2
AR5K_RAC_SISR3	Read and clear SISR3
AR5K_RAC_SISR3	Read and clear SISR3
AR5K_RAC_SISR4	Read and clear SISR4
AR5K_RAC_SISR4	Read and clear SISR4
AR5K_RATE_ACKSIFS(_n)
AR5K_RATE_ACKSIFS(_n)
AR5K_RATE_ACKSIFS_BASE	Register Address
AR5K_RATE_ACKSIFS_BASE	Register Address
AR5K_RATE_ACKSIFS_NORMAL	Normal SIFS (field)
AR5K_RATE_ACKSIFS_NORMAL	Normal SIFS (field)
AR5K_RATE_ACKSIFS_TURBO	Turbo SIFS (field)
AR5K_RATE_ACKSIFS_TURBO	Turbo SIFS (field)
AR5K_RATE_DUR(_n)
AR5K_RATE_DUR(_n)
AR5K_RATE_DUR_BASE
AR5K_RATE_DUR_BASE
AR5K_RATE2DB(_n)
AR5K_RATE2DB(_n)
AR5K_RATE2DB_BASE
AR5K_RATE2DB_BASE
AR5K_REG_DISABLE_BITS(ah, _reg, _flags)
AR5K_REG_DISABLE_BITS(ah, _reg, _flags)
AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask)
AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask)
AR5K_REG_MS(_val, _flags)
AR5K_REG_MS(_val, _flags)
AR5K_REG_READ_Q(ah, _reg, _queue)
AR5K_REG_READ_Q(ah, _reg, _queue)
AR5K_REG_SM(_val, _flags)
AR5K_REG_SM(_val, _flags)
AR5K_REG_WAIT(_i)
AR5K_REG_WAIT(_i)
AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)
AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)
AR5K_REG_WRITE_Q(ah, _reg, _queue)
AR5K_REG_WRITE_Q(ah, _reg, _queue)
AR5K_RESET_CTL	Register Address
AR5K_RESET_CTL	Register Address
AR5K_RESET_CTL_BASEBAND	Baseband reset [5211+]
AR5K_RESET_CTL_BASEBAND	Baseband reset [5211+]
AR5K_RESET_CTL_DMA	DMA (Rx/Tx) reset [5210]
AR5K_RESET_CTL_DMA	DMA (Rx/Tx) reset [5210]
AR5K_RESET_CTL_MAC	MAC reset (PCU+Baseband ?) [5210]
AR5K_RESET_CTL_MAC	MAC reset (PCU+Baseband ?) [5210]
AR5K_RESET_CTL_PCI	PCI Core reset (interrupts etc)
AR5K_RESET_CTL_PCI	PCI Core reset (interrupts etc)
AR5K_RESET_CTL_PCU	Protocol Control Unit reset
AR5K_RESET_CTL_PCU	Protocol Control Unit reset
AR5K_RESET_CTL_PHY	PHY reset [5210]
AR5K_RESET_CTL_PHY	PHY reset [5210]
AR5K_RETRY_CNT	Register Address [5210]
AR5K_RETRY_CNT	Register Address [5210]
AR5K_RETRY_CNT_SLG	Station long retry count (?)
AR5K_RETRY_CNT_SLG	Station long retry count (?)
AR5K_RETRY_CNT_SSH	Station short retry count (?)
AR5K_RETRY_CNT_SSH	Station short retry count (?)
AR5K_RF_BUFFER
AR5K_RF_BUFFER
AR5K_RF_BUFFER_CONTROL_0	Channel on 5110
AR5K_RF_BUFFER_CONTROL_0	Channel on 5110
AR5K_RF_BUFFER_CONTROL_1	Bank 7 on 5112
AR5K_RF_BUFFER_CONTROL_1	Bank 7 on 5112
AR5K_RF_BUFFER_CONTROL_2	Bank 7 on 5111
AR5K_RF_BUFFER_CONTROL_2	Bank 7 on 5111
AR5K_RF_BUFFER_CONTROL_3	Bank 2 on 5112
AR5K_RF_BUFFER_CONTROL_3	Bank 2 on 5112
AR5K_RF_BUFFER_CONTROL_4	RF Stage register on 5110
AR5K_RF_BUFFER_CONTROL_4	RF Stage register on 5110
AR5K_RF_BUFFER_CONTROL_5	Bank 3 on 5111
AR5K_RF_BUFFER_CONTROL_5	Bank 3 on 5111
AR5K_RF_BUFFER_CONTROL_6	Bank 3 on 5112
AR5K_RF_BUFFER_CONTROL_6	Bank 3 on 5112
AR5K_RF_GAIN(_n)
AR5K_RF_GAIN(_n)
AR5K_RF_GAIN_BASE	RF Amplrifier Gain table base address
AR5K_RF_GAIN_BASE	RF Amplrifier Gain table base address
AR5K_RF2316_DB_2GHZ
AR5K_RF2316_DB_2GHZ
AR5K_RF2316_OB_2GHZ
AR5K_RF2316_OB_2GHZ
AR5K_RF2413_DB_2GHZ
AR5K_RF2413_DB_2GHZ
AR5K_RF2413_OB_2GHZ
AR5K_RF2413_OB_2GHZ
AR5K_RF2425_DB_2GHZ
AR5K_RF2425_DB_2GHZ
AR5K_RF2425_OB_2GHZ
AR5K_RF2425_OB_2GHZ
AR5K_RF5111_DB_2GHZ
AR5K_RF5111_DB_2GHZ
AR5K_RF5111_DB_5GHZ
AR5K_RF5111_DB_5GHZ
AR5K_RF5111_GAIN_I
AR5K_RF5111_GAIN_I
AR5K_RF5111_MAX_TIME
AR5K_RF5111_MAX_TIME
AR5K_RF5111_OB_2GHZ
AR5K_RF5111_OB_2GHZ
AR5K_RF5111_OB_5GHZ
AR5K_RF5111_OB_5GHZ
AR5K_RF5111_PLO_SEL
AR5K_RF5111_PLO_SEL
AR5K_RF5111_PWD(_n)
AR5K_RF5111_PWD(_n)
AR5K_RF5111_PWD_XPD
AR5K_RF5111_PWD_XPD
AR5K_RF5111_RFGAIN_SEL
AR5K_RF5111_RFGAIN_SEL
AR5K_RF5111_RFGAIN_STEP
AR5K_RF5111_RFGAIN_STEP
AR5K_RF5111_WAIT_I
AR5K_RF5111_WAIT_I
AR5K_RF5111_WAIT_S
AR5K_RF5111_WAIT_S
AR5K_RF5111_XPD_GAIN
AR5K_RF5111_XPD_GAIN
AR5K_RF5112_DB_2GHZ
AR5K_RF5112_DB_2GHZ
AR5K_RF5112_DB_5GHZ
AR5K_RF5112_DB_5GHZ
AR5K_RF5112_FIXED_BIAS_A
AR5K_RF5112_FIXED_BIAS_A
AR5K_RF5112_FIXED_BIAS_B
AR5K_RF5112_FIXED_BIAS_B
AR5K_RF5112_OB_2GHZ
AR5K_RF5112_OB_2GHZ
AR5K_RF5112_OB_5GHZ
AR5K_RF5112_OB_5GHZ
AR5K_RF5112_PWD(_n)
AR5K_RF5112_PWD(_n)
AR5K_RF5112_XPD_GAIN
AR5K_RF5112_XPD_GAIN
AR5K_RF5112_XPD_SEL
AR5K_RF5112_XPD_SEL
AR5K_RF5112A_DB_2GHZ
AR5K_RF5112A_DB_2GHZ
AR5K_RF5112A_DB_5GHZ
AR5K_RF5112A_DB_5GHZ
AR5K_RF5112A_FIXED_BIAS_A
AR5K_RF5112A_FIXED_BIAS_A
AR5K_RF5112A_FIXED_BIAS_B
AR5K_RF5112A_FIXED_BIAS_B
AR5K_RF5112A_HIGH_VC_CP
AR5K_RF5112A_HIGH_VC_CP
AR5K_RF5112A_LOW_VC_CP
AR5K_RF5112A_LOW_VC_CP
AR5K_RF5112A_MID_VC_CP
AR5K_RF5112A_MID_VC_CP
AR5K_RF5112A_OB_2GHZ
AR5K_RF5112A_OB_2GHZ
AR5K_RF5112A_OB_5GHZ
AR5K_RF5112A_OB_5GHZ
AR5K_RF5112A_PAD2GND
AR5K_RF5112A_PAD2GND
AR5K_RF5112A_PDGAINHI
AR5K_RF5112A_PDGAINHI
AR5K_RF5112A_PDGAINLO
AR5K_RF5112A_PDGAINLO
AR5K_RF5112A_PUSH_UP
AR5K_RF5112A_PUSH_UP
AR5K_RF5112A_PWD(_n)
AR5K_RF5112A_PWD(_n)
AR5K_RF5112A_XB2_LVL
AR5K_RF5112A_XB2_LVL
AR5K_RF5112A_XB5_LVL
AR5K_RF5112A_XB5_LVL
AR5K_RF5112A_XPD_SEL
AR5K_RF5112A_XPD_SEL
AR5K_RF5112X_GAIN_I
AR5K_RF5112X_GAIN_I
AR5K_RF5112X_MIXGAIN_OVR
AR5K_RF5112X_MIXGAIN_OVR
AR5K_RF5112X_MIXGAIN_STEP
AR5K_RF5112X_MIXGAIN_STEP
AR5K_RF5112X_MIXVGA_OVR
AR5K_RF5112X_MIXVGA_OVR
AR5K_RF5112X_PD_DELAY_A
AR5K_RF5112X_PD_DELAY_A
AR5K_RF5112X_PD_DELAY_B
AR5K_RF5112X_PD_DELAY_B
AR5K_RF5112X_PD_DELAY_XR
AR5K_RF5112X_PD_DELAY_XR
AR5K_RF5112X_PD_PERIOD_A
AR5K_RF5112X_PD_PERIOD_A
AR5K_RF5112X_PD_PERIOD_B
AR5K_RF5112X_PD_PERIOD_B
AR5K_RF5112X_PD_PERIOD_XR
AR5K_RF5112X_PD_PERIOD_XR
AR5K_RF5413_DB_2GHZ
AR5K_RF5413_DB_2GHZ
AR5K_RF5413_DB_5GHZ
AR5K_RF5413_DB_5GHZ
AR5K_RF5413_DERBY_CHAN_SEL_MODE
AR5K_RF5413_DERBY_CHAN_SEL_MODE
AR5K_RF5413_OB_2GHZ
AR5K_RF5413_OB_2GHZ
AR5K_RF5413_OB_5GHZ
AR5K_RF5413_OB_5GHZ
AR5K_RF5413_PWD_ICLOBUF2G
AR5K_RF5413_PWD_ICLOBUF2G
AR5K_RFCNT
AR5K_RFCNT
AR5K_RFCNT_M	[5211+] (?)
AR5K_RFCNT_M	[5211+] (?)
AR5K_RFCNT_RFCL	[5210]
AR5K_RFCNT_RFCL	[5210]
AR5K_RPGTO
AR5K_RPGTO
AR5K_RPGTO_M
AR5K_RPGTO_M
AR5K_RSSI_EP_MULTIPLIER
AR5K_RSSI_EP_MULTIPLIER
AR5K_RSSI_THR	Register Address
AR5K_RSSI_THR	Register Address
AR5K_RSSI_THR_BMISS
AR5K_RSSI_THR_BMISS
AR5K_RSSI_THR_BMISS_5210	Mask for Beacon Missed threshold [5210]
AR5K_RSSI_THR_BMISS_5210	Mask for Beacon Missed threshold [5210]
AR5K_RSSI_THR_BMISS_5210_S
AR5K_RSSI_THR_BMISS_5210_S
AR5K_RSSI_THR_BMISS_5211	Mask for Beacon Missed threshold [5211+]
AR5K_RSSI_THR_BMISS_5211	Mask for Beacon Missed threshold [5211+]
AR5K_RSSI_THR_BMISS_5211_S
AR5K_RSSI_THR_BMISS_5211_S
AR5K_RSSI_THR_BMISS_S
AR5K_RSSI_THR_BMISS_S
AR5K_RSSI_THR_M	Mask for RSSI threshold [5211+]
AR5K_RSSI_THR_M	Mask for RSSI threshold [5211+]
AR5K_RTS_FAIL
AR5K_RTS_FAIL
AR5K_RTS_FAIL_5210
AR5K_RTS_FAIL_5210
AR5K_RTS_FAIL_5211
AR5K_RTS_FAIL_5211
AR5K_RTS_OK
AR5K_RTS_OK
AR5K_RTS_OK_5210
AR5K_RTS_OK_5210
AR5K_RTS_OK_5211
AR5K_RTS_OK_5211
AR5K_RTSD0	Register Address
AR5K_RTSD0	Register Address
AR5K_RTSD0_12	12Mb
AR5K_RTSD0_12	12Mb
AR5K_RTSD0_12_S
AR5K_RTSD0_12_S
AR5K_RTSD0_18	16Mb
AR5K_RTSD0_18	16Mb
AR5K_RTSD0_18_S
AR5K_RTSD0_18_S
AR5K_RTSD0_6	6Mb RTS duration mask (?)
AR5K_RTSD0_6	6Mb RTS duration mask (?)
AR5K_RTSD0_6_S	6Mb RTS duration shift (?)
AR5K_RTSD0_6_S	6Mb RTS duration shift (?)
AR5K_RTSD0_9	9Mb
AR5K_RTSD0_9	9Mb
AR5K_RTSD0_9_S
AR5K_RTSD0_9_S
AR5K_RTSD1	Register Address
AR5K_RTSD1	Register Address
AR5K_RTSD1_24	24Mb
AR5K_RTSD1_24	24Mb
AR5K_RTSD1_24_S
AR5K_RTSD1_24_S
AR5K_RTSD1_36	36Mb
AR5K_RTSD1_36	36Mb
AR5K_RTSD1_36_S
AR5K_RTSD1_36_S
AR5K_RTSD1_48	48Mb
AR5K_RTSD1_48	48Mb
AR5K_RTSD1_48_S
AR5K_RTSD1_48_S
AR5K_RTSD1_54	54Mb
AR5K_RTSD1_54	54Mb
AR5K_RTSD1_54_S
AR5K_RTSD1_54_S
AR5K_RX_DESC_ERROR0
AR5K_RX_DESC_ERROR0
AR5K_RX_DESC_ERROR1_PHY_ERROR_C
AR5K_RX_DESC_ERROR1_PHY_ERROR_C
AR5K_RX_DESC_ERROR1_PHY_ERROR_C
AR5K_RX_DESC_ERROR1_PHY_ERROR_C
AR5K_RX_FILTER
AR5K_RX_FILTER
AR5K_RX_FILTER_5210	Register Address [5210]
AR5K_RX_FILTER_5210	Register Address [5210]
AR5K_RX_FILTER_5211	Register Address [5211+]
AR5K_RX_FILTER_5211	Register Address [5211+]
AR5K_RX_FILTER_BCAST	Don't filter broadcast frames
AR5K_RX_FILTER_BCAST	Don't filter broadcast frames
AR5K_RX_FILTER_BEACON	Don't filter beacon frames
AR5K_RX_FILTER_BEACON	Don't filter beacon frames
AR5K_RX_FILTER_CONTROL	Don't filter control frames
AR5K_RX_FILTER_CONTROL	Don't filter control frames
AR5K_RX_FILTER_MCAST	Don't filter multicast frames
AR5K_RX_FILTER_MCAST	Don't filter multicast frames
AR5K_RX_FILTER_PHYERR
AR5K_RX_FILTER_PHYERR
AR5K_RX_FILTER_PHYERR_5211	[5211]
AR5K_RX_FILTER_PHYERR_5211	[5211]
AR5K_RX_FILTER_PHYERR_5212	Don't filter phy errors [5212+]
AR5K_RX_FILTER_PHYERR_5212	Don't filter phy errors [5212+]
AR5K_RX_FILTER_PROBEREQ	Don't filter probe requests [5212+]
AR5K_RX_FILTER_PROBEREQ	Don't filter probe requests [5212+]
AR5K_RX_FILTER_PROM	Set promiscuous mode
AR5K_RX_FILTER_PROM	Set promiscuous mode
AR5K_RX_FILTER_RADARERR
AR5K_RX_FILTER_RADARERR
AR5K_RX_FILTER_RADARERR_5211	[5211]
AR5K_RX_FILTER_RADARERR_5211	[5211]
AR5K_RX_FILTER_RADARERR_5212	Don't filter phy radar errors [5212+]
AR5K_RX_FILTER_RADARERR_5212	Don't filter phy radar errors [5212+]
AR5K_RX_FILTER_UCAST	Don't filter unicast frames
AR5K_RX_FILTER_UCAST	Don't filter unicast frames
AR5K_RX_FILTER_XRPOLL	Don't filter XR poll frame [5212+]
AR5K_RX_FILTER_XRPOLL	Don't filter XR poll frame [5212+]
AR5K_RXCFG	Register Address
AR5K_RXCFG	Register Address
AR5K_RXCFG_DEF_ANTENNA	Default antenna (?)
AR5K_RXCFG_DEF_ANTENNA	Default antenna (?)
AR5K_RXCFG_JUMBO_RXE	Enable jumbo rx descriptors [5211+]
AR5K_RXCFG_JUMBO_RXE	Enable jumbo rx descriptors [5211+]
AR5K_RXCFG_JUMBO_WRAP	Wrap jumbo frames [5211+]
AR5K_RXCFG_JUMBO_WRAP	Wrap jumbo frames [5211+]
AR5K_RXCFG_SDMAMW	DMA size (write)
AR5K_RXCFG_SDMAMW	DMA size (write)
AR5K_RXCFG_SDMAMW_S
AR5K_RXCFG_SDMAMW_S
AR5K_RXCFG_SLE_ENTRY	Sleep entry policy
AR5K_RXCFG_SLE_ENTRY	Sleep entry policy
AR5K_RXCFG_ZLFDMA	Enable Zero-length frame DMA
AR5K_RXCFG_ZLFDMA	Enable Zero-length frame DMA
AR5K_RXDESC_INTREQ
AR5K_RXDESC_INTREQ
AR5K_RXDP
AR5K_RXDP
AR5K_RXERR_CRC
AR5K_RXERR_CRC
AR5K_RXERR_DECRYPT
AR5K_RXERR_DECRYPT
AR5K_RXERR_FIFO
AR5K_RXERR_FIFO
AR5K_RXERR_MIC
AR5K_RXERR_MIC
AR5K_RXERR_PHY
AR5K_RXERR_PHY
AR5K_RXJLA
AR5K_RXJLA
AR5K_RXKEYIX_INVALID
AR5K_RXKEYIX_INVALID
AR5K_RXNOFRM
AR5K_RXNOFRM
AR5K_RXNOFRM_M
AR5K_RXNOFRM_M
AR5K_SEQ_MASK
AR5K_SEQ_MASK
AR5K_SET_SHORT_PREAMBLE
AR5K_SET_SHORT_PREAMBLE
AR5K_SFR
AR5K_SFR
AR5K_SFR_EN
AR5K_SFR_EN
AR5K_SIMR0	Register Address [5211+]
AR5K_SIMR0	Register Address [5211+]
AR5K_SIMR0_QCU_TXDESC	Mask for QCU_TXDESC
AR5K_SIMR0_QCU_TXDESC	Mask for QCU_TXDESC
AR5K_SIMR0_QCU_TXDESC_S
AR5K_SIMR0_QCU_TXDESC_S
AR5K_SIMR0_QCU_TXOK	Mask for QCU_TXOK
AR5K_SIMR0_QCU_TXOK	Mask for QCU_TXOK
AR5K_SIMR0_QCU_TXOK_S
AR5K_SIMR0_QCU_TXOK_S
AR5K_SIMR1	Register Address [5211+]
AR5K_SIMR1	Register Address [5211+]
AR5K_SIMR1_QCU_TXEOL	Mask for QCU_TXEOL
AR5K_SIMR1_QCU_TXEOL	Mask for QCU_TXEOL
AR5K_SIMR1_QCU_TXEOL_S
AR5K_SIMR1_QCU_TXEOL_S
AR5K_SIMR1_QCU_TXERR	Mask for QCU_TXERR
AR5K_SIMR1_QCU_TXERR	Mask for QCU_TXERR
AR5K_SIMR1_QCU_TXERR_S
AR5K_SIMR1_QCU_TXERR_S
AR5K_SIMR2	Register Address [5211+]
AR5K_SIMR2	Register Address [5211+]
AR5K_SIMR2_BCN_TIMEOUT	Beacon Timeout [5212+]
AR5K_SIMR2_BCN_TIMEOUT	Beacon Timeout [5212+]
AR5K_SIMR2_CAB_END	[5212+]
AR5K_SIMR2_CAB_END	[5212+]
AR5K_SIMR2_CAB_TIMEOUT	CAB Timeout [5212+]
AR5K_SIMR2_CAB_TIMEOUT	CAB Timeout [5212+]
AR5K_SIMR2_DPERR	Bus parity error
AR5K_SIMR2_DPERR	Bus parity error
AR5K_SIMR2_DTIM	[5212+]
AR5K_SIMR2_DTIM	[5212+]
AR5K_SIMR2_DTIM_SYNC	DTIM Sync lost [5212+]
AR5K_SIMR2_DTIM_SYNC	DTIM Sync lost [5212+]
AR5K_SIMR2_MCABT	Master Cycle Abort
AR5K_SIMR2_MCABT	Master Cycle Abort
AR5K_SIMR2_QCU_TXURN	Mask for QCU_TXURN
AR5K_SIMR2_QCU_TXURN	Mask for QCU_TXURN
AR5K_SIMR2_QCU_TXURN_S
AR5K_SIMR2_QCU_TXURN_S
AR5K_SIMR2_SSERR	Signaled System Error
AR5K_SIMR2_SSERR	Signaled System Error
AR5K_SIMR2_TIM	[5212+]
AR5K_SIMR2_TIM	[5212+]
AR5K_SIMR2_TSFOOR	TSF OOR (?)
AR5K_SIMR2_TSFOOR	TSF OOR (?)
AR5K_SIMR3	Register Address [5211+]
AR5K_SIMR3	Register Address [5211+]
AR5K_SIMR3_QCBRORN	Mask for QCBRORN
AR5K_SIMR3_QCBRORN	Mask for QCBRORN
AR5K_SIMR3_QCBRORN_S
AR5K_SIMR3_QCBRORN_S
AR5K_SIMR3_QCBRURN	Mask for QCBRURN
AR5K_SIMR3_QCBRURN	Mask for QCBRURN
AR5K_SIMR3_QCBRURN_S
AR5K_SIMR3_QCBRURN_S
AR5K_SIMR4	Register Address [5211+]
AR5K_SIMR4	Register Address [5211+]
AR5K_SIMR4_QTRIG	Mask for QTRIG
AR5K_SIMR4_QTRIG	Mask for QTRIG
AR5K_SIMR4_QTRIG_S
AR5K_SIMR4_QTRIG_S
AR5K_SISR0	Register Address [5211+]
AR5K_SISR0	Register Address [5211+]
AR5K_SISR0_QCU_TXDESC	Mask for QCU_TXDESC
AR5K_SISR0_QCU_TXDESC	Mask for QCU_TXDESC
AR5K_SISR0_QCU_TXDESC_S
AR5K_SISR0_QCU_TXDESC_S
AR5K_SISR0_QCU_TXOK	Mask for QCU_TXOK
AR5K_SISR0_QCU_TXOK	Mask for QCU_TXOK
AR5K_SISR0_QCU_TXOK_S
AR5K_SISR0_QCU_TXOK_S
AR5K_SISR1	Register Address [5211+]
AR5K_SISR1	Register Address [5211+]
AR5K_SISR1_QCU_TXEOL	Mask for QCU_TXEOL
AR5K_SISR1_QCU_TXEOL	Mask for QCU_TXEOL
AR5K_SISR1_QCU_TXEOL_S
AR5K_SISR1_QCU_TXEOL_S
AR5K_SISR1_QCU_TXERR	Mask for QCU_TXERR
AR5K_SISR1_QCU_TXERR	Mask for QCU_TXERR
AR5K_SISR1_QCU_TXERR_S
AR5K_SISR1_QCU_TXERR_S
AR5K_SISR2	Register Address [5211+]
AR5K_SISR2	Register Address [5211+]
AR5K_SISR2_BCN_TIMEOUT	Beacon Timeout [5212+]
AR5K_SISR2_BCN_TIMEOUT	Beacon Timeout [5212+]
AR5K_SISR2_CAB_END	[5212+]
AR5K_SISR2_CAB_END	[5212+]
AR5K_SISR2_CAB_TIMEOUT	CAB Timeout [5212+]
AR5K_SISR2_CAB_TIMEOUT	CAB Timeout [5212+]
AR5K_SISR2_DPERR	Bus parity error
AR5K_SISR2_DPERR	Bus parity error
AR5K_SISR2_DTIM	[5212+]
AR5K_SISR2_DTIM	[5212+]
AR5K_SISR2_DTIM_SYNC	DTIM sync lost [5212+]
AR5K_SISR2_DTIM_SYNC	DTIM sync lost [5212+]
AR5K_SISR2_MCABT	Master Cycle Abort
AR5K_SISR2_MCABT	Master Cycle Abort
AR5K_SISR2_QCU_TXURN	Mask for QCU_TXURN
AR5K_SISR2_QCU_TXURN	Mask for QCU_TXURN
AR5K_SISR2_QCU_TXURN_S
AR5K_SISR2_QCU_TXURN_S
AR5K_SISR2_SSERR	Signaled System Error
AR5K_SISR2_SSERR	Signaled System Error
AR5K_SISR2_TIM	[5212+]
AR5K_SISR2_TIM	[5212+]
AR5K_SISR2_TSFOOR	TSF OOR (?)
AR5K_SISR2_TSFOOR	TSF OOR (?)
AR5K_SISR3	Register Address [5211+]
AR5K_SISR3	Register Address [5211+]
AR5K_SISR3_QCBRORN	Mask for QCBRORN
AR5K_SISR3_QCBRORN	Mask for QCBRORN
AR5K_SISR3_QCBRORN_S
AR5K_SISR3_QCBRORN_S
AR5K_SISR3_QCBRURN	Mask for QCBRURN
AR5K_SISR3_QCBRURN	Mask for QCBRURN
AR5K_SISR3_QCBRURN_S
AR5K_SISR3_QCBRURN_S
AR5K_SISR4	Register Address [5211+]
AR5K_SISR4	Register Address [5211+]
AR5K_SISR4_QTRIG	Mask for QTRIG
AR5K_SISR4_QTRIG	Mask for QTRIG
AR5K_SISR4_QTRIG_S
AR5K_SISR4_QTRIG_S
AR5K_SLEEP_CTL	Register Address
AR5K_SLEEP_CTL	Register Address
AR5K_SLEEP_CTL_DUR_TIM_POL	Sleep duration timing policy
AR5K_SLEEP_CTL_DUR_TIM_POL	Sleep duration timing policy
AR5K_SLEEP_CTL_DUR_WRITE_POL	Sleep duration write policy
AR5K_SLEEP_CTL_DUR_WRITE_POL	Sleep duration write policy
AR5K_SLEEP_CTL_SLDUR	Sleep duration mask
AR5K_SLEEP_CTL_SLDUR	Sleep duration mask
AR5K_SLEEP_CTL_SLDUR_S
AR5K_SLEEP_CTL_SLDUR_S
AR5K_SLEEP_CTL_SLE	Sleep enable mask
AR5K_SLEEP_CTL_SLE	Sleep enable mask
AR5K_SLEEP_CTL_SLE_ALLOW	Normal sleep policy
AR5K_SLEEP_CTL_SLE_ALLOW	Normal sleep policy
AR5K_SLEEP_CTL_SLE_POL	Sleep policy mode
AR5K_SLEEP_CTL_SLE_POL	Sleep policy mode
AR5K_SLEEP_CTL_SLE_S
AR5K_SLEEP_CTL_SLE_S
AR5K_SLEEP_CTL_SLE_SLP	Force chip sleep
AR5K_SLEEP_CTL_SLE_SLP	Force chip sleep
AR5K_SLEEP_CTL_SLE_UNITS	[5211+]
AR5K_SLEEP_CTL_SLE_UNITS	[5211+]
AR5K_SLEEP_CTL_SLE_WAKE	Force chip awake
AR5K_SLEEP_CTL_SLE_WAKE	Force chip awake
AR5K_SLEEP0	Register Address
AR5K_SLEEP0	Register Address
AR5K_SLEEP0_ASSUME_DTIM	Assume DTIM
AR5K_SLEEP0_ASSUME_DTIM	Assume DTIM
AR5K_SLEEP0_CABTO	Mask for CAB Time Out
AR5K_SLEEP0_CABTO	Mask for CAB Time Out
AR5K_SLEEP0_CABTO_S
AR5K_SLEEP0_CABTO_S
AR5K_SLEEP0_ENH_SLEEP_EN	Enable enchanced sleep control
AR5K_SLEEP0_ENH_SLEEP_EN	Enable enchanced sleep control
AR5K_SLEEP0_NEXT_DTIM	Mask for next DTIM (?)
AR5K_SLEEP0_NEXT_DTIM	Mask for next DTIM (?)
AR5K_SLEEP0_NEXT_DTIM_S
AR5K_SLEEP0_NEXT_DTIM_S
AR5K_SLEEP1	Register Address
AR5K_SLEEP1	Register Address
AR5K_SLEEP1_BEACON_TO	Mask for Beacon Time Out
AR5K_SLEEP1_BEACON_TO	Mask for Beacon Time Out
AR5K_SLEEP1_BEACON_TO_S
AR5K_SLEEP1_BEACON_TO_S
AR5K_SLEEP1_NEXT_TIM	Mask for next TIM (?)
AR5K_SLEEP1_NEXT_TIM	Mask for next TIM (?)
AR5K_SLEEP1_NEXT_TIM_S
AR5K_SLEEP1_NEXT_TIM_S
AR5K_SLEEP2	Register Address
AR5K_SLEEP2	Register Address
AR5K_SLEEP2_DTIM_PER	Mask for DTIM period (?)
AR5K_SLEEP2_DTIM_PER	Mask for DTIM period (?)
AR5K_SLEEP2_DTIM_PER_S
AR5K_SLEEP2_DTIM_PER_S
AR5K_SLEEP2_TIM_PER	Mask for TIM period (?)
AR5K_SLEEP2_TIM_PER	Mask for TIM period (?)
AR5K_SLEEP2_TIM_PER_S
AR5K_SLEEP2_TIM_PER_S
AR5K_SLOT_TIME
AR5K_SLOT_TIME
AR5K_SLOT_TIME_20
AR5K_SLOT_TIME_20
AR5K_SLOT_TIME_9
AR5K_SLOT_TIME_9
AR5K_SLOT_TIME_MAX
AR5K_SLOT_TIME_MAX
AR5K_SOFTLED_OFF
AR5K_SOFTLED_OFF
AR5K_SOFTLED_ON
AR5K_SOFTLED_ON
AR5K_SOFTLED_PIN
AR5K_SOFTLED_PIN
AR5K_SREV	Register Address
AR5K_SREV	Register Address
AR5K_SREV_AR2413	Griffin lite
AR5K_SREV_AR2413	Griffin lite
AR5K_SREV_AR2414	Griffin
AR5K_SREV_AR2414	Griffin
AR5K_SREV_AR2415	Talon
AR5K_SREV_AR2415	Talon
AR5K_SREV_AR2417	Nala
AR5K_SREV_AR2417	Nala
AR5K_SREV_AR2425	Swan
AR5K_SREV_AR2425	Swan
AR5K_SREV_AR5210	Crete
AR5K_SREV_AR5210	Crete
AR5K_SREV_AR5211	Oahu
AR5K_SREV_AR5211	Oahu
AR5K_SREV_AR5212	Venice
AR5K_SREV_AR5212	Venice
AR5K_SREV_AR5213	???
AR5K_SREV_AR5213	???
AR5K_SREV_AR5213A	Hainan
AR5K_SREV_AR5213A	Hainan
AR5K_SREV_AR5311	Maui 1
AR5K_SREV_AR5311	Maui 1
AR5K_SREV_AR5311A	Maui 2
AR5K_SREV_AR5311A	Maui 2
AR5K_SREV_AR5311B	Spirit
AR5K_SREV_AR5311B	Spirit
AR5K_SREV_AR5413	Eagle lite
AR5K_SREV_AR5413	Eagle lite
AR5K_SREV_AR5414	Eagle
AR5K_SREV_AR5414	Eagle
AR5K_SREV_AR5416	PCI-E
AR5K_SREV_AR5416	PCI-E
AR5K_SREV_AR5418	PCI-E
AR5K_SREV_AR5418	PCI-E
AR5K_SREV_AR5424	Condor
AR5K_SREV_AR5424	Condor
AR5K_SREV_PHY_2413
AR5K_SREV_PHY_2413
AR5K_SREV_PHY_2425
AR5K_SREV_PHY_2425
AR5K_SREV_PHY_5211
AR5K_SREV_PHY_5211
AR5K_SREV_PHY_5212
AR5K_SREV_PHY_5212
AR5K_SREV_PHY_5212A
AR5K_SREV_PHY_5212A
AR5K_SREV_PHY_5212B
AR5K_SREV_PHY_5212B
AR5K_SREV_PHY_5413
AR5K_SREV_PHY_5413
AR5K_SREV_RAD_2111
AR5K_SREV_RAD_2111
AR5K_SREV_RAD_2112
AR5K_SREV_RAD_2112
AR5K_SREV_RAD_2112A
AR5K_SREV_RAD_2112A
AR5K_SREV_RAD_2112B
AR5K_SREV_RAD_2112B
AR5K_SREV_RAD_2316	Cobra SoC
AR5K_SREV_RAD_2316	Cobra SoC
AR5K_SREV_RAD_2317
AR5K_SREV_RAD_2317
AR5K_SREV_RAD_2413
AR5K_SREV_RAD_2413
AR5K_SREV_RAD_2425
AR5K_SREV_RAD_2425
AR5K_SREV_RAD_5110
AR5K_SREV_RAD_5110
AR5K_SREV_RAD_5111
AR5K_SREV_RAD_5111
AR5K_SREV_RAD_5111A
AR5K_SREV_RAD_5111A
AR5K_SREV_RAD_5112
AR5K_SREV_RAD_5112
AR5K_SREV_RAD_5112A
AR5K_SREV_RAD_5112A
AR5K_SREV_RAD_5112B
AR5K_SREV_RAD_5112B
AR5K_SREV_RAD_5133
AR5K_SREV_RAD_5133
AR5K_SREV_RAD_5413
AR5K_SREV_RAD_5413
AR5K_SREV_RAD_5424	Mostly same as 5413
AR5K_SREV_RAD_5424	Mostly same as 5413
AR5K_SREV_REV	Mask for revision
AR5K_SREV_REV	Mask for revision
AR5K_SREV_REV_S
AR5K_SREV_REV_S
AR5K_SREV_UNKNOWN
AR5K_SREV_UNKNOWN
AR5K_SREV_VER	Mask for version
AR5K_SREV_VER	Mask for version
AR5K_SREV_VER_S
AR5K_SREV_VER_S
AR5K_STA_ID0
AR5K_STA_ID0
AR5K_STA_ID0_ARRD_L32
AR5K_STA_ID0_ARRD_L32
AR5K_STA_ID1	Register Address
AR5K_STA_ID1	Register Address
AR5K_STA_ID1_ACKCTS_6MB	Use 6Mbit/s for ACK/CTS
AR5K_STA_ID1_ACKCTS_6MB	Use 6Mbit/s for ACK/CTS
AR5K_STA_ID1_ADDR_U16	Upper 16 bits of MAC addres
AR5K_STA_ID1_ADDR_U16	Upper 16 bits of MAC addres
AR5K_STA_ID1_ADHOC	Set Ad-Hoc mode
AR5K_STA_ID1_ADHOC	Set Ad-Hoc mode
AR5K_STA_ID1_AP	Set AP mode
AR5K_STA_ID1_AP	Set AP mode
AR5K_STA_ID1_BASE_RATE_11B	Use 11b base rate for ACK/CTS [5211+]
AR5K_STA_ID1_BASE_RATE_11B	Use 11b base rate for ACK/CTS [5211+]
AR5K_STA_ID1_CBCIV_ENDIAN	???
AR5K_STA_ID1_CBCIV_ENDIAN	???
AR5K_STA_ID1_CRYPT_MIC_EN	Enable MIC
AR5K_STA_ID1_CRYPT_MIC_EN	Enable MIC
AR5K_STA_ID1_DEFAULT_ANTENNA	Use default antenna
AR5K_STA_ID1_DEFAULT_ANTENNA	Use default antenna
AR5K_STA_ID1_DESC_ANTENNA	Update antenna from descriptor
AR5K_STA_ID1_DESC_ANTENNA	Update antenna from descriptor
AR5K_STA_ID1_KEYSRCH_MCAST	Do key cache search for mcast frames
AR5K_STA_ID1_KEYSRCH_MCAST	Do key cache search for mcast frames
AR5K_STA_ID1_KEYSRCH_MODE	Look up key when key id != 0
AR5K_STA_ID1_KEYSRCH_MODE	Look up key when key id != 0
AR5K_STA_ID1_NO_KEYSRCH	No key search
AR5K_STA_ID1_NO_KEYSRCH	No key search
AR5K_STA_ID1_NO_PSPOLL	No power save polling [5210]
AR5K_STA_ID1_NO_PSPOLL	No power save polling [5210]
AR5K_STA_ID1_PCF
AR5K_STA_ID1_PCF
AR5K_STA_ID1_PCF_5210	Enable PCF on [5210]
AR5K_STA_ID1_PCF_5210	Enable PCF on [5210]
AR5K_STA_ID1_PCF_5211	Enable PCF on [5211+]
AR5K_STA_ID1_PCF_5211	Enable PCF on [5211+]
AR5K_STA_ID1_PRESERVE_SEQ_NUM	Preserve sequence number
AR5K_STA_ID1_PRESERVE_SEQ_NUM	Preserve sequence number
AR5K_STA_ID1_PWR_SV	Power save reporting
AR5K_STA_ID1_PWR_SV	Power save reporting
AR5K_STA_ID1_RTS_DEF_ANTENNA	Use default antenna for RTS
AR5K_STA_ID1_RTS_DEF_ANTENNA	Use default antenna for RTS
AR5K_STA_ID1_SELFGEN_DEF_ANT	Use def. antenna for self generated frames
AR5K_STA_ID1_SELFGEN_DEF_ANT	Use def. antenna for self generated frames
AR5K_TIME_OUT	Register Address
AR5K_TIME_OUT	Register Address
AR5K_TIME_OUT_ACK	ACK timeout mask
AR5K_TIME_OUT_ACK	ACK timeout mask
AR5K_TIME_OUT_ACK_S
AR5K_TIME_OUT_ACK_S
AR5K_TIME_OUT_CTS	CTS timeout mask
AR5K_TIME_OUT_CTS	CTS timeout mask
AR5K_TIME_OUT_CTS_S
AR5K_TIME_OUT_CTS_S
AR5K_TIMER0
AR5K_TIMER0
AR5K_TIMER0_5210
AR5K_TIMER0_5210
AR5K_TIMER0_5211
AR5K_TIMER0_5211
AR5K_TIMER1
AR5K_TIMER1
AR5K_TIMER1_5210
AR5K_TIMER1_5210
AR5K_TIMER1_5211
AR5K_TIMER1_5211
AR5K_TIMER2
AR5K_TIMER2
AR5K_TIMER2_5210
AR5K_TIMER2_5210
AR5K_TIMER2_5211
AR5K_TIMER2_5211
AR5K_TIMER3
AR5K_TIMER3
AR5K_TIMER3_5210
AR5K_TIMER3_5210
AR5K_TIMER3_5211
AR5K_TIMER3_5211
AR5K_TOPS
AR5K_TOPS
AR5K_TOPS_M
AR5K_TOPS_M
AR5K_TPC
AR5K_TPC
AR5K_TPC_ACK	ack frames
AR5K_TPC_ACK	ack frames
AR5K_TPC_ACK_S
AR5K_TPC_ACK_S
AR5K_TPC_CHIRP	chirp frames
AR5K_TPC_CHIRP	chirp frames
AR5K_TPC_CHIRP_S
AR5K_TPC_CHIRP_S
AR5K_TPC_CTS	cts frames
AR5K_TPC_CTS	cts frames
AR5K_TPC_CTS_S
AR5K_TPC_CTS_S
AR5K_TPC_DOPPLER	doppler chirp span
AR5K_TPC_DOPPLER	doppler chirp span
AR5K_TPC_DOPPLER_S
AR5K_TPC_DOPPLER_S
AR5K_TRIG_LVL
AR5K_TRIG_LVL
AR5K_TSF_L32
AR5K_TSF_L32
AR5K_TSF_L32_5210
AR5K_TSF_L32_5210
AR5K_TSF_L32_5211
AR5K_TSF_L32_5211
AR5K_TSF_PARM	Register Address
AR5K_TSF_PARM	Register Address
AR5K_TSF_PARM_INC	Mask for TSF increment
AR5K_TSF_PARM_INC	Mask for TSF increment
AR5K_TSF_PARM_INC_S
AR5K_TSF_PARM_INC_S
AR5K_TSF_THRES
AR5K_TSF_THRES
AR5K_TSF_U32
AR5K_TSF_U32
AR5K_TSF_U32_5210
AR5K_TSF_U32_5210
AR5K_TSF_U32_5211
AR5K_TSF_U32_5211
AR5K_TUNE_ADDITIONAL_SWBA_BACKO
AR5K_TUNE_ADDITIONAL_SWBA_BACKO
AR5K_TUNE_AIFS
AR5K_TUNE_AIFS
AR5K_TUNE_AIFS_11B
AR5K_TUNE_AIFS_11B
AR5K_TUNE_AIFS_XR
AR5K_TUNE_AIFS_XR
AR5K_TUNE_ANT_DIVERSITY
AR5K_TUNE_ANT_DIVERSITY
AR5K_TUNE_BEACON_INTERVAL
AR5K_TUNE_BEACON_INTERVAL
AR5K_TUNE_BMISS_THRES
AR5K_TUNE_BMISS_THRES
AR5K_TUNE_CWMAX
AR5K_TUNE_CWMAX
AR5K_TUNE_CWMAX_11B
AR5K_TUNE_CWMAX_11B
AR5K_TUNE_CWMAX_XR
AR5K_TUNE_CWMAX_XR
AR5K_TUNE_CWMIN
AR5K_TUNE_CWMIN
AR5K_TUNE_CWMIN_11B
AR5K_TUNE_CWMIN_11B
AR5K_TUNE_CWMIN_XR
AR5K_TUNE_CWMIN_XR
AR5K_TUNE_DEFAULT_TXPOWER
AR5K_TUNE_DEFAULT_TXPOWER
AR5K_TUNE_DMA_BEACON_RESP
AR5K_TUNE_DMA_BEACON_RESP
AR5K_TUNE_HWTXTRIES
AR5K_TUNE_HWTXTRIES
AR5K_TUNE_MAX_TX_FIFO_THRES
AR5K_TUNE_MAX_TX_FIFO_THRES
AR5K_TUNE_MAX_TXPOWER
AR5K_TUNE_MAX_TXPOWER
AR5K_TUNE_MIN_TX_FIFO_THRES
AR5K_TUNE_MIN_TX_FIFO_THRES
AR5K_TUNE_NOISE_FLOOR
AR5K_TUNE_NOISE_FLOOR
AR5K_TUNE_RADAR_ALERT
AR5K_TUNE_RADAR_ALERT
AR5K_TUNE_REGISTER_DWELL_TIME
AR5K_TUNE_REGISTER_DWELL_TIME
AR5K_TUNE_REGISTER_TIMEOUT
AR5K_TUNE_REGISTER_TIMEOUT
AR5K_TUNE_RSSI_THRES
AR5K_TUNE_RSSI_THRES
AR5K_TUNE_SW_BEACON_RESP
AR5K_TUNE_SW_BEACON_RESP
AR5K_TUNE_TPC_TXPOWER
AR5K_TUNE_TPC_TXPOWER
AR5K_TX_MASK0
AR5K_TX_MASK0
AR5K_TX_MASK1
AR5K_TX_MASK1
AR5K_TXCFG	Register Address
AR5K_TXCFG	Register Address
AR5K_TXCFG_ADHOC_BCN_ATIM	Adhoc Beacon ATIM Policy
AR5K_TXCFG_ADHOC_BCN_ATIM	Adhoc Beacon ATIM Policy
AR5K_TXCFG_ATIM_WINDOW_DEF_DIS	Disable ATIM window defer [5211+]
AR5K_TXCFG_ATIM_WINDOW_DEF_DIS	Disable ATIM window defer [5211+]
AR5K_TXCFG_B_MODE	Set b mode for 5111 (enable 2111)
AR5K_TXCFG_B_MODE	Set b mode for 5111 (enable 2111)
AR5K_TXCFG_DCU_CACHING_DIS	Disable DCU caching
AR5K_TXCFG_DCU_CACHING_DIS	Disable DCU caching
AR5K_TXCFG_DCU_DBL_BUF_DIS	Disable double buffering on DCU
AR5K_TXCFG_DCU_DBL_BUF_DIS	Disable double buffering on DCU
AR5K_TXCFG_DMASIZE	Flag for passing DMA size [5210]
AR5K_TXCFG_DMASIZE	Flag for passing DMA size [5210]
AR5K_TXCFG_FRMPAD_DIS	[5211+]
AR5K_TXCFG_FRMPAD_DIS	[5211+]
AR5K_TXCFG_JUMBO_DESC_EN	Enable jumbo tx descriptors [5211+]
AR5K_TXCFG_JUMBO_DESC_EN	Enable jumbo tx descriptors [5211+]
AR5K_TXCFG_JUMBO_FRM_MODE	Jumbo frame mode [5211+]
AR5K_TXCFG_JUMBO_FRM_MODE	Jumbo frame mode [5211+]
AR5K_TXCFG_RDY_CBR_DIS	Ready time CBR disable [5211+]
AR5K_TXCFG_RDY_CBR_DIS	Ready time CBR disable [5211+]
AR5K_TXCFG_RTSRND	[5211+]
AR5K_TXCFG_RTSRND	[5211+]
AR5K_TXCFG_SDMAMR	DMA size (read)
AR5K_TXCFG_SDMAMR	DMA size (read)
AR5K_TXCFG_SDMAMR_S
AR5K_TXCFG_SDMAMR_S
AR5K_TXCFG_TXCONT_EN
AR5K_TXCFG_TXCONT_EN
AR5K_TXCFG_TXFSTP	TX DMA full Stop [5210]
AR5K_TXCFG_TXFSTP	TX DMA full Stop [5210]
AR5K_TXCFG_TXFULL	TX Triger level mask
AR5K_TXCFG_TXFULL	TX Triger level mask
AR5K_TXCFG_TXFULL_0B
AR5K_TXCFG_TXFULL_0B
AR5K_TXCFG_TXFULL_128B
AR5K_TXCFG_TXFULL_128B
AR5K_TXCFG_TXFULL_192B
AR5K_TXCFG_TXFULL_192B
AR5K_TXCFG_TXFULL_256B
AR5K_TXCFG_TXFULL_256B
AR5K_TXCFG_TXFULL_64B
AR5K_TXCFG_TXFULL_64B
AR5K_TXCFG_TXFULL_S
AR5K_TXCFG_TXFULL_S
AR5K_TXDESC_CLRDMASK
AR5K_TXDESC_CLRDMASK
AR5K_TXDESC_CTSENA
AR5K_TXDESC_CTSENA
AR5K_TXDESC_INTREQ
AR5K_TXDESC_INTREQ
AR5K_TXDESC_NOACK	[5211+]
AR5K_TXDESC_NOACK	[5211+]
AR5K_TXDESC_RTSENA
AR5K_TXDESC_RTSENA
AR5K_TXDESC_VEOL	[5211+]
AR5K_TXDESC_VEOL	[5211+]
AR5K_TXEPOST
AR5K_TXEPOST
AR5K_TXERR_FIFO
AR5K_TXERR_FIFO
AR5K_TXERR_FILT
AR5K_TXERR_FILT
AR5K_TXERR_XRETRY
AR5K_TXERR_XRETRY
AR5K_TXKEYIX_INVALID
AR5K_TXKEYIX_INVALID
AR5K_TXNOFRM
AR5K_TXNOFRM
AR5K_TXNOFRM_M
AR5K_TXNOFRM_M
AR5K_TXNOFRM_QCU
AR5K_TXNOFRM_QCU
AR5K_TXNOFRM_QCU_S
AR5K_TXNOFRM_QCU_S
AR5K_TXPC	Register Address
AR5K_TXPC	Register Address
AR5K_TXPC_ACK_M	ACK tx power
AR5K_TXPC_ACK_M	ACK tx power
AR5K_TXPC_ACK_S
AR5K_TXPC_ACK_S
AR5K_TXPC_CHIRP_M	CHIRP tx power
AR5K_TXPC_CHIRP_M	CHIRP tx power
AR5K_TXPC_CHIRP_S
AR5K_TXPC_CHIRP_S
AR5K_TXPC_CTS_M	CTS tx power
AR5K_TXPC_CTS_M	CTS tx power
AR5K_TXPC_CTS_S
AR5K_TXPC_CTS_S
AR5K_TXPC_DOPPLER	Doppler chirp span (?)
AR5K_TXPC_DOPPLER	Doppler chirp span (?)
AR5K_TXPC_DOPPLER_S
AR5K_TXPC_DOPPLER_S
AR5K_TXPOWER_CCK(_r, _v)
AR5K_TXPOWER_CCK(_r, _v)
AR5K_TXPOWER_OFDM(_r, _v)
AR5K_TXPOWER_OFDM(_r, _v)
AR5K_TXQ_FLAG_BACKOFF_DISABLE	Disable random post-backoff
AR5K_TXQ_FLAG_BACKOFF_DISABLE	Disable random post-backoff
AR5K_TXQ_FLAG_CBRORNINT_ENABLE	Enable CBRORN interrupt
AR5K_TXQ_FLAG_CBRORNINT_ENABLE	Enable CBRORN interrupt
AR5K_TXQ_FLAG_CBRURNINT_ENABLE	Enable CBRURN interrupt
AR5K_TXQ_FLAG_CBRURNINT_ENABLE	Enable CBRURN interrupt
AR5K_TXQ_FLAG_COMPRESSION_ENABL	Enable hw compression -not implemented-
AR5K_TXQ_FLAG_COMPRESSION_ENABL	Enable hw compression -not implemented-
AR5K_TXQ_FLAG_FRAG_BURST_BACKOF	Enable backoff while bursting
AR5K_TXQ_FLAG_FRAG_BURST_BACKOF	Enable backoff while bursting
AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS	Disable backoff while bursting
AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS	Disable backoff while bursting
AR5K_TXQ_FLAG_QTRIGINT_ENABLE	Enable QTRIG interrupt
AR5K_TXQ_FLAG_QTRIGINT_ENABLE	Enable QTRIG interrupt
AR5K_TXQ_FLAG_RDYTIME_EXP_POLIC	Enable ready time expiry policy (?)
AR5K_TXQ_FLAG_RDYTIME_EXP_POLIC	Enable ready time expiry policy (?)
AR5K_TXQ_FLAG_TXDESCINT_ENABLE	Enable TXDESC interrupt -not used-
AR5K_TXQ_FLAG_TXDESCINT_ENABLE	Enable TXDESC interrupt -not used-
AR5K_TXQ_FLAG_TXEOLINT_ENABLE	Enable TXEOL interrupt -not used-
AR5K_TXQ_FLAG_TXEOLINT_ENABLE	Enable TXEOL interrupt -not used-
AR5K_TXQ_FLAG_TXERRINT_ENABLE	Enable TXERR interrupt
AR5K_TXQ_FLAG_TXERRINT_ENABLE	Enable TXERR interrupt
AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE	Enable TXNOFRM interrupt
AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE	Enable TXNOFRM interrupt
AR5K_TXQ_FLAG_TXOKINT_ENABLE	Enable TXOK interrupt
AR5K_TXQ_FLAG_TXOKINT_ENABLE	Enable TXOK interrupt
AR5K_TXQ_FLAG_TXURNINT_ENABLE	Enable TXURN interrupt
AR5K_TXQ_FLAG_TXURNINT_ENABLE	Enable TXURN interrupt
AR5K_TXQ_USEDEFAULT
AR5K_TXQ_USEDEFAULT
AR5K_TXSTAT_ALTRATE
AR5K_TXSTAT_ALTRATE
AR5K_USEC
AR5K_USEC
AR5K_USEC_1	clock cycles for 1us
AR5K_USEC_1	clock cycles for 1us
AR5K_USEC_1_S
AR5K_USEC_1_S
AR5K_USEC_32	clock cycles for 1us while on 32Mhz clock
AR5K_USEC_32	clock cycles for 1us while on 32Mhz clock
AR5K_USEC_32_S
AR5K_USEC_32_S
AR5K_USEC_5210	Register Address [5210]
AR5K_USEC_5210	Register Address [5210]
AR5K_USEC_5211	Register Address [5211+]
AR5K_USEC_5211	Register Address [5211+]
AR5K_USEC_RX_LATENCY_5210	also for 5311
AR5K_USEC_RX_LATENCY_5210	also for 5311
AR5K_USEC_RX_LATENCY_5210_S
AR5K_USEC_RX_LATENCY_5210_S
AR5K_USEC_RX_LATENCY_5211
AR5K_USEC_RX_LATENCY_5211
AR5K_USEC_RX_LATENCY_5211_S
AR5K_USEC_RX_LATENCY_5211_S
AR5K_USEC_TX_LATENCY_5210	also for 5311
AR5K_USEC_TX_LATENCY_5210	also for 5311
AR5K_USEC_TX_LATENCY_5210_S
AR5K_USEC_TX_LATENCY_5210_S
AR5K_USEC_TX_LATENCY_5211
AR5K_USEC_TX_LATENCY_5211
AR5K_USEC_TX_LATENCY_5211_S
AR5K_USEC_TX_LATENCY_5211_S
AR5K_WOW_PAT_DATA	Register Address
AR5K_WOW_PAT_DATA	Register Address
AR5K_WOW_PAT_DATA_0_3_M	Pattern 0, 3 mask
AR5K_WOW_PAT_DATA_0_3_M	Pattern 0, 3 mask
AR5K_WOW_PAT_DATA_0_3_V	Pattern 0, 3 value
AR5K_WOW_PAT_DATA_0_3_V	Pattern 0, 3 value
AR5K_WOW_PAT_DATA_1_4_M	Pattern 1, 4 mask
AR5K_WOW_PAT_DATA_1_4_M	Pattern 1, 4 mask
AR5K_WOW_PAT_DATA_1_4_V	Pattern 1, 4 value
AR5K_WOW_PAT_DATA_1_4_V	Pattern 1, 4 value
AR5K_WOW_PAT_DATA_2_5_M	Pattern 2, 5 mask
AR5K_WOW_PAT_DATA_2_5_M	Pattern 2, 5 mask
AR5K_WOW_PAT_DATA_2_5_V	Pattern 2, 5 value
AR5K_WOW_PAT_DATA_2_5_V	Pattern 2, 5 value
AR5K_WOW_PAT_IDX
AR5K_WOW_PAT_IDX
AR5K_WOW_PCFG	Register Address
AR5K_WOW_PCFG	Register Address
AR5K_WOW_PCFG_LONG_FRAME_POL	Long frame policy
AR5K_WOW_PCFG_LONG_FRAME_POL	Long frame policy
AR5K_WOW_PCFG_PAT_0_EN	Enable pattern 0
AR5K_WOW_PCFG_PAT_0_EN	Enable pattern 0
AR5K_WOW_PCFG_PAT_1_EN	Enable pattern 1
AR5K_WOW_PCFG_PAT_1_EN	Enable pattern 1
AR5K_WOW_PCFG_PAT_2_EN	Enable pattern 2
AR5K_WOW_PCFG_PAT_2_EN	Enable pattern 2
AR5K_WOW_PCFG_PAT_3_EN	Enable pattern 3
AR5K_WOW_PCFG_PAT_3_EN	Enable pattern 3
AR5K_WOW_PCFG_PAT_4_EN	Enable pattern 4
AR5K_WOW_PCFG_PAT_4_EN	Enable pattern 4
AR5K_WOW_PCFG_PAT_5_EN	Enable pattern 5
AR5K_WOW_PCFG_PAT_5_EN	Enable pattern 5
AR5K_WOW_PCFG_PAT_MATCH_EN	Pattern match enable
AR5K_WOW_PCFG_PAT_MATCH_EN	Pattern match enable
AR5K_WOW_PCFG_WOBMISS	Wake on bea(con) miss (?)
AR5K_WOW_PCFG_WOBMISS	Wake on bea(con) miss (?)
AR5K_XRCHIRP	Register Address
AR5K_XRCHIRP	Register Address
AR5K_XRCHIRP_GAP	Mask for CHIRP gap (?)
AR5K_XRCHIRP_GAP	Mask for CHIRP gap (?)
AR5K_XRCHIRP_SEND	Send CHIRP
AR5K_XRCHIRP_SEND	Send CHIRP
AR5K_XRDELAY	Register Address
AR5K_XRDELAY	Register Address
AR5K_XRDELAY_CHIRP_DELAY_M	Mask for CHIRP data delay
AR5K_XRDELAY_CHIRP_DELAY_M	Mask for CHIRP data delay
AR5K_XRDELAY_CHIRP_DELAY_S
AR5K_XRDELAY_CHIRP_DELAY_S
AR5K_XRDELAY_SLOT_DELAY_M	Mask for slot delay
AR5K_XRDELAY_SLOT_DELAY_M	Mask for slot delay
AR5K_XRDELAY_SLOT_DELAY_S
AR5K_XRDELAY_SLOT_DELAY_S
AR5K_XRLAT_TX
AR5K_XRLAT_TX
AR5K_XRMODE	Register Address
AR5K_XRMODE	Register Address
AR5K_XRMODE_FRAME_HOLD_M	Mask for frame hold (?)
AR5K_XRMODE_FRAME_HOLD_M	Mask for frame hold (?)
AR5K_XRMODE_FRAME_HOLD_S
AR5K_XRMODE_FRAME_HOLD_S
AR5K_XRMODE_POLL_SUBTYPE_M	Mask for Poll subtype (?)
AR5K_XRMODE_POLL_SUBTYPE_M	Mask for Poll subtype (?)
AR5K_XRMODE_POLL_SUBTYPE_S
AR5K_XRMODE_POLL_SUBTYPE_S
AR5K_XRMODE_POLL_TYPE_M	Mask for Poll type (?)
AR5K_XRMODE_POLL_TYPE_M	Mask for Poll type (?)
AR5K_XRMODE_POLL_TYPE_S
AR5K_XRMODE_POLL_TYPE_S
AR5K_XRMODE_POLL_WAIT_ALL	Wait for poll
AR5K_XRMODE_POLL_WAIT_ALL	Wait for poll
AR5K_XRMODE_SIFS_DELAY	Mask for SIFS delay
AR5K_XRMODE_SIFS_DELAY	Mask for SIFS delay
AR5K_XRSTOMP	Register Address
AR5K_XRSTOMP	Register Address
AR5K_XRSTOMP_DATA	Stomp data (?)
AR5K_XRSTOMP_DATA	Stomp data (?)
AR5K_XRSTOMP_RSSI_THRES	Mask for XR RSSI threshold
AR5K_XRSTOMP_RSSI_THRES	Mask for XR RSSI threshold
AR5K_XRSTOMP_RX	Stomp Rx (?)
AR5K_XRSTOMP_RX	Stomp Rx (?)
AR5K_XRSTOMP_TX	Stomp Tx (?)
AR5K_XRSTOMP_TX	Stomp Tx (?)
AR5K_XRSTOMP_TX_BSSID	Stomp Tx BSSID (?)
AR5K_XRSTOMP_TX_BSSID	Stomp Tx BSSID (?)
AR5K_XRSTOMP_TX_RSSI	Stomp Tx RSSI (?)
AR5K_XRSTOMP_TX_RSSI	Stomp Tx RSSI (?)
AR5K_XRTIMEOUT	Register Address
AR5K_XRTIMEOUT	Register Address
AR5K_XRTIMEOUT_CHIRP_M	Mask for CHIRP timeout
AR5K_XRTIMEOUT_CHIRP_M	Mask for CHIRP timeout
AR5K_XRTIMEOUT_CHIRP_S
AR5K_XRTIMEOUT_CHIRP_S
AR5K_XRTIMEOUT_POLL_M	Mask for Poll timeout
AR5K_XRTIMEOUT_POLL_M	Mask for Poll timeout
AR5K_XRTIMEOUT_POLL_S
AR5K_XRTIMEOUT_POLL_S
arbel
arbel
arbel.c
arbel.c
arbel.h
arbel.h
arbel_alloc_icm	Allocate ICM
arbel_alloc_icm	Allocate ICM
arbel_alloc_qn_offset	@file
arbel_alloc_qn_offset	@file
ARBEL_BITMASK_SIZE(max_entries)
ARBEL_BITMASK_SIZE(max_entries)
arbel_close	Close Infiniband link
arbel_close	Close Infiniband link
arbel_cmd	Issue HCA command
arbel_cmd	Issue HCA command
arbel_cmd_2rst_qpee
arbel_cmd_2rst_qpee
arbel_cmd_close_hca
arbel_cmd_close_hca
arbel_cmd_close_ib
arbel_cmd_close_ib
arbel_cmd_disable_lam
arbel_cmd_disable_lam
arbel_cmd_enable_lam
arbel_cmd_enable_lam
arbel_cmd_hw2sw_cq
arbel_cmd_hw2sw_cq
arbel_cmd_hw2sw_eq
arbel_cmd_hw2sw_eq
arbel_cmd_init_hca
arbel_cmd_init_hca
arbel_cmd_init_ib
arbel_cmd_init_ib
arbel_cmd_init2rtr_qpee
arbel_cmd_init2rtr_qpee
arbel_cmd_mad_ifc
arbel_cmd_mad_ifc
arbel_cmd_map_eq
arbel_cmd_map_eq
arbel_cmd_map_fa
arbel_cmd_map_fa
arbel_cmd_map_icm
arbel_cmd_map_icm
arbel_cmd_map_icm_aux
arbel_cmd_map_icm_aux
arbel_cmd_mgid_hash
arbel_cmd_mgid_hash
arbel_cmd_query_dev_lim
arbel_cmd_query_dev_lim
arbel_cmd_query_fw
arbel_cmd_query_fw
arbel_cmd_read_mgm
arbel_cmd_read_mgm
arbel_cmd_rst2init_qpee
arbel_cmd_rst2init_qpee
arbel_cmd_rtr2rts_qpee
arbel_cmd_rtr2rts_qpee
arbel_cmd_rts2rts_qp
arbel_cmd_rts2rts_qp
arbel_cmd_run_fw
arbel_cmd_run_fw
arbel_cmd_set_icm_size
arbel_cmd_set_icm_size
arbel_cmd_sw2hw_cq
arbel_cmd_sw2hw_cq
arbel_cmd_sw2hw_eq
arbel_cmd_sw2hw_eq
arbel_cmd_sw2hw_mpt
arbel_cmd_sw2hw_mpt
arbel_cmd_unmap_fa
arbel_cmd_unmap_fa
arbel_cmd_unmap_icm
arbel_cmd_unmap_icm
arbel_cmd_unmap_icm_aux
arbel_cmd_unmap_icm_aux
arbel_cmd_wait	HCA commands
arbel_cmd_wait	HCA commands
arbel_cmd_write_mgm
arbel_cmd_write_mgm
arbel_complete	Handle completion
arbel_complete	Handle completion
arbel_completion_queue
arbel_completion_queue
arbel_create_cq	Completion queue operations
arbel_create_cq	Completion queue operations
arbel_create_eq	Event queues
arbel_create_eq	Event queues
arbel_create_qp	Create queue pair
arbel_create_qp	Create queue pair
arbel_create_recv_wq	Create receive work queue
arbel_create_recv_wq	Create receive work queue
arbel_create_send_wq	Queue pair operations
arbel_create_send_wq	Queue pair operations
ARBEL_DB_EQ_OFFSET(_eqn)
ARBEL_DB_EQ_OFFSET(_eqn)
ARBEL_DB_POST_SND_OFFSET
ARBEL_DB_POST_SND_OFFSET
arbel_destroy_cq	Destroy completion queue
arbel_destroy_cq	Destroy completion queue
arbel_destroy_eq	Destroy event queue
arbel_destroy_eq	Destroy event queue
arbel_destroy_qp	Destroy queue pair
arbel_destroy_qp	Destroy queue pair
arbel_dev_limits
arbel_dev_limits
ARBEL_EV_PORT_STATE_CHANGE
ARBEL_EV_PORT_STATE_CHANGE
arbel_event_port_state_change	Handle port state event
arbel_event_port_state_change	Handle port state event
arbel_event_queue
arbel_event_queue
arbel_free_icm	Free ICM
arbel_free_icm	Free ICM
arbel_free_qn_offset	Free queue number
arbel_free_qn_offset	Free queue number
arbel_get_limits	Infinihost Context Memory management
arbel_get_limits	Infinihost Context Memory management
ARBEL_GLOBAL_PD
ARBEL_GLOBAL_PD
ARBEL_GROUP_SEPARATOR_DOORBELL
ARBEL_GROUP_SEPARATOR_DOORBELL
ARBEL_HCR_2RST_QPEE
ARBEL_HCR_2RST_QPEE
ARBEL_HCR_BASE
ARBEL_HCR_BASE
ARBEL_HCR_CLOSE_HCA
ARBEL_HCR_CLOSE_HCA
ARBEL_HCR_CLOSE_IB
ARBEL_HCR_CLOSE_IB
ARBEL_HCR_DISABLE_LAM
ARBEL_HCR_DISABLE_LAM
ARBEL_HCR_ENABLE_LAM
ARBEL_HCR_ENABLE_LAM
ARBEL_HCR_HW2SW_CQ
ARBEL_HCR_HW2SW_CQ
ARBEL_HCR_HW2SW_EQ
ARBEL_HCR_HW2SW_EQ
ARBEL_HCR_IN_CMD( _opcode, _in_mbox, _in_len )
ARBEL_HCR_IN_CMD( _opcode, _in_mbox, _in_len )
ARBEL_HCR_IN_LEN( _command )
ARBEL_HCR_IN_LEN( _command )
ARBEL_HCR_IN_MBOX
ARBEL_HCR_IN_MBOX
ARBEL_HCR_INIT_HCA
ARBEL_HCR_INIT_HCA
ARBEL_HCR_INIT_IB
ARBEL_HCR_INIT_IB
ARBEL_HCR_INIT2RTR_QPEE
ARBEL_HCR_INIT2RTR_QPEE
ARBEL_HCR_INOUT_CMD( _opcode, _in_mbox, _in_len, \ _out_mbox, _out_len )
ARBEL_HCR_INOUT_CMD( _opcode, _in_mbox, _in_len, \ _out_mbox, _out_len )
ARBEL_HCR_MAD_IFC
ARBEL_HCR_MAD_IFC
ARBEL_HCR_MAP_EQ
ARBEL_HCR_MAP_EQ
ARBEL_HCR_MAP_FA
ARBEL_HCR_MAP_FA
ARBEL_HCR_MAP_ICM
ARBEL_HCR_MAP_ICM
ARBEL_HCR_MAP_ICM_AUX
ARBEL_HCR_MAP_ICM_AUX
ARBEL_HCR_MAX_WAIT_MS
ARBEL_HCR_MAX_WAIT_MS
ARBEL_HCR_MGID_HASH
ARBEL_HCR_MGID_HASH
ARBEL_HCR_OPCODE( _command )
ARBEL_HCR_OPCODE( _command )
ARBEL_HCR_OUT_CMD( _opcode, _out_mbox, _out_len )
ARBEL_HCR_OUT_CMD( _opcode, _out_mbox, _out_len )
ARBEL_HCR_OUT_LEN( _command )
ARBEL_HCR_OUT_LEN( _command )
ARBEL_HCR_OUT_MBOX
ARBEL_HCR_OUT_MBOX
ARBEL_HCR_QUERY_DEV_LIM
ARBEL_HCR_QUERY_DEV_LIM
ARBEL_HCR_QUERY_FW
ARBEL_HCR_QUERY_FW
ARBEL_HCR_READ_MGM
ARBEL_HCR_READ_MGM
ARBEL_HCR_REG(x)
ARBEL_HCR_REG(x)
ARBEL_HCR_RST2INIT_QPEE
ARBEL_HCR_RST2INIT_QPEE
ARBEL_HCR_RTR2RTS_QPEE
ARBEL_HCR_RTR2RTS_QPEE
ARBEL_HCR_RTS2RTS_QPEE
ARBEL_HCR_RTS2RTS_QPEE
ARBEL_HCR_RUN_FW
ARBEL_HCR_RUN_FW
ARBEL_HCR_SET_ICM_SIZE
ARBEL_HCR_SET_ICM_SIZE
ARBEL_HCR_SW2HW_CQ
ARBEL_HCR_SW2HW_CQ
ARBEL_HCR_SW2HW_EQ
ARBEL_HCR_SW2HW_EQ
ARBEL_HCR_SW2HW_MPT
ARBEL_HCR_SW2HW_MPT
ARBEL_HCR_UNMAP_FA
ARBEL_HCR_UNMAP_FA
ARBEL_HCR_UNMAP_ICM
ARBEL_HCR_UNMAP_ICM
ARBEL_HCR_UNMAP_ICM_AUX
ARBEL_HCR_UNMAP_ICM_AUX
ARBEL_HCR_VOID_CMD( _opcode )
ARBEL_HCR_VOID_CMD( _opcode )
ARBEL_HCR_WRITE_MGM
ARBEL_HCR_WRITE_MGM
ARBEL_INVALID_LKEY
ARBEL_INVALID_LKEY
arbel_mad	MAD operations
arbel_mad	MAD operations
ARBEL_MAP_EQ
ARBEL_MAP_EQ
ARBEL_MAX_CQS
ARBEL_MAX_CQS
ARBEL_MAX_DOORBELL_RECORDS
ARBEL_MAX_DOORBELL_RECORDS
ARBEL_MAX_EQS
ARBEL_MAX_EQS
ARBEL_MAX_GATHER
ARBEL_MAX_GATHER
ARBEL_MAX_QPS
ARBEL_MAX_QPS
ARBEL_MAX_SCATTER
ARBEL_MAX_SCATTER
ARBEL_MBOX_ALIGN
ARBEL_MBOX_ALIGN
ARBEL_MBOX_SIZE
ARBEL_MBOX_SIZE
arbel_mcast_attach	Multicast group operations
arbel_mcast_attach	Multicast group operations
arbel_mcast_detach	Detach from multicast group
arbel_mcast_detach	Detach from multicast group
ARBEL_MKEY_PREFIX
ARBEL_MKEY_PREFIX
arbel_modify_qp	Modify queue pair
arbel_modify_qp	Modify queue pair
ARBEL_MTU_2048
ARBEL_MTU_2048
ARBEL_NO_EQ
ARBEL_NO_EQ
ARBEL_NUM_EQES
ARBEL_NUM_EQES
ARBEL_NUM_PORTS
ARBEL_NUM_PORTS
ARBEL_OPCODE_RECV_ERROR
ARBEL_OPCODE_RECV_ERROR
ARBEL_OPCODE_SEND
ARBEL_OPCODE_SEND
ARBEL_OPCODE_SEND_ERROR
ARBEL_OPCODE_SEND_ERROR
arbel_open	Infiniband link-layer operations
arbel_open	Infiniband link-layer operations
ARBEL_PAGE_SIZE
ARBEL_PAGE_SIZE
ARBEL_PCI_CONFIG_BAR
ARBEL_PCI_CONFIG_BAR
ARBEL_PCI_CONFIG_BAR_SIZE
ARBEL_PCI_CONFIG_BAR_SIZE
ARBEL_PCI_UAR_BAR
ARBEL_PCI_UAR_BAR
ARBEL_PCI_UAR_IDX
ARBEL_PCI_UAR_IDX
ARBEL_PCI_UAR_SIZE
ARBEL_PCI_UAR_SIZE
arbel_poll_cq	Poll completion queue
arbel_poll_cq	Poll completion queue
arbel_poll_eq	Poll event queue
arbel_poll_eq	Poll event queue
ARBEL_PORT_BASE
ARBEL_PORT_BASE
arbel_post_recv	Post receive work queue entry
arbel_post_recv	Post receive work queue entry
arbel_post_send	Post send work queue entry
arbel_post_send	Post send work queue entry
arbel_probe	Probe PCI device
arbel_probe	Probe PCI device
ARBEL_QPEE_OPT_PARAM_QKEY
ARBEL_QPEE_OPT_PARAM_QKEY
ARBEL_QPN_BASE
ARBEL_QPN_BASE
arbel_queue_pair
arbel_queue_pair
arbel_recv_work_queue
arbel_recv_work_queue
arbel_recv_wqe
arbel_recv_wqe
ARBEL_RECV_WQE_ALIGN
ARBEL_RECV_WQE_ALIGN
arbel_remove	Remove PCI device
arbel_remove	Remove PCI device
arbel_ring_doorbell	Work request operations
arbel_ring_doorbell	Work request operations
arbel_send_work_queue
arbel_send_work_queue
arbel_send_wqe
arbel_send_wqe
ARBEL_SEND_WQE_ALIGN
ARBEL_SEND_WQE_ALIGN
arbel_setup_mpt	PCI interface
arbel_setup_mpt	PCI interface
ARBEL_ST_UD
ARBEL_ST_UD
arbel_start_firmware	Firmware control
arbel_start_firmware	Firmware control
arbel_stop_firmware	Stop firmware running
arbel_stop_firmware	Stop firmware running
ARBEL_UAR_RES_CQ_ARM
ARBEL_UAR_RES_CQ_ARM
ARBEL_UAR_RES_CQ_CI
ARBEL_UAR_RES_CQ_CI
ARBEL_UAR_RES_GROUP_SEP
ARBEL_UAR_RES_GROUP_SEP
ARBEL_UAR_RES_NONE
ARBEL_UAR_RES_NONE
ARBEL_UAR_RES_RQ
ARBEL_UAR_RES_RQ
ARBEL_UAR_RES_SQ
ARBEL_UAR_RES_SQ
ARBEL_UNMAP_EQ
ARBEL_UNMAP_EQ
arbelprm_access_lam_inject_errors_input_modifier_st	Little Endian
arbelprm_access_lam_inject_errors_input_modifier_st	Little Endian
arbelprm_access_lam_inject_errors_input_parameter_st	Little Endian
arbelprm_access_lam_inject_errors_input_parameter_st	Little Endian
arbelprm_access_lam_inject_errors_st	Little Endian
arbelprm_access_lam_inject_errors_st	Little Endian
arbelprm_access_lam_st	Little Endian
arbelprm_access_lam_st	Little Endian
arbelprm_address_path_st	Little Endian
arbelprm_address_path_st	Little Endian
arbelprm_arbel_prm_st	Little Endian
arbelprm_arbel_prm_st	Little Endian
arbelprm_clr_int_st	Little Endian
arbelprm_clr_int_st	Little Endian
arbelprm_completion_entry
arbelprm_completion_entry
arbelprm_completion_event_st	Little Endian
arbelprm_completion_event_st	Little Endian
arbelprm_completion_queue_context_st	Little Endian
arbelprm_completion_queue_context_st	Little Endian
arbelprm_completion_queue_entry_st	Little Endian
arbelprm_completion_queue_entry_st	Little Endian
arbelprm_completion_queue_error_st	Little Endian
arbelprm_completion_queue_error_st	Little Endian
arbelprm_completion_with_error_st	Little Endian
arbelprm_completion_with_error_st	Little Endian
arbelprm_configuration_registers_st	Little Endian
arbelprm_configuration_registers_st	Little Endian
arbelprm_cq_arm_db_record_st	Little Endian
arbelprm_cq_arm_db_record_st	Little Endian
arbelprm_cq_ci_db_record_st	Little Endian
arbelprm_cq_ci_db_record_st	Little Endian
arbelprm_cq_cmd_doorbell_st	Little Endian
arbelprm_cq_cmd_doorbell_st	Little Endian
arbelprm_dimminfo_st	Little Endian
arbelprm_dimminfo_st	Little Endian
arbelprm_doorbell_record
arbelprm_doorbell_record
arbelprm_doorbell_register
arbelprm_doorbell_register
arbelprm_ecc_detect_event_data_st	Little Endian
arbelprm_ecc_detect_event_data_st	Little Endian
arbelprm_enable_lam_st	Little Endian
arbelprm_enable_lam_st	Little Endian
arbelprm_eq_arm_db_region_st	Little Endian
arbelprm_eq_arm_db_region_st	Little Endian
arbelprm_eq_cmd_doorbell_st	Little Endian
arbelprm_eq_cmd_doorbell_st	Little Endian
arbelprm_eq_doorbell_register
arbelprm_eq_doorbell_register
arbelprm_eq_set_ci_st
arbelprm_eq_set_ci_st
arbelprm_eq_set_ci_table_st	Little Endian
arbelprm_eq_set_ci_table_st	Little Endian
arbelprm_eqc_st	Little Endian
arbelprm_eqc_st	Little Endian
arbelprm_event_entry
arbelprm_event_entry
arbelprm_event_mask_st
arbelprm_event_mask_st
arbelprm_event_queue_entry_st	Little Endian
arbelprm_event_queue_entry_st	Little Endian
arbelprm_extended_completion_queue_entry_st	Little Endian
arbelprm_extended_completion_queue_entry_st	Little Endian
arbelprm_fast_registration_segment_st	Little Endian
arbelprm_fast_registration_segment_st	Little Endian
arbelprm_gpio_event_data_st	Little Endian
arbelprm_gpio_event_data_st	Little Endian
arbelprm_hca_command_register_st	Little Endian
arbelprm_hca_command_register_st	Little Endian
arbelprm_hcr_completion_event_st	Little Endian
arbelprm_hcr_completion_event_st	Little Endian
arbelprm_header_log_register_st	Little Endian
arbelprm_header_log_register_st	Little Endian
arbelprm_init_hca_st	Little Endian
arbelprm_init_hca_st	Little Endian
arbelprm_init_ib_st	Little Endian
arbelprm_init_ib_st	Little Endian
arbelprm_lam_en_out_param_st	Little Endian
arbelprm_lam_en_out_param_st	Little Endian
arbelprm_local_invalidate_segment_st	Little Endian
arbelprm_local_invalidate_segment_st	Little Endian
arbelprm_mad
arbelprm_mad
arbelprm_mad_ifc_input_modifier_st	Little Endian
arbelprm_mad_ifc_input_modifier_st	Little Endian
arbelprm_mad_ifc_st	Little Endian
arbelprm_mad_ifc_st	Little Endian
arbelprm_mgm_entry_st	Little Endian
arbelprm_mgm_entry_st	Little Endian
arbelprm_mgm_hash_st
arbelprm_mgm_hash_st
arbelprm_mgmqp_st	Little Endian
arbelprm_mgmqp_st	Little Endian
arbelprm_misc_counters_st	Little Endian
arbelprm_misc_counters_st	Little Endian
arbelprm_mod_stat_cfg_st	Little Endian
arbelprm_mod_stat_cfg_st	Little Endian
arbelprm_mpt_st	Little Endian
arbelprm_mpt_st	Little Endian
arbelprm_mt25208_type0_st	Little Endian
arbelprm_mt25208_type0_st	Little Endian
arbelprm_mtt_st	Little Endian
arbelprm_mtt_st	Little Endian
arbelprm_multicastparam_st	Little Endian
arbelprm_multicastparam_st	Little Endian
arbelprm_page_fault_event_data_st	Little Endian
arbelprm_page_fault_event_data_st	Little Endian
arbelprm_pbl_st	Little Endian
arbelprm_pbl_st	Little Endian
arbelprm_performance_counters_st	Little Endian
arbelprm_performance_counters_st	Little Endian
arbelprm_performance_monitor_event_st	Little Endian
arbelprm_performance_monitor_event_st	Little Endian
arbelprm_performance_monitors_st	Little Endian
arbelprm_performance_monitors_st	Little Endian
arbelprm_port_state_change_event_st
arbelprm_port_state_change_event_st
arbelprm_port_state_change_st	Little Endian
arbelprm_port_state_change_st	Little Endian
arbelprm_qp_db_record_st	Little Endian
arbelprm_qp_db_record_st	Little Endian
arbelprm_qp_ee_event_st	Little Endian
arbelprm_qp_ee_event_st	Little Endian
arbelprm_qp_ee_state_transitions_st	Little Endian
arbelprm_qp_ee_state_transitions_st	Little Endian
arbelprm_qpcbaseaddr_st	Little Endian
arbelprm_qpcbaseaddr_st	Little Endian
arbelprm_query_adapter_st	Little Endian
arbelprm_query_adapter_st	Little Endian
arbelprm_query_debug_msg_st	Little Endian
arbelprm_query_debug_msg_st	Little Endian
arbelprm_query_dev_lim_st	Little Endian
arbelprm_query_dev_lim_st	Little Endian
arbelprm_query_fw_st	Little Endian
arbelprm_query_fw_st	Little Endian
arbelprm_queue_pair_ee_context_entry_st	Little Endian
arbelprm_queue_pair_ee_context_entry_st	Little Endian
arbelprm_rd_send_doorbell_st	Little Endian
arbelprm_rd_send_doorbell_st	Little Endian
arbelprm_receive_doorbell_st	Little Endian
arbelprm_receive_doorbell_st	Little Endian
arbelprm_recv_wqe
arbelprm_recv_wqe
arbelprm_recv_wqe_segment_next_st	Little Endian
arbelprm_recv_wqe_segment_next_st	Little Endian
arbelprm_resize_cq_st	Little Endian
arbelprm_resize_cq_st	Little Endian
arbelprm_scalar_parameter_st
arbelprm_scalar_parameter_st
arbelprm_scrubbing_event_st	Little Endian
arbelprm_scrubbing_event_st	Little Endian
arbelprm_send_doorbell_st	Little Endian
arbelprm_send_doorbell_st	Little Endian
arbelprm_send_wqe_segment_st	Little Endian
arbelprm_send_wqe_segment_st	Little Endian
arbelprm_set_ib_st	Little Endian
arbelprm_set_ib_st	Little Endian
arbelprm_srq_context_st	Little Endian
arbelprm_srq_context_st	Little Endian
arbelprm_tptparams_st	Little Endian
arbelprm_tptparams_st	Little Endian
arbelprm_transport_and_ci_error_counters_st	Little Endian
arbelprm_transport_and_ci_error_counters_st	Little Endian
arbelprm_uar_params_st	Little Endian
arbelprm_uar_params_st	Little Endian
arbelprm_uar_st	Little Endian
arbelprm_uar_st	Little Endian
arbelprm_ud_address_vector_st	Little Endian
arbelprm_ud_address_vector_st	Little Endian
arbelprm_ud_send_wqe
arbelprm_ud_send_wqe
arbelprm_udavtable_memory_parameters_st	Little Endian
arbelprm_udavtable_memory_parameters_st	Little Endian
arbelprm_virtual_physical_mapping_st	Little Endian
arbelprm_virtual_physical_mapping_st	Little Endian
arbelprm_vsd_st	Little Endian
arbelprm_vsd_st	Little Endian
arbelprm_wqe_segment_atomic_st	Little Endian
arbelprm_wqe_segment_atomic_st	Little Endian
arbelprm_wqe_segment_bind_st	Little Endian
arbelprm_wqe_segment_bind_st	Little Endian
arbelprm_wqe_segment_ctrl_mlx_st	Little Endian
arbelprm_wqe_segment_ctrl_mlx_st	Little Endian
arbelprm_wqe_segment_ctrl_recv_st	Little Endian
arbelprm_wqe_segment_ctrl_recv_st	Little Endian
arbelprm_wqe_segment_ctrl_send_st	Little Endian
arbelprm_wqe_segment_ctrl_send_st	Little Endian
arbelprm_wqe_segment_data_inline_st	Little Endian
arbelprm_wqe_segment_data_inline_st	Little Endian
arbelprm_wqe_segment_data_ptr_st	Little Endian
arbelprm_wqe_segment_data_ptr_st	Little Endian
arbelprm_wqe_segment_next_st	Little Endian
arbelprm_wqe_segment_next_st	Little Endian
arbelprm_wqe_segment_rd_st	Little Endian
arbelprm_wqe_segment_rd_st	Little Endian
arbelprm_wqe_segment_remote_address_st	Little Endian
arbelprm_wqe_segment_remote_address_st	Little Endian
arbelprm_wqe_segment_st	Little Endian
arbelprm_wqe_segment_st	Little Endian
arbelprm_wqe_segment_ud_st	Little Endian
arbelprm_wqe_segment_ud_st	Little Endian
arc4.c
arc4_setiv
arc4_setkey	Set ARC4 key
arc4_skip	Perform ARC4 encryption or decryption, skipping initial keystream bytes
arc4_xor	Perform ARC4 encryption or decryption
ARCNET_TYPE	*< ARCNET
arp.c
arp.h
arp_entry
arp_find_entry	Find entry in the ARP cache
arp_find_protocol	Identify ARP protocol
arp_net_protocol
ARP_NET_PROTOCOLS
arp_ntoa	Transcribe ARP address
arp_packet
arp_packet
arp_resolve	Look up media-specific link-layer address in the ARP cache
arp_rx	Process incoming ARP packets
arp_table_end
arphdr
ARPHRD_APPLETLK	*< APPLEtalk
ARPHRD_ARCNET	*< ARCnet
ARPHRD_ATM	*< ATM
ARPHRD_AX25	*< AX.25 Level 2
ARPHRD_CHAOS	*< Chaosnet
ARPHRD_DLCI	*< Frame Relay DLCI
ARPHRD_EETHER	*< Experimental Ethernet
ARPHRD_ETHER	*< Ethernet 10Mbps
ARPHRD_EUI64	*< EUI-64
ARPHRD_IEEE1394	*< IEEE 1394 IPv4 - RFC 2734
ARPHRD_IEEE802	*< IEEE 802.2 Ethernet/TR/TB
ARPHRD_INFINIBAND	*< InfiniBand
ARPHRD_METRICOM	*< Metricom STRIP (new IANA id)
ARPHRD_NETROM	*< from KA9Q: NET/ROM pseudo
ARPHRD_PRONET	*< PROnet token ring
ARPOP_InREPLY	*< InARP reply
ARPOP_InREQUEST	*< InARP request
ARPOP_NAK	*< (ATM)ARP NAK
ARPOP_REPLY	*< ARP reply
ARPOP_REQUEST	*< ARP request
ARPOP_RREPLY	*< RARP reply
ARPOP_RREQUEST	*< RARP request
ARRAY_SIZE(a)
ARRAY_SIZE(a)
ARRAY_SIZE(a)
ARRAY_SIZE(a)
ARRAY_SIZE(arr)
ARRAY_SIZE(x)
ARRAY_SIZE(x)
ARROW_DOWN
ARROW_LEFT
ARROW_RIGHT
ARROW_UP
ASF_STAT	ASF status register
ASF_STAT	ASF status register
ASIC_PIO
ASIC_PIO
ASIC_PIO
ASIC_PIO
ASIC_REV_5700
ASIC_REV_5700
ASIC_REV_5701
ASIC_REV_5701
ASIC_REV_5703
ASIC_REV_5703
ASIC_REV_5704
ASIC_REV_5704
ASIC_REV_5705
ASIC_REV_5705
ASIC_REV_5750
ASIC_REV_5750
ASIC_REV_5787
ASIC_REV_5787
ASICCtrl_HiWord_bit
ASICCtrl_HiWord_bit
ASM_PFX(name)
ASM_PFX(name)
ASM_PFX(name)
ASM_PFX(name)
asn1.c
asn1.c
asn1.h
ASN1_BIT_STRING
asn1_cursor
asn1_enter	Enter ASN.1 object
asn1_enter	Enter ASN.1 object
ASN1_EXPLICIT_TAG
ASN1_INTEGER
ASN1_IP_ADDRESS
ASN1_NULL
ASN1_OCTET_STRING
ASN1_OID
ASN1_SEQUENCE
asn1_skip	Skip ASN.1 object
asn1_skip	Skip ASN.1 object
asn1_start	@file
asn1_start	@file
asprintf	Write a formatted string to newly allocated memory.
asprintf	Write a formatted string to newly allocated memory.
asprintf.c
asprintf.c
assert( condition )
ASSERT(x)
ASSERT(x)
ASSERT(x)
ASSERT(x)
assert.h
assert_match
assert_match(a,b,c)
ASSERTING
ASSERTING
ASSOC_RETRIES
ASSOC_TIMEOUT
AT_EEPROM_LEN
AT_EEPROM_LEN
AT_ERR_CONFIG
AT_ERR_CONFIG
AT_ERR_EEPROM
AT_ERR_EEPROM
AT_ERR_MAC_TYPE
AT_ERR_MAC_TYPE
AT_ERR_PARAM
AT_ERR_PARAM
AT_ERR_PHY
AT_ERR_PHY
AT_ERR_PHY_RES
AT_ERR_PHY_RES
AT_ERR_PHY_SPEED
AT_ERR_PHY_SPEED
AT_ERR_PHY_TYPE
AT_ERR_PHY_TYPE
AT_ERR_TIMEOUT
AT_ERR_TIMEOUT
AT_HW_MAX_IDLE_DELAY
AT_HW_MAX_IDLE_DELAY
AT_MAX_RECEIVE_QUEUE
AT_MAX_RECEIVE_QUEUE
AT_PAGE_NUM_PER_QUEUE
AT_PAGE_NUM_PER_QUEUE
AT_READ_REG(a, reg)
AT_READ_REG(a, reg)
AT_READ_REG_ARRAY(a, reg, offset)
AT_READ_REG_ARRAY(a, reg, offset)
AT_READ_REGB(a, reg)
AT_READ_REGB(a, reg)
AT_READ_REGW(a, reg)
AT_READ_REGW(a, reg)
AT_REGS_LEN
AT_REGS_LEN
AT_TWSI_EEPROM_TIMEOUT
AT_TWSI_EEPROM_TIMEOUT
AT_WRITE_FLUSH(a)
AT_WRITE_FLUSH(a)
AT_WRITE_REG(a, reg, value)
AT_WRITE_REG(a, reg, value)
AT_WRITE_REG_ARRAY(a, reg, offset, value)
AT_WRITE_REG_ARRAY(a, reg, offset, value)
AT_WRITE_REGB(a, reg, value)
AT_WRITE_REGB(a, reg, value)
AT_WRITE_REGW(a, reg, value)
AT_WRITE_REGW(a, reg, value)
ata.c
ata.c
ata.h
ata_cb
ATA_CMD_IDENTIFY
ATA_CMD_READ
ATA_CMD_READ_EXT
ATA_CMD_WRITE
ATA_CMD_WRITE_EXT
ata_command
ATA_DEV_LBA
ATA_DEV_MASK
ATA_DEV_MASTER
ATA_DEV_OBSOLETE
ATA_DEV_SLAVE
ata_device
ata_fifo
ata_identify	Identify ATA device
ata_identify	Identify ATA device
ata_identity
ata_lba
ata_read	Read block from ATA device
ata_read	Read block from ATA device
ATA_SECTOR_SIZE
ATA_SUPPORTS_LBA48
ata_write	Write block to ATA device
ata_write	Write block to ATA device
ATAPI_DEVICE_PATH
ATC_COLOR_PAGE
ATC_MODE
ATC_OVERSCAN
ATC_PEL
ATC_PLANE_ENABLE
ATH_CHAN_MAX
ATH_CHAN_MAX
ATH_CHAN_MAX
ATH_CHAN_MAX
ATH_RXBUF	number of RX buffers
ATH_RXBUF	number of RX buffers
ATH_TXBUF	number of TX buffers
ATH_TXBUF	number of TX buffers
ath5k.c
ath5k.c
ath5k.h
ath5k.h
ath5k_ant_setting
ath5k_ant_setting
ath5k_athchan_2ghz
ath5k_athchan_2ghz
ath5k_attach	*********************\
ath5k_attach	*********************\
ath5k_attach.c
ath5k_attach.c
ath5k_bitrate_to_hw_rix
ath5k_bitrate_to_hw_rix
ath5k_buf
ath5k_buf
ath5k_cal_data_offset_2413	and each section's size.
ath5k_cal_data_offset_2413	and each section's size.
ATH5K_CALIB_INTERVAL	Calibrate PHY every 10 seconds
ATH5K_CALIB_INTERVAL	Calibrate PHY every 10 seconds
ath5k_calibrate
ath5k_calibrate
ath5k_capabilities
ath5k_capabilities
ath5k_capability_type
ath5k_capability_type
ath5k_caps.c
ath5k_caps.c
ath5k_chan_pcal_info
ath5k_chan_pcal_info
ath5k_chan_pcal_info_rf2413
ath5k_chan_pcal_info_rf2413
ath5k_chan_pcal_info_rf5111
ath5k_chan_pcal_info_rf5111
ath5k_chan_pcal_info_rf5112
ath5k_chan_pcal_info_rf5112
ath5k_chan_set
ath5k_chan_set
ath5k_channel_ok	************************\
ath5k_channel_ok	************************\
ath5k_chip_name	******************\
ath5k_chip_name	******************\
ath5k_combine_linear_pcdac_curves
ath5k_combine_linear_pcdac_curves
ath5k_combine_pwr_to_pdadc_curves
ath5k_combine_pwr_to_pdadc_curves
ath5k_config
ath5k_config
ath5k_configure_filter
ath5k_configure_filter
ath5k_copy_channels
ath5k_copy_channels
ath5k_create_power_curve
ath5k_create_power_curve
ath5k_ctl_mode
ath5k_ctl_mode
ath5k_desc
ath5k_desc
ath5k_desc.c
ath5k_desc.c
ATH5K_DESC_ALIGN	Alignment for TX/RX descriptors
ATH5K_DESC_ALIGN	Alignment for TX/RX descriptors
ath5k_desc_alloc	*****************\
ath5k_desc_alloc	*****************\
ath5k_desc_free
ath5k_desc_free
ath5k_detach
ath5k_detach
ath5k_dma.c
ath5k_dma.c
ath5k_dmasize
ath5k_dmasize
ath5k_driver_mode
ath5k_driver_mode
ath5k_edge_power
ath5k_edge_power
ath5k_eeprom.c
ath5k_eeprom.c
ath5k_eeprom_bin2freq
ath5k_eeprom_bin2freq
ath5k_eeprom_convert_pcal_info_2413	used by interpolation code
ath5k_eeprom_convert_pcal_info_2413	used by interpolation code
ath5k_eeprom_convert_pcal_info_5111	used by interpolation code
ath5k_eeprom_convert_pcal_info_5111	used by interpolation code
ath5k_eeprom_convert_pcal_info_5112	used by interpolation code
ath5k_eeprom_convert_pcal_info_5112	used by interpolation code
ath5k_eeprom_detach
ath5k_eeprom_detach
ath5k_eeprom_free_pcal_info
ath5k_eeprom_free_pcal_info
ath5k_eeprom_info
ath5k_eeprom_info
ath5k_eeprom_init
ath5k_eeprom_init
ath5k_eeprom_init_11a_pcal_freq
ath5k_eeprom_init_11a_pcal_freq
ath5k_eeprom_init_11bg_2413
ath5k_eeprom_init_11bg_2413
ath5k_eeprom_init_header
ath5k_eeprom_init_header
ath5k_eeprom_init_modes
ath5k_eeprom_init_modes
ath5k_eeprom_is_hb63
ath5k_eeprom_is_hb63
ath5k_eeprom_read_ants
ath5k_eeprom_read_ants
ath5k_eeprom_read_ctl_info
ath5k_eeprom_read_ctl_info
ath5k_eeprom_read_freq_list	frequency mask)
ath5k_eeprom_read_freq_list	frequency mask)
ath5k_eeprom_read_mac
ath5k_eeprom_read_mac
ath5k_eeprom_read_modes
ath5k_eeprom_read_modes
ath5k_eeprom_read_pcal_info
ath5k_eeprom_read_pcal_info
ath5k_eeprom_read_pcal_info_2413
ath5k_eeprom_read_pcal_info_2413
ath5k_eeprom_read_pcal_info_5111
ath5k_eeprom_read_pcal_info_5111
ath5k_eeprom_read_pcal_info_5112
ath5k_eeprom_read_pcal_info_5112
ath5k_eeprom_read_target_rate_pwr_info
ath5k_eeprom_read_target_rate_pwr_info
ath5k_eeprom_read_turbo_modes
ath5k_eeprom_read_turbo_modes
ath5k_fill_pwr_to_pcdac_table
ath5k_fill_pwr_to_pcdac_table
ath5k_gain
ath5k_gain
ath5k_gain_opt
ath5k_gain_opt
ath5k_gain_opt_step
ath5k_gain_opt_step
ath5k_get_chan_pcal_surrounding_piers
ath5k_get_chan_pcal_surrounding_piers
ath5k_get_interpolated_value	**************\
ath5k_get_interpolated_value	**************\
ath5k_get_linear_pcdac_min
ath5k_get_linear_pcdac_min
ath5k_get_max_ctl_power
ath5k_get_max_ctl_power
ath5k_get_pcdac_intercepts
ath5k_get_pcdac_intercepts
ath5k_get_rate_pcal_data
ath5k_get_rate_pcal_data
ath5k_gpio.c
ath5k_gpio.c
ath5k_handle_rx
ath5k_handle_rx
ath5k_handle_tx
ath5k_handle_tx
ath5k_hw
ath5k_hw
ath5k_hw_2w_tx_ctl
ath5k_hw_2w_tx_ctl
ath5k_hw_4w_tx_ctl
ath5k_hw_4w_tx_ctl
ath5k_hw_5210_tx_desc
ath5k_hw_5210_tx_desc
ath5k_hw_5212_tx_desc
ath5k_hw_5212_tx_desc
ath5k_hw_all_rx_desc
ath5k_hw_all_rx_desc
ath5k_hw_attach	ath5k_hw_attach - Check if hw is supported and init the needed structs
ath5k_hw_attach	ath5k_hw_attach - Check if hw is supported and init the needed structs
ath5k_hw_chan_has_spur_noise
ath5k_hw_chan_has_spur_noise
ath5k_hw_channel
ath5k_hw_channel
ath5k_hw_commit_eeprom_settings
ath5k_hw_commit_eeprom_settings
ath5k_hw_detach	ath5k_hw_detach - Free the ath5k_hw struct
ath5k_hw_detach	ath5k_hw_detach - Free the ath5k_hw struct
ath5k_hw_eeprom_read
ath5k_hw_eeprom_read
ath5k_hw_gainf_calibrate	adjustment
ath5k_hw_gainf_calibrate	adjustment
ath5k_hw_get_ack_timeout	****************\
ath5k_hw_get_ack_timeout	****************\
ath5k_hw_get_capability
ath5k_hw_get_capability
ath5k_hw_get_cts_timeout	ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec
ath5k_hw_get_cts_timeout	ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec
ath5k_hw_get_def_antenna
ath5k_hw_get_def_antenna
ath5k_hw_get_gpio
ath5k_hw_get_gpio
ath5k_hw_get_isr	ath5k_hw_get_isr - Get interrupt status
ath5k_hw_get_isr	ath5k_hw_get_isr - Get interrupt status
ath5k_hw_get_lladdr	**************\
ath5k_hw_get_lladdr	**************\
ath5k_hw_get_rx_filter	ath5k_hw_get_rx_filter - Get current rx filter
ath5k_hw_get_rx_filter	ath5k_hw_get_rx_filter - Get current rx filter
ath5k_hw_get_rxdp	ath5k_hw_get_rxdp - Get RX Descriptor's address
ath5k_hw_get_rxdp	ath5k_hw_get_rxdp - Get RX Descriptor's address
ath5k_hw_get_txdp	ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
ath5k_hw_get_txdp	ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
ath5k_hw_hasbssidmask(_ah)
ath5k_hw_hasbssidmask(_ah)
ath5k_hw_hasveol(_ah)
ath5k_hw_hasveol(_ah)
ath5k_hw_ini_mode_registers
ath5k_hw_ini_mode_registers
ath5k_hw_init_desc_functions
ath5k_hw_init_desc_functions
ath5k_hw_is_intr_pending	*****************\
ath5k_hw_is_intr_pending	*****************\
ath5k_hw_nic_reset
ath5k_hw_nic_reset
ath5k_hw_nic_wakeup
ath5k_hw_nic_wakeup
ath5k_hw_noise_floor_calibration	***************\
ath5k_hw_noise_floor_calibration	***************\
ath5k_hw_phy_calibrate
ath5k_hw_phy_calibrate
ath5k_hw_phy_disable
ath5k_hw_phy_disable
ath5k_hw_post	ath5k_hw_post - Power On Self Test helper function
ath5k_hw_post	ath5k_hw_post - Power On Self Test helper function
ath5k_hw_proc_2word_tx_status
ath5k_hw_proc_2word_tx_status
ath5k_hw_proc_4word_tx_status
ath5k_hw_proc_4word_tx_status
ath5k_hw_proc_5210_rx_status
ath5k_hw_proc_5210_rx_status
ath5k_hw_proc_5212_rx_status
ath5k_hw_proc_5212_rx_status
ath5k_hw_radio_revision	******************\
ath5k_hw_radio_revision	******************\
ath5k_hw_release_tx_queue
ath5k_hw_release_tx_queue
ath5k_hw_request_rfgain_probe
ath5k_hw_request_rfgain_probe
ath5k_hw_reset
ath5k_hw_reset
ath5k_hw_reset_key	*******************\
ath5k_hw_reset_key	*******************\
ath5k_hw_reset_tx_queue
ath5k_hw_reset_tx_queue
ath5k_hw_rf_check_gainf_readback	their detection window) so we must ignore it
ath5k_hw_rf_check_gainf_readback	their detection window) so we must ignore it
ath5k_hw_rf_gainf_adjust	of parameters from rf gain optimization ladder
ath5k_hw_rf_gainf_adjust	of parameters from rf gain optimization ladder
ath5k_hw_rf_gainf_corr	based on the current step for RF5112 rev. 2
ath5k_hw_rf_gainf_corr	based on the current step for RF5112 rev. 2
ath5k_hw_rf2425_channel
ath5k_hw_rf2425_channel
ath5k_hw_rf5110_calibrate
ath5k_hw_rf5110_calibrate
ath5k_hw_rf5110_chan2athchan
ath5k_hw_rf5110_chan2athchan
ath5k_hw_rf5110_channel
ath5k_hw_rf5110_channel
ath5k_hw_rf5111_chan2athchan
ath5k_hw_rf5111_chan2athchan
ath5k_hw_rf5111_channel
ath5k_hw_rf5111_channel
ath5k_hw_rf5112_channel
ath5k_hw_rf5112_channel
ath5k_hw_rf511x_calibrate
ath5k_hw_rf511x_calibrate
ath5k_hw_rfb_op
ath5k_hw_rfb_op
ath5k_hw_rfgain_init	with gain_F calibration
ath5k_hw_rfgain_init	with gain_F calibration
ath5k_hw_rfgain_opt_init	********************\
ath5k_hw_rfgain_opt_init	********************\
ath5k_hw_rfregs_init	******************\
ath5k_hw_rfregs_init	******************\
ath5k_hw_rix_to_bitrate
ath5k_hw_rix_to_bitrate
ath5k_hw_rx_ctl
ath5k_hw_rx_ctl
ath5k_hw_rx_error
ath5k_hw_rx_error
ath5k_hw_rx_status
ath5k_hw_rx_status
ath5k_hw_set_ack_bitrate_high	ath5k_hw_set_ack_bitrate - set bitrate for ACKs
ath5k_hw_set_ack_bitrate_high	ath5k_hw_set_ack_bitrate - set bitrate for ACKs
ath5k_hw_set_ack_timeout	ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
ath5k_hw_set_ack_timeout	ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
ath5k_hw_set_associd	ath5k_hw_set_associd - Set BSSID for association
ath5k_hw_set_associd	ath5k_hw_set_associd - Set BSSID for association
ath5k_hw_set_bssid_mask	ath5k_hw_set_bssid_mask - filter out bssids we listen
ath5k_hw_set_bssid_mask	ath5k_hw_set_bssid_mask - filter out bssids we listen
ath5k_hw_set_capabilities
ath5k_hw_set_capabilities
ath5k_hw_set_cts_timeout	ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
ath5k_hw_set_cts_timeout	ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
ath5k_hw_set_def_antenna
ath5k_hw_set_def_antenna
ath5k_hw_set_gpio
ath5k_hw_set_gpio
ath5k_hw_set_gpio_input
ath5k_hw_set_gpio_input
ath5k_hw_set_gpio_intr
ath5k_hw_set_gpio_intr
ath5k_hw_set_gpio_output
ath5k_hw_set_gpio_output
ath5k_hw_set_imr	ath5k_hw_set_imr - Set interrupt mask
ath5k_hw_set_imr	ath5k_hw_set_imr - Set interrupt mask
ath5k_hw_set_lladdr	ath5k_hw_set_lladdr - Set station id
ath5k_hw_set_lladdr	ath5k_hw_set_lladdr - Set station id
ath5k_hw_set_mcast_filter
ath5k_hw_set_mcast_filter
ath5k_hw_set_opmode	*****************\
ath5k_hw_set_opmode	*****************\
ath5k_hw_set_rx_filter	ath5k_hw_set_rx_filter - Set rx filter
ath5k_hw_set_rx_filter	ath5k_hw_set_rx_filter - Set rx filter
ath5k_hw_set_rxdp	ath5k_hw_set_rxdp - Set RX Descriptor's address
ath5k_hw_set_rxdp	ath5k_hw_set_rxdp - Set RX Descriptor's address
ath5k_hw_set_slot_time
ath5k_hw_set_slot_time
ath5k_hw_set_tx_queueprops
ath5k_hw_set_tx_queueprops
ath5k_hw_set_txdp	ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
ath5k_hw_set_txdp	ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
ath5k_hw_set_txpower_limit
ath5k_hw_set_txpower_limit
ath5k_hw_setup_2word_tx_desc
ath5k_hw_setup_2word_tx_desc
ath5k_hw_setup_4word_tx_desc
ath5k_hw_setup_4word_tx_desc
ath5k_hw_setup_rx_desc
ath5k_hw_setup_rx_desc
ath5k_hw_setup_tx_queue
ath5k_hw_setup_tx_queue
ath5k_hw_start_rx_dma	*******\
ath5k_hw_start_rx_dma	*******\
ath5k_hw_start_rx_pcu	**********\
ath5k_hw_start_rx_pcu	**********\
ath5k_hw_start_tx_dma	********\
ath5k_hw_start_tx_dma	********\
ath5k_hw_stop_rx_dma	ath5k_hw_stop_rx_dma - Stop DMA receive
ath5k_hw_stop_rx_dma	ath5k_hw_stop_rx_dma - Stop DMA receive
ath5k_hw_stop_rx_pcu	at5k_hw_stop_rx_pcu - Stop RX engine
ath5k_hw_stop_rx_pcu	at5k_hw_stop_rx_pcu - Stop RX engine
ath5k_hw_stop_tx_dma	ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
ath5k_hw_stop_tx_dma	ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
ath5k_hw_tweak_initval_settings
ath5k_hw_tweak_initval_settings
ath5k_hw_tx_status
ath5k_hw_tx_status
ath5k_hw_txpower
ath5k_hw_txpower
ath5k_hw_update_tx_triglevel	ath5k_hw_update_tx_triglevel - Update tx trigger level
ath5k_hw_update_tx_triglevel	ath5k_hw_update_tx_triglevel - Update tx trigger level
ath5k_hw_wake
ath5k_hw_wake
ath5k_hw_write_initvals
ath5k_hw_write_initvals
ath5k_hw_write_ofdm_timings	ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
ath5k_hw_write_ofdm_timings	ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
ath5k_hw_write_rate_duration	ath5k_hw_write_rate_duration - fill rate code to duration table
ath5k_hw_write_rate_duration	ath5k_hw_write_rate_duration - fill rate code to duration table
ath5k_ieee2mhz	******************\
ath5k_ieee2mhz	******************\
ath5k_ini
ath5k_ini
ath5k_ini_mode
ath5k_ini_mode
ath5k_ini_rfbuffer
ath5k_ini_rfbuffer
ath5k_ini_rfgain
ath5k_ini_rfgain
ath5k_init
ath5k_init
ath5k_initvals.c
ath5k_initvals.c
ath5k_int
ath5k_int
ath5k_irq	******************\
ath5k_irq	******************\
ath5k_is_rfkill_set
ath5k_is_rfkill_set
ath5k_mode_setup
ath5k_mode_setup
ATH5K_NR_RATES
ATH5K_NR_RATES
ath5k_pcu.c
ath5k_pcu.c
ath5k_pdgain_info
ath5k_pdgain_info
ath5k_pdgains_size_2413	these two functions
ath5k_pdgains_size_2413	these two functions
ath5k_phy.c
ath5k_phy.c
ath5k_pkt_type
ath5k_pkt_type
ath5k_poll
ath5k_poll
ath5k_power_mode
ath5k_power_mode
ath5k_powertable_type
ath5k_powertable_type
ath5k_probe
ath5k_probe
ath5k_qcu.c
ath5k_qcu.c
ath5k_radio
ath5k_radio
ATH5K_RATE_CODE_11M
ATH5K_RATE_CODE_11M
ATH5K_RATE_CODE_12M
ATH5K_RATE_CODE_12M
ATH5K_RATE_CODE_18M
ATH5K_RATE_CODE_18M
ATH5K_RATE_CODE_1M
ATH5K_RATE_CODE_1M
ATH5K_RATE_CODE_24M
ATH5K_RATE_CODE_24M
ATH5K_RATE_CODE_2M
ATH5K_RATE_CODE_2M
ATH5K_RATE_CODE_36M
ATH5K_RATE_CODE_36M
ATH5K_RATE_CODE_48M
ATH5K_RATE_CODE_48M
ATH5K_RATE_CODE_5_5M
ATH5K_RATE_CODE_5_5M
ATH5K_RATE_CODE_54M
ATH5K_RATE_CODE_54M
ATH5K_RATE_CODE_6M
ATH5K_RATE_CODE_6M
ATH5K_RATE_CODE_9M
ATH5K_RATE_CODE_9M
ATH5K_RATE_CODE_XR_1M
ATH5K_RATE_CODE_XR_1M
ATH5K_RATE_CODE_XR_2M
ATH5K_RATE_CODE_XR_2M
ATH5K_RATE_CODE_XR_3M
ATH5K_RATE_CODE_XR_3M
ATH5K_RATE_CODE_XR_500K
ATH5K_RATE_CODE_XR_500K
ath5k_rate_pcal_info
ath5k_rate_pcal_info
ath5k_rates[]
ath5k_rates[]
ath5k_remove
ath5k_remove
ath5k_reset
ath5k_reset
ath5k_reset.c
ath5k_reset.c
ath5k_reset_wake
ath5k_reset_wake
ATH5K_RETRIES	Number of times to retry packet sends
ATH5K_RETRIES	Number of times to retry packet sends
ath5k_rf_reg
ath5k_rf_reg
ath5k_rf_regs_idx
ath5k_rf_regs_idx
ath5k_rfb_field
ath5k_rfb_field
ath5k_rfgain
ath5k_rfgain
ath5k_rfkill.c
ath5k_rfkill.c
ath5k_rfkill_disable
ath5k_rfkill_disable
ath5k_rfkill_enable
ath5k_rfkill_enable
ath5k_rfkill_hw_start
ath5k_rfkill_hw_start
ath5k_rfkill_hw_stop
ath5k_rfkill_hw_stop
ath5k_rfkill_set_intr
ath5k_rfkill_set_intr
ath5k_rx_iob_alloc	*************\
ath5k_rx_iob_alloc	*************\
ath5k_rx_start	***********\
ath5k_rx_start	***********\
ath5k_rx_status
ath5k_rx_status
ath5k_rx_stop
ath5k_rx_stop
ath5k_rxbuf_free
ath5k_rxbuf_free
ath5k_rxbuf_setup
ath5k_rxbuf_setup
ath5k_setcurmode
ath5k_setcurmode
ath5k_setup_bands
ath5k_setup_bands
ath5k_setup_channel_powertable
ath5k_setup_channel_powertable
ath5k_setup_pcdac_table
ath5k_setup_pcdac_table
ath5k_setup_pwr_to_pdadc_table
ath5k_setup_pwr_to_pdadc_table
ath5k_setup_rate_powertable
ath5k_setup_rate_powertable
ath5k_softc
ath5k_softc
ATH5K_SPMBL_BOTH
ATH5K_SPMBL_BOTH
ATH5K_SPMBL_NO
ATH5K_SPMBL_NO
ATH5K_SPMBL_YES
ATH5K_SPMBL_YES
ath5k_srev_name
ath5k_srev_name
ath5k_srev_type
ath5k_srev_type
ath5k_start
ath5k_start
ath5k_stop
ath5k_stop
ath5k_stop_hw
ath5k_stop_hw
ath5k_tx	******************\
ath5k_tx	******************\
ath5k_tx_processq	***********\
ath5k_tx_processq	***********\
ath5k_tx_queue
ath5k_tx_queue
ath5k_tx_queue_id
ath5k_tx_queue_id
ath5k_tx_queue_subtype
ath5k_tx_queue_subtype
ath5k_tx_status
ath5k_tx_status
ath5k_txbuf_free
ath5k_txbuf_free
ath5k_txbuf_setup
ath5k_txbuf_setup
ath5k_txq
ath5k_txq
ath5k_txq_cleanup
ath5k_txq_cleanup
ath5k_txq_drainq
ath5k_txq_drainq
ath5k_txq_info
ath5k_txq_info
ath5k_txq_release
ath5k_txq_release
ath5k_txq_setup	************\
ath5k_txq_setup	************\
ath5k_version
ath5k_version
atl1e.c
atl1e.c
atl1e.h
atl1e.h
atl1e_adapter
atl1e_adapter
atl1e_cal_ring_size
atl1e_cal_ring_size
atl1e_check_eeprom_exist	****** Hardware-level functions: *******
atl1e_check_eeprom_exist	****** Hardware-level functions: *******
atl1e_check_link
atl1e_check_link
atl1e_clean_rx_irq
atl1e_clean_rx_irq
atl1e_clean_rx_ring
atl1e_clean_rx_ring
atl1e_clean_tx_irq
atl1e_clean_tx_irq
atl1e_clean_tx_ring
atl1e_clean_tx_ring
atl1e_clear_phy_int
atl1e_clear_phy_int
atl1e_close
atl1e_close
atl1e_configure
atl1e_configure
atl1e_configure_des_ring
atl1e_configure_des_ring
atl1e_configure_dma
atl1e_configure_dma
atl1e_configure_rx
atl1e_configure_rx
atl1e_configure_tx
atl1e_configure_tx
atl1e_dma_req_block
atl1e_dma_req_block
atl1e_down
atl1e_down
atl1e_force_ps
atl1e_force_ps
atl1e_free_ring_resources
atl1e_free_ring_resources
atl1e_get_permanent_address
atl1e_get_permanent_address
atl1e_get_rx_page
atl1e_get_rx_page
atl1e_get_speed_and_duplex
atl1e_get_speed_and_duplex
atl1e_get_tpd
atl1e_get_tpd
atl1e_get_tx_buffer
atl1e_get_tx_buffer
atl1e_hw
atl1e_hw
atl1e_hw_set_mac_addr
atl1e_hw_set_mac_addr
atl1e_init_hw
atl1e_init_hw
atl1e_init_netdev
atl1e_init_netdev
atl1e_init_pcie
atl1e_init_pcie
atl1e_init_ring_ptrs
atl1e_init_ring_ptrs
atl1e_init_ring_resources
atl1e_init_ring_resources
atl1e_irq
atl1e_irq
atl1e_irq_disable
atl1e_irq_disable
atl1e_irq_enable
atl1e_irq_enable
atl1e_irq_reset
atl1e_irq_reset
atl1e_mdio_read
atl1e_mdio_read
atl1e_mdio_write
atl1e_mdio_write
atl1e_nic_type
atl1e_nic_type
atl1e_open
atl1e_open
atl1e_phy_commit
atl1e_phy_commit
atl1e_phy_init
atl1e_phy_init
atl1e_phy_setup_autoneg_adv
atl1e_phy_setup_autoneg_adv
atl1e_poll
atl1e_poll
atl1e_probe
atl1e_probe
atl1e_read_mac_addr
atl1e_read_mac_addr
atl1e_read_phy_reg
atl1e_read_phy_reg
atl1e_recv_ret_status
atl1e_recv_ret_status
atl1e_remove
atl1e_remove
atl1e_reset
atl1e_reset
atl1e_reset_hw
atl1e_reset_hw
atl1e_restart_autoneg
atl1e_restart_autoneg
atl1e_rx_page
atl1e_rx_page
atl1e_rx_page_desc
atl1e_rx_page_desc
atl1e_rx_ring
atl1e_rx_ring
atl1e_setup_mac_ctrl
atl1e_setup_mac_ctrl
atl1e_setup_pcicmd
atl1e_setup_pcicmd
atl1e_setup_ring_resources
atl1e_setup_ring_resources
atl1e_sw_init
atl1e_sw_init
atl1e_tpd_avail
atl1e_tpd_avail
atl1e_tpd_desc
atl1e_tpd_desc
atl1e_tx_buffer
atl1e_tx_buffer
atl1e_tx_map
atl1e_tx_map
atl1e_tx_queue
atl1e_tx_queue
atl1e_tx_ring
atl1e_tx_ring
atl1e_up
atl1e_up
atl1e_write_phy_reg
atl1e_write_phy_reg
atl1e_xmit_frame
atl1e_xmit_frame
ATMEL_CHIP_ERASE
ATMEL_RDID
ATMEL_SECTOR_ERASE
ATT_C	21 Attribute Controller Registers
ATT_IW	Attribute Controller Index & Data Write Register
ATT_R	Attribute Controller Data Read Register
ATTR_BCOL_BLACK
ATTR_BCOL_BLACK
ATTR_BCOL_BLUE
ATTR_BCOL_BLUE
ATTR_BCOL_CYAN
ATTR_BCOL_CYAN
ATTR_BCOL_GREEN
ATTR_BCOL_GREEN
ATTR_BCOL_MAGENTA
ATTR_BCOL_MAGENTA
ATTR_BCOL_MASK
ATTR_BCOL_MASK
ATTR_BCOL_RED
ATTR_BCOL_RED
ATTR_BCOL_WHITE
ATTR_BCOL_WHITE
ATTR_BCOL_YELLOW
ATTR_BCOL_YELLOW
ATTR_BOLD
ATTR_BOLD
ATTR_DEFAULT
ATTR_DEFAULT
ATTR_FCOL_BLACK
ATTR_FCOL_BLACK
ATTR_FCOL_BLUE
ATTR_FCOL_BLUE
ATTR_FCOL_CYAN
ATTR_FCOL_CYAN
ATTR_FCOL_GREEN
ATTR_FCOL_GREEN
ATTR_FCOL_MAGENTA
ATTR_FCOL_MAGENTA
ATTR_FCOL_MASK
ATTR_FCOL_MASK
ATTR_FCOL_RED
ATTR_FCOL_RED
ATTR_FCOL_WHITE
ATTR_FCOL_WHITE
ATTR_FCOL_YELLOW
ATTR_FCOL_YELLOW
ATTRS_SHIFT
AUI
AUI
AUI_LOOPBACK
AUI_LOOPBACK
AUI_ON
AUI_ON
AUI_ONLY
AUI_ONLY
AUTO_ALL_MODES
AUTO_ALL_MODES
AUTO_AUI_10BASET
AUTO_AUI_10BASET
AUTO_ENABLE
AUTO_ENABLE
AUTO_NEG_BITS
AUTO_NEG_BITS
AUTO_NEG_BUSY
AUTO_NEG_BUSY
AUTO_NEG_CNF_OFFSET	8920 eeprom
AUTO_NEG_CNF_OFFSET	8920 eeprom
AUTO_NEG_ENABLE
AUTO_NEG_ENABLE
AUTO_NEG_MASK
AUTO_NEG_MASK
AUTO_POLARITY_DISABLE	register 11h bit 4
AUTO_POLARITY_DISABLE	register 11h bit 4
AUTO_READ_DONE_TIMEOUT
AUTO_READ_DONE_TIMEOUT
AUTO_RX_DMA
AUTO_RX_DMA
AUTO_WAKEUP
AUTO_WAKEUP
autoboot	Boot the system
autoboot.c
autoboot.h
autoboot_cmd.c
autoboot_cmd.c
autoboot_exec
autoboot_exec
autocolour
autocolour
AUTOINCREMENT	Bit mask to set bit-15 for autoincrement
AUTOINCREMENT	Bit mask to set bit-15 for autoincrement
AUTOMEDIA
AUTOMEDIA
AUTONEG_ADVERTISE_10_100_ALL	All 10/100 speeds
AUTONEG_ADVERTISE_10_100_ALL	All 10/100 speeds
AUTONEG_ADVERTISE_10_ALL	10Mbps Full & Half speeds
AUTONEG_ADVERTISE_10_ALL	10Mbps Full & Half speeds
AUTONEG_ADVERTISE_SPEED_DEFAULT	Everything but 1000-Half
AUTONEG_ADVERTISE_SPEED_DEFAULT	Everything but 1000-Half
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_DISABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTONEG_ENABLE
AUTOPOLL0	Auto-poll0 register
AUTOPOLL0	Auto-poll0 register
AUTOPOLL0_BITS
AUTOPOLL0_BITS
AUTOPOLL1	Auto-poll1 register
AUTOPOLL1	Auto-poll1 register
AUTOPOLL1_BITS
AUTOPOLL1_BITS
AUTOPOLL2	Auto-poll2 register
AUTOPOLL2	Auto-poll2 register
AUTOPOLL2_BITS
AUTOPOLL2_BITS
AUTOPOLL3	Auto-poll3 register
AUTOPOLL3	Auto-poll3 register
AUTOPOLL3_BITS
AUTOPOLL3_BITS
AUTOPOLL4	Auto-poll4 register
AUTOPOLL4	Auto-poll4 register
AUTOPOLL4_BITS
AUTOPOLL4_BITS
AUTOPOLL5	Auto-poll5 register
AUTOPOLL5	Auto-poll5 register
AUTOPOLL5_BITS
AUTOPOLL5_BITS
autosized_block
autosized_block
autovivify_child_settings	Find or create child named settings block
autovivify_child_settings	Find or create child named settings block
AUXCR_MDPPS
AUXCR_MDPPS
await_fsp
await_rpc	AWAIT_RPC - Wait for an rpc packet
AX25_TYPE	*< Amateur Radio AX.25
axtls_aes.c
axtls_aes.c
axtls_sha1.c
axtls_sha1.c

B

B	A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 　[Top]

B_OWNED_BY_CHIP
B_OWNED_BY_CHIP
B_OWNED_BY_HOST
B_OWNED_BY_HOST
b44.c
b44.c
b44.h
b44.h
B44_30BIT_DMA_MASK
B44_30BIT_DMA_MASK
B44_ADDR_HI	ENET Address Hi (B0 only)
B44_ADDR_HI	ENET Address Hi (B0 only)
B44_ADDR_LO	ENET Address Lo (B0 only)
B44_ADDR_LO	ENET Address Lo (B0 only)
B44_BIST_STAT	Built-In Self-Test Status
B44_BIST_STAT	Built-In Self-Test Status
B44_CAM_CTRL	EMAC CAM Control
B44_CAM_CTRL	EMAC CAM Control
B44_CAM_DATA_HI	EMAC CAM Data High
B44_CAM_DATA_HI	EMAC CAM Data High
B44_CAM_DATA_LO	EMAC CAM Data Low
B44_CAM_DATA_LO	EMAC CAM Data Low
b44_cam_write
b44_cam_write
b44_chip_reset
b44_chip_reset
B44_CHIP_RESET_FULL
B44_CHIP_RESET_FULL
B44_CHIP_RESET_PARTIAL
B44_CHIP_RESET_PARTIAL
b44_close	Close network device
b44_close	Close network device
B44_DEVCTRL	Device Control
B44_DEVCTRL	Device Control
B44_DMA_ALIGNMENT
B44_DMA_ALIGNMENT
B44_DMAFIFO_AD	DMA FIFO Diag Address
B44_DMAFIFO_AD	DMA FIFO Diag Address
B44_DMAFIFO_HI	DMA FIFO Diag High Data
B44_DMAFIFO_HI	DMA FIFO Diag High Data
B44_DMAFIFO_LO	DMA FIFO Diag Low Data
B44_DMAFIFO_LO	DMA FIFO Diag Low Data
B44_DMARX_ADDR	DMA RX Descriptor Ring Addr
B44_DMARX_ADDR	DMA RX Descriptor Ring Addr
B44_DMARX_CTRL	DMA RX Control
B44_DMARX_CTRL	DMA RX Control
B44_DMARX_PTR	DMA RX Last Posted Desc
B44_DMARX_PTR	DMA RX Last Posted Desc
B44_DMARX_STAT	Cur Active Desc. + Status
B44_DMARX_STAT	Cur Active Desc. + Status
B44_DMATX_ADDR	DMA TX Descriptor Ring Addr
B44_DMATX_ADDR	DMA TX Descriptor Ring Addr
B44_DMATX_CTRL	DMA TX Control
B44_DMATX_CTRL	DMA TX Control
B44_DMATX_PTR	DMA TX Last Posted Desc.
B44_DMATX_PTR	DMA TX Last Posted Desc.
B44_DMATX_STAT	DMA TX Cur Actve Desc. + Sts
B44_DMATX_STAT	DMA TX Cur Actve Desc. + Sts
B44_EMAC_IMASK	EMAC Interrupt Mask
B44_EMAC_IMASK	EMAC Interrupt Mask
B44_EMAC_ISTAT	EMAC Interrupt Status
B44_EMAC_ISTAT	EMAC Interrupt Status
B44_ENET_CTRL	EMAC ENET Control
B44_ENET_CTRL	EMAC ENET Control
B44_FILT_ADDR	ENET Filter Address
B44_FILT_ADDR	ENET Filter Address
B44_FILT_DATA	ENET Filter Data
B44_FILT_DATA	ENET Filter Data
b44_free_rx_ring
b44_free_rx_ring
b44_free_tx_ring
b44_free_tx_ring
B44_FULL_RESET
B44_FULL_RESET
B44_FULL_RESET_SKIP_PHY
B44_FULL_RESET_SKIP_PHY
B44_GPTIMER	General Purpose Timer
B44_GPTIMER	General Purpose Timer
b44_halt	called by b44_poll in the error path
b44_halt	called by b44_poll in the error path
B44_IMASK	Interrupt Mask
B44_IMASK	Interrupt Mask
b44_init_hw
b44_init_hw
b44_init_rx_ring
b44_init_rx_ring
b44_init_tx_ring
b44_init_tx_ring
b44_irq	Enable or disable interrupts
b44_irq	Enable or disable interrupts
B44_ISTAT	Interrupt Status
B44_ISTAT	Interrupt Status
b44_load_mac_and_phy_addr
b44_load_mac_and_phy_addr
B44_MAC_CTRL	MAC Control
B44_MAC_CTRL	MAC Control
B44_MAC_FLOW	MAC Flow Control
B44_MAC_FLOW	MAC Flow Control
B44_MAX_MTU
B44_MAX_MTU
B44_MDIO_CTRL	EMAC MDIO Control
B44_MDIO_CTRL	EMAC MDIO Control
B44_MDIO_DATA	EMAC MDIO Data
B44_MDIO_DATA	EMAC MDIO Data
B44_MIB_CTRL	EMAC MIB Control
B44_MIB_CTRL	EMAC MIB Control
B44_MII_ALEDCTRL	Activity LED
B44_MII_ALEDCTRL	Activity LED
B44_MII_AUXCTRL	Auxiliary Control
B44_MII_AUXCTRL	Auxiliary Control
B44_MII_TLEDCTRL	Traffic Meter LED
B44_MII_TLEDCTRL	Traffic Meter LED
B44_MIN_MTU
B44_MIN_MTU
b44_open	Open network device
b44_open	Open network device
B44_PARTIAL_RESET
B44_PARTIAL_RESET
b44_phy_read	* Interaction with the PHY **
b44_phy_read	* Interaction with the PHY **
b44_phy_reset
b44_phy_reset
b44_phy_write
b44_phy_write
b44_poll	Poll for completed and received packets
b44_poll	Poll for completed and received packets
b44_populate_rx_descriptor	* Management of ring descriptors **
b44_populate_rx_descriptor	* Management of ring descriptors **
b44_private
b44_private
b44_probe	* Implementation of gPXE driver callbacks **
b44_probe	* Implementation of gPXE driver callbacks **
b44_process_rx_packets
b44_process_rx_packets
B44_RCV_LAZY	Lazy Interrupt Control
B44_RCV_LAZY	Lazy Interrupt Control
b44_read_eeprom
b44_read_eeprom
B44_REGS_SIZE
B44_REGS_SIZE
b44_remove	Remove device
b44_remove	Remove device
B44_RING_LAST
B44_RING_LAST
B44_RING_SIZE
B44_RING_SIZE
B44_RX_1024_MAX	MIB RX 1024 to max byte Pkts
B44_RX_1024_MAX	MIB RX 1024 to max byte Pkts
B44_RX_128_255	MIB RX 128 to 255 byte Pkts
B44_RX_128_255	MIB RX 128 to 255 byte Pkts
B44_RX_256_511	MIB RX 256 to 511 byte Pkts
B44_RX_256_511	MIB RX 256 to 511 byte Pkts
B44_RX_512_1023	MIB RX 512 to 1023 byte Pkts
B44_RX_512_1023	MIB RX 512 to 1023 byte Pkts
B44_RX_64	MIB RX <= 64 byte Packets
B44_RX_64	MIB RX <= 64 byte Packets
B44_RX_65_127	MIB RX 65 to 127 byte Pkts
B44_RX_65_127	MIB RX 65 to 127 byte Pkts
B44_RX_ALIGN	MIB RX Align Errors
B44_RX_ALIGN	MIB RX Align Errors
B44_RX_BCAST	MIB RX Broadcast Packets
B44_RX_BCAST	MIB RX Broadcast Packets
B44_RX_CRC	MIB RX CRC Errors
B44_RX_CRC	MIB RX CRC Errors
B44_RX_CRCA	MIB RX CRC Align Errors
B44_RX_CRCA	MIB RX CRC Align Errors
B44_RX_FRAG	MIB RX Fragment Packets
B44_RX_FRAG	MIB RX Fragment Packets
B44_RX_GOOD_O	MIB RX Good Octets
B44_RX_GOOD_O	MIB RX Good Octets
B44_RX_GOOD_P	MIB RX Good Packets
B44_RX_GOOD_P	MIB RX Good Packets
B44_RX_JABBER	MIB RX Jabber Packets
B44_RX_JABBER	MIB RX Jabber Packets
B44_RX_MCAST	MIB RX Multicast Packets
B44_RX_MCAST	MIB RX Multicast Packets
B44_RX_MISS	MIB RX Missed Packets
B44_RX_MISS	MIB RX Missed Packets
B44_RX_NPAUSE	MIB RX Non-Pause Packets
B44_RX_NPAUSE	MIB RX Non-Pause Packets
B44_RX_O	MIB RX Octets
B44_RX_O	MIB RX Octets
B44_RX_OSIZE	MIB RX Oversize Packets
B44_RX_OSIZE	MIB RX Oversize Packets
B44_RX_P	MIB RX Packets
B44_RX_P	MIB RX Packets
B44_RX_PAUSE	MIB RX Pause Packets
B44_RX_PAUSE	MIB RX Pause Packets
b44_rx_refill
b44_rx_refill
B44_RX_RING_LEN_BYTES
B44_RX_RING_LEN_BYTES
B44_RX_SYM	MIB RX Symbol Errors
B44_RX_SYM	MIB RX Symbol Errors
B44_RX_USIZE	MIB RX Undersize Packets
B44_RX_USIZE	MIB RX Undersize Packets
B44_RXBURST	RX Max Burst Length
B44_RXBURST	RX Max Burst Length
B44_RXCONFIG	EMAC RX Config
B44_RXCONFIG	EMAC RX Config
B44_RXMAXLEN	EMAC RX Max Packet Length
B44_RXMAXLEN	EMAC RX Max Packet Length
B44_SBIDHIGH	SB Identification High
B44_SBIDHIGH	SB Identification High
B44_SBIMSTATE	SB Initiator Agent State
B44_SBIMSTATE	SB Initiator Agent State
B44_SBINTVEC	SB Interrupt Mask
B44_SBINTVEC	SB Interrupt Mask
B44_SBTMSHIGH	SB Target State High
B44_SBTMSHIGH	SB Target State High
B44_SBTMSLOW	SB Target State Low
B44_SBTMSLOW	SB Target State Low
b44_set_mac_addr
b44_set_mac_addr
b44_set_rx_mode
b44_set_rx_mode
b44_transmit	Transmit packet
b44_transmit	Transmit packet
B44_TX_1024_MAX	MIB TX 1024 to max byte Pkts
B44_TX_1024_MAX	MIB TX 1024 to max byte Pkts
B44_TX_128_255	MIB TX 128 to 255 byte Pkts
B44_TX_128_255	MIB TX 128 to 255 byte Pkts
B44_TX_256_511	MIB TX 256 to 511 byte Pkts
B44_TX_256_511	MIB TX 256 to 511 byte Pkts
B44_TX_512_1023	MIB TX 512 to 1023 byte Pkts
B44_TX_512_1023	MIB TX 512 to 1023 byte Pkts
B44_TX_64	MIB TX <= 64 byte Packets
B44_TX_64	MIB TX <= 64 byte Packets
B44_TX_65_127	MIB TX 65 to 127 byte Pkts
B44_TX_65_127	MIB TX 65 to 127 byte Pkts
B44_TX_BCAST	MIB TX Broadcast Packets
B44_TX_BCAST	MIB TX Broadcast Packets
B44_TX_CLOST	MIB TX Carrier Lost
B44_TX_CLOST	MIB TX Carrier Lost
b44_tx_complete	Recycles sent TX descriptors and notifies network stack
b44_tx_complete	Recycles sent TX descriptors and notifies network stack
B44_TX_CTRL	EMAC TX Control
B44_TX_CTRL	EMAC TX Control
B44_TX_DEFERED	MIB TX Defered Packets
B44_TX_DEFERED	MIB TX Defered Packets
B44_TX_ECOLS	MIB TX Excessive Collisions
B44_TX_ECOLS	MIB TX Excessive Collisions
B44_TX_FRAG	MIB TX Fragment Packets
B44_TX_FRAG	MIB TX Fragment Packets
B44_TX_GOOD_O	MIB TX Good Octets
B44_TX_GOOD_O	MIB TX Good Octets
B44_TX_GOOD_P	MIB TX Good Packets
B44_TX_GOOD_P	MIB TX Good Packets
B44_TX_HIWMARK	EMAC TX High Watermark
B44_TX_HIWMARK	EMAC TX High Watermark
B44_TX_JABBER	MIB TX Jabber Packets
B44_TX_JABBER	MIB TX Jabber Packets
B44_TX_LCOLS	MIB TX Late Collisions
B44_TX_LCOLS	MIB TX Late Collisions
B44_TX_MCAST	MIB TX Multicast Packets
B44_TX_MCAST	MIB TX Multicast Packets
B44_TX_MCOLS	MIB TX Multiple Collisions
B44_TX_MCOLS	MIB TX Multiple Collisions
B44_TX_O	MIB TX Octets
B44_TX_O	MIB TX Octets
B44_TX_OSIZE	MIB TX Oversize Packets
B44_TX_OSIZE	MIB TX Oversize Packets
B44_TX_P	MIB TX Packets
B44_TX_P	MIB TX Packets
B44_TX_PAUSE	MIB TX Pause Packets
B44_TX_PAUSE	MIB TX Pause Packets
B44_TX_RING_LEN_BYTES
B44_TX_RING_LEN_BYTES
B44_TX_SCOLS	MIB TX Single Collisions
B44_TX_SCOLS	MIB TX Single Collisions
B44_TX_TCOLS	MIB TX Total Collisions
B44_TX_TCOLS	MIB TX Total Collisions
B44_TX_URUNS	MIB TX Underruns
B44_TX_URUNS	MIB TX Underruns
B44_TXBURST	TX Max Burst Length
B44_TXBURST	TX Max Burst Length
B44_TXMAXLEN	EMAC TX Max Packet Length
B44_TXMAXLEN	EMAC TX Max Packet Length
b44_wait_bit	Wait until the given bit is set/cleared.
b44_wait_bit	Wait until the given bit is set/cleared.
B44_WKUP_LEN	Wakeup Length
B44_WKUP_LEN	Wakeup Length
BABL	Babble transmitter timeout error
BABL	Babble transmitter timeout error
BACKOFF_OFF
BACKOFF_OFF
backspace	Delete character to left of current cursor position
backspace	Delete character to left of current cursor position
BACKSPACE
bad_phy_status
BANK_SELECT
BANK_SELECT
BANK0_SELECT
BANK0_SELECT
BANK1_SELECT
BANK1_SELECT
BANK2_SELECT
BANK2_SELECT
BANNER_TIMEOUT	Tenths of a second for which the shell
BANNER_TIMEOUT	Tenths of a second for which the shell
BAP_TIMEOUT
BAP_TIMEOUT
BAR_0
BAR_0
BAR_0
BAR_0
BAR_1
BAR_1
BAR_1
BAR_1
BAR_5
BAR_5
BAR_5
BAR_5
barrier()
BASE
BASE
BASE
BASE
base.h
base.h
Base.h
base64.c
base64.c
base64.h
base64_encode	Base64-encode a string
base64_encode	Base64-encode a string
basemem.c
basemem.h
basemem_packet
basemem_packet.c
basemem_packet.h
BASEMEM_PACKET_LEN
basename	Return base name from path
basename	Return base name from path
basename.c
basename.c
BB_ANTATTEN_CHAN14
BB_ANTATTEN_CHAN14
BB_ANTENNA_B
BB_ANTENNA_B
BB_HOST_BANG
BB_HOST_BANG
BB_HOST_BANG_CLK
BB_HOST_BANG_CLK
BB_HOST_BANG_DATA
BB_HOST_BANG_DATA
BB_HOST_BANG_EN
BB_HOST_BANG_EN
bbConfig
bbFlushBits
bbPutBit
bbPutByte
BBS_BBS_DEVICE_PATH
BBS_BBS_DP
BBS_DEVICE_PATH
BBS_TYPE_BEV
BBS_TYPE_CDROM
BBS_TYPE_EMBEDDED_NETWORK
BBS_TYPE_FLOPPY
BBS_TYPE_HARDDRIVE
BBS_TYPE_PCMCIA
BBS_TYPE_UNKNOWN
BBS_TYPE_USB
bbWriteBits
BCD_COUNT
BCM_PAGE_BITS
BCM_PAGE_BITS
BCM_PAGE_SIZE
BCM_PAGE_SIZE
BCM4400_PCI_CORE_ADDR
BCM4400_PCI_CORE_ADDR
BCM5708S_1000X_CTL1
BCM5708S_1000X_CTL1
BCM5708S_1000X_CTL1_AUTODET_EN
BCM5708S_1000X_CTL1_AUTODET_EN
BCM5708S_1000X_CTL1_FIBER_MODE
BCM5708S_1000X_CTL1_FIBER_MODE
BCM5708S_1000X_CTL2
BCM5708S_1000X_CTL2
BCM5708S_1000X_CTL2_PLLEL_DET_E
BCM5708S_1000X_CTL2_PLLEL_DET_E
BCM5708S_1000X_STAT1
BCM5708S_1000X_STAT1
BCM5708S_1000X_STAT1_FD
BCM5708S_1000X_STAT1_FD
BCM5708S_1000X_STAT1_LINK
BCM5708S_1000X_STAT1_LINK
BCM5708S_1000X_STAT1_RX_PAUSE
BCM5708S_1000X_STAT1_RX_PAUSE
BCM5708S_1000X_STAT1_SGMII
BCM5708S_1000X_STAT1_SGMII
BCM5708S_1000X_STAT1_SPEED_10
BCM5708S_1000X_STAT1_SPEED_10
BCM5708S_1000X_STAT1_SPEED_100
BCM5708S_1000X_STAT1_SPEED_100
BCM5708S_1000X_STAT1_SPEED_1G
BCM5708S_1000X_STAT1_SPEED_1G
BCM5708S_1000X_STAT1_SPEED_2G5
BCM5708S_1000X_STAT1_SPEED_2G5
BCM5708S_1000X_STAT1_SPEED_MASK
BCM5708S_1000X_STAT1_SPEED_MASK
BCM5708S_1000X_STAT1_TX_PAUSE
BCM5708S_1000X_STAT1_TX_PAUSE
BCM5708S_BLK_ADDR
BCM5708S_BLK_ADDR
BCM5708S_BLK_ADDR_DIG
BCM5708S_BLK_ADDR_DIG
BCM5708S_BLK_ADDR_DIG3
BCM5708S_BLK_ADDR_DIG3
BCM5708S_BLK_ADDR_TX_MISC
BCM5708S_BLK_ADDR_TX_MISC
BCM5708S_DIG_3_0
BCM5708S_DIG_3_0
BCM5708S_DIG_3_0_USE_IEEE
BCM5708S_DIG_3_0_USE_IEEE
BCM5708S_TX_ACTL1
BCM5708S_TX_ACTL1
BCM5708S_TX_ACTL1_DRIVER_VCM
BCM5708S_TX_ACTL1_DRIVER_VCM
BCM5708S_TX_ACTL3
BCM5708S_TX_ACTL3
BCM5708S_UP1
BCM5708S_UP1
BCM5708S_UP1_2G5
BCM5708S_UP1_2G5
bcom_check_link
bcom_phy_init
bcom_phy_intr
BCON	Byte CONtrol
BCON	Byte CONtrol
bcopy	bcopy - Copy one area of memory to another
bcopy	bcopy - Copy one area of memory to another
BCR0_CRFT0
BCR0_CRFT0
BCR0_CRFT1
BCR0_CRFT1
BCR0_CRFT2
BCR0_CRFT2
BCR0_DMAL0
BCR0_DMAL0
BCR0_DMAL1
BCR0_DMAL1
BCR0_DMAL2
BCR0_DMAL2
BCR1_CTFT0
BCR1_CTFT0
BCR1_CTFT1
BCR1_CTFT1
BCR1_CTSF
BCR1_CTSF
BCR1_POT0
BCR1_POT0
BCR1_POT1
BCR1_POT1
BCR1_POT2
BCR1_POT2
BDA_FBMS
BDA_NUM_DRIVES
BDA_SEG
BDINFO_FLAGS_DISABLED
BDINFO_FLAGS_DISABLED
BDINFO_FLAGS_MAXLEN_MASK
BDINFO_FLAGS_MAXLEN_MASK
BDINFO_FLAGS_MAXLEN_SHIFT
BDINFO_FLAGS_MAXLEN_SHIFT
BDINFO_FLAGS_USE_EXT_RECV	ext rx_buffer_desc
BDINFO_FLAGS_USE_EXT_RECV	ext rx_buffer_desc
be16_to_cpu(x)
be16_to_cpu(x)
be16_to_cpus(x)
be16_to_cpus(x)
be32_to_cpu(x)
be32_to_cpu(x)
be32_to_cpus(x)
be32_to_cpus(x)
be64_to_cpu(x)
be64_to_cpu(x)
be64_to_cpus(x)
be64_to_cpus(x)
beep	@file
beep	@file
bflush
bflush
bi_add	@brief Perform an addition operation between two bigints.
bi_add	@brief Perform an addition operation between two bigints.
bi_barrett	@brief Perform a single Barrett reduction.
bi_barrett	@brief Perform a single Barrett reduction.
bi_clone	@brief Do a full copy of the bigint object.
bi_clone	@brief Do a full copy of the bigint object.
bi_compare	@brief Compare two bigints.
bi_compare	@brief Compare two bigints.
bi_copy	@brief Increment the number of references to this object.
bi_copy	@brief Increment the number of references to this object.
bi_crt	Use the Chinese Remainder Theorem to quickly perform RSA decrypts.
bi_crt	Use the Chinese Remainder Theorem to quickly perform RSA decrypts.
BI_CTX	*< A big integer "session" context.
BI_CTX	*< A big integer "session" context.
bi_depermanent	@brief Take a permanent object and make it eligible for freedom.
bi_depermanent	@brief Take a permanent object and make it eligible for freedom.
bi_divide	@brief Does both division and modulo calculations.
bi_divide	@brief Does both division and modulo calculations.
bi_export	@brief Take a bigint and convert it into a byte sequence.
bi_export	@brief Take a bigint and convert it into a byte sequence.
bi_free	@brief Free a bigint object so it can be used again.
bi_free	@brief Free a bigint object so it can be used again.
bi_free_mod	@brief Used when cleaning various bigints at the end of a session.
bi_free_mod	@brief Used when cleaning various bigints at the end of a session.
bi_import	@brief Allow a binary sequence to be imported as a bigint.
bi_import	@brief Allow a binary sequence to be imported as a bigint.
bi_initialize	@brief Start a new bigint context.
bi_initialize	@brief Start a new bigint context.
bi_int_divide
bi_int_divide
bi_int_multiply	Perform a multiply between a bigint an an (unsigned) integer
bi_int_multiply	Perform a multiply between a bigint an an (unsigned) integer
bi_mod(A, B)
bi_mod(A, B)
bi_mod_power	@brief Perform a modular exponentiation.
bi_mod_power	@brief Perform a modular exponentiation.
bi_mod_power2	@brief Perform a modular exponentiation using a temporary modulus.
bi_mod_power2	@brief Perform a modular exponentiation using a temporary modulus.
bi_mont	@brief Perform a single montgomery reduction.
bi_mont	@brief Perform a single montgomery reduction.
bi_multiply	@brief Perform a multiplication operation between two bigints.
bi_multiply	@brief Perform a multiplication operation between two bigints.
bi_permanent	@brief Simply make a bigint object "unfreeable" if bi_free() is called on it.
bi_permanent	@brief Simply make a bigint object "unfreeable" if bi_free() is called on it.
bi_print
bi_print
bi_residue(A, B)
bi_residue(A, B)
bi_residue(A, B)
bi_residue(A, B)
bi_residue(A, B)
bi_residue(A, B)
bi_set_mod	@brief Pre-calculate some of the expensive steps in reduction.
bi_set_mod	@brief Pre-calculate some of the expensive steps in reduction.
bi_square	@brief Perform a square operation on a bigint.
bi_square	@brief Perform a square operation on a bigint.
bi_square(A, B)
bi_square(A, B)
bi_str_import	@brief The testharness uses this code to import text hex-streams and
bi_str_import	@brief The testharness uses this code to import text hex-streams and
bi_subtract	@brief Perform a subtraction operation between two bigints.
bi_subtract	@brief Perform a subtraction operation between two bigints.
bi_terminate	@brief Close the bigint context and free any resources.
bi_terminate	@brief Close the bigint context and free any resources.
big_bswap.h
bigint.c
bigint.c
bigint.h
bigint.h
bigint_impl.h
bigint_impl.h
BIGINT_M_OFFSET	*< Normal modulo offset.
BIGINT_M_OFFSET	*< Normal modulo offset.
BIGINT_NUM_MODS	*< The number of modulus constants used.
BIGINT_NUM_MODS
BIGINT_NUM_MODS	*< The number of modulus constants used.
BIGINT_NUM_MODS
BIGINT_P_OFFSET	*< p modulo offset.
BIGINT_P_OFFSET	*< p modulo offset.
BIGINT_Q_OFFSET	*< q module offset.
BIGINT_Q_OFFSET	*< q module offset.
BINARY_COUNT
bios.h
bios_console.c
bios_cpu_nap	Save power by halting the CPU until the next interrupt
bios_currticks	Get current system time in ticks
bios_disk_device
bios_disk_driver
BIOS_DISK_DRIVER( _name, _fill_drive_name, _min_drive, _max_drive )
bios_disk_loc
BIOS_DISK_MAX_NAME_LEN
bios_disk_sector
bios_disks.h
bios_find_smbios	@file
bios_getchar	Get character from BIOS console
bios_handle_cup	Handle ANSI CUP (cursor position)
bios_handle_ed	Handle ANSI ED (erase in page)
bios_handle_sgr	Handle ANSI SGR (set graphics rendition)
bios_iskey	Check for character ready to read from BIOS console
BIOS_KEY(scancode)
BIOS_KEY_MIN
BIOS_LAST_OFFSET
BIOS_LAST_OFFSET
bios_nap.c
bios_nap.h
BIOS_OFFSET_INC
BIOS_OFFSET_INC
BIOS_OFFSET_INC
BIOS_OFFSET_INC
bios_putchar	Print a character to BIOS console
BIOS_SEG
bios_smbios.c
bios_smbios.h
BIOS_START_SEG
BIOS_START_SEG
BIOS_START_SEG
BIOS_START_SEG
bios_timer.c
bios_timer.h
biosint.c
biosint.h
BIST0_FUSE_FLAG	1: Indicating one cell has been fixed
BIST0_FUSE_FLAG	1: Indicating one cell has been fixed
BIST0_NOW	1: To trigger BIST0 logic. This bit stays high during the
BIST0_NOW	1: To trigger BIST0 logic. This bit stays high during the
BIST0_SRAM_FAIL	1: The SRAM failure is un-repairable because it has address
BIST0_SRAM_FAIL	1: The SRAM failure is un-repairable because it has address
BIST1_FUSE_FLAG
BIST1_FUSE_FLAG
BIST1_NOW	1: To trigger BIST0 logic. This bit stays high during the
BIST1_NOW	1: To trigger BIST0 logic. This bit stays high during the
BIST1_SRAM_FAIL	1: The SRAM failure is un-repairable because it has address
BIST1_SRAM_FAIL	1: The SRAM failure is un-repairable because it has address
BIT_ASSEMBLE_1( _ptr, _index, _field, _value )
BIT_ASSEMBLE_2( _ptr, _index, _field, _value, ... )
BIT_ASSEMBLE_3( _ptr, _index, _field, _value, ... )
BIT_ASSEMBLE_4( _ptr, _index, _field, _value, ... )
BIT_ASSEMBLE_5( _ptr, _index, _field, _value, ... )
BIT_ASSEMBLE_6( _ptr, _index, _field, _value, ... )
BIT_ASSEMBLE_7( _ptr, _index, _field, _value, ... )
bit_basher
bit_basher_operations
BIT_FILL( _ptr, _index, _assembled )
BIT_FILL_1( _ptr, _field1, ... )
BIT_FILL_2( _ptr, _field1, ... )
BIT_FILL_3( _ptr, _field1, ... )
BIT_FILL_4( _ptr, _field1, ... )
BIT_FILL_5( _ptr, _field1, ... )
BIT_FILL_6( _ptr, _field1, ... )
BIT_GET( _ptr, _field )
BIT_GET64( _ptr, _field )
BIT_MASK( _ptr, _field )
BIT_MASK_1( _ptr, _index, _field )
BIT_MASK_2( _ptr, _index, _field, ... )
BIT_MASK_3( _ptr, _index, _field, ... )
BIT_MASK_4( _ptr, _index, _field, ... )
BIT_MASK_5( _ptr, _index, _field, ... )
BIT_MASK_6( _ptr, _index, _field, ... )
BIT_MASK_7( _ptr, _index, _field, ... )
BIT_OFFSET( _ptr, _field )
BIT_SET( _ptr, _field, _value )
BIT_WIDTH( _ptr, _field )
BIT0
BIT0
BIT0
BIT0
BIT0
BIT1
BIT1
BIT1
BIT10
BIT10
BIT10
BIT11
BIT11
BIT11
BIT12
BIT12
BIT12
BIT13
BIT13
BIT13
BIT14
BIT14
BIT14
BIT15
BIT15
BIT15
BIT15
BIT15
BIT16
BIT16
BIT16
BIT17
BIT17
BIT17
BIT18
BIT18
BIT18
BIT19
BIT19
BIT19
BIT2
BIT2
BIT2
BIT20
BIT20
BIT20
BIT21
BIT21
BIT21
BIT22
BIT22
BIT22
BIT23
BIT23
BIT23
BIT24
BIT24
BIT24
BIT25
BIT25
BIT25
BIT26
BIT26
BIT26
BIT27
BIT27
BIT27
BIT28
BIT28
BIT28
BIT29
BIT29
BIT29
BIT3
BIT3
BIT3
BIT30
BIT30
BIT30
BIT31
BIT31
BIT31
BIT32
BIT32_to_cpu
BIT32_to_cpu
BIT33
BIT34
BIT35
BIT36
BIT37
BIT38
BIT39
BIT4
BIT4
BIT4
BIT40
BIT41
BIT42
BIT43
BIT44
BIT45
BIT46
BIT47
BIT48
BIT49
BIT5
BIT5
BIT5
BIT50
BIT51
BIT52
BIT53
BIT54
BIT55
BIT56
BIT57
BIT58
BIT59
BIT6
BIT6
BIT6
BIT60
BIT61
BIT62
BIT63
BIT64_to_cpu
BIT64_to_cpu
BIT7
BIT7
BIT7
BIT8
BIT8
BIT8
BIT9
BIT9
BIT9
bitbash.c
bitbash.c
bitbash.h
bitmap
bitmap.c
bitmap.c
bitmap.h
BITMAP_BLKSIZE
BITMAP_INDEX( bit )
BITMAP_MASK( bit )
bitmap_resize	@file
bitmap_resize	@file
bitmap_set	Set bit in bitmap
bitmap_set	Set bit in bitmap
bitmap_test	Test bit in bitmap
bitmap_test	Test bit in bitmap
bitops.c
bitops.c
bitops.h
BITSIZE
block_device
block_device_operations
blockdev.h
BLOCKELEMENT_FULL_BLOCK
BLOCKELEMENT_LIGHT_SHADE
BMCR_ANENABLE	Enable auto negotiation
BMCR_ANRESTART	Auto negotiation restart
BMCR_AUTO
BMCR_AUTO
BMCR_CTST	Collision test
BMCR_FDX
BMCR_FDX
BMCR_FULLDPLX	Full duplex
BMCR_ISO
BMCR_ISO
BMCR_ISOLATE	Disconnect DP83840 from MII
BMCR_LBK
BMCR_LBK
BMCR_LOOPBACK	TXD loopback bits
BMCR_PD
BMCR_PD
BMCR_PDOWN	Powerdown the DP83840
BMCR_REAUTO
BMCR_REAUTO
BMCR_RESET
BMCR_RESET	Reset the DP83840
BMCR_RESET
BMCR_RESV	Unused...
BMCR_SPEED100
BMCR_SPEED100	Select 100Mbps
BMCR_SPEED100
BMCR_SPEED1000	MSB of Speed (1000)
BMCR_SPEED1G
BMCR_SPEED1G
BMSR_100BASE4	Can do 100mbps, 4k packets
BMSR_100FULL	Can do 100mbps, full-duplex
BMSR_100FULL2	Can do 100BASE-T2 FDX
BMSR_100HALF	Can do 100mbps, half-duplex
BMSR_100HALF2	Can do 100BASE-T2 HDX
BMSR_10FULL	Can do 10mbps, full-duplex
BMSR_10HALF	Can do 10mbps, half-duplex
BMSR_ANEGCAPABLE	Able to do auto-negotiation
BMSR_ANEGCOMPLETE	Auto-negotiation complete
BMSR_AUTOCM
BMSR_AUTOCM
BMSR_ERCAP	Ext-reg capability
BMSR_ESTATEN	Extended Status in R15
BMSR_JCD	Jabber detected
BMSR_LNK
BMSR_LNK
BMSR_LSTATUS	Link status
BMSR_RESV	Unused...
BMSR_RFAULT	Remote fault detected
BNC
BNC
BNC_BIT
BNC_BIT
bnx2
bnx2
bnx2.c
bnx2.c
bnx2.h
bnx2.h
bnx2_5706s_linkup
bnx2_5706s_linkup
bnx2_5708s_linkup
bnx2_5708s_linkup
bnx2_alloc_bad_rbuf
bnx2_alloc_bad_rbuf
bnx2_alloc_mem
bnx2_alloc_mem
BNX2_BC_STATE
BNX2_BC_STATE
BNX2_BC_STATE_APPLY_WKARND
BNX2_BC_STATE_APPLY_WKARND
BNX2_BC_STATE_BC_DBG_CMD_LOOP_C
BNX2_BC_STATE_BC_DBG_CMD_LOOP_C
BNX2_BC_STATE_BC_DBG_CMD_LOOP_I
BNX2_BC_STATE_BC_DBG_CMD_LOOP_I
BNX2_BC_STATE_BC_DBG_CMD_SIGNAT
BNX2_BC_STATE_BC_DBG_CMD_SIGNAT
BNX2_BC_STATE_BC_DBG_CMD_SIGNAT
BNX2_BC_STATE_BC_DBG_CMD_SIGNAT
BNX2_BC_STATE_BC1_START
BNX2_BC_STATE_BC1_START
BNX2_BC_STATE_DEBUG_CMD
BNX2_BC_STATE_DEBUG_CMD
BNX2_BC_STATE_ERR_BAD_BC2_CRC
BNX2_BC_STATE_ERR_BAD_BC2_CRC
BNX2_BC_STATE_ERR_BAD_VERSION
BNX2_BC_STATE_ERR_BAD_VERSION
BNX2_BC_STATE_ERR_BC1_LOOP
BNX2_BC_STATE_ERR_BC1_LOOP
BNX2_BC_STATE_ERR_DRV_DEAD
BNX2_BC_STATE_ERR_DRV_DEAD
BNX2_BC_STATE_ERR_MASK
BNX2_BC_STATE_ERR_MASK
BNX2_BC_STATE_ERR_NO_RXP
BNX2_BC_STATE_ERR_NO_RXP
BNX2_BC_STATE_ERR_TOO_MANY_RBUF
BNX2_BC_STATE_ERR_TOO_MANY_RBUF
BNX2_BC_STATE_ERR_UNKNOWN_CMD
BNX2_BC_STATE_ERR_UNKNOWN_CMD
BNX2_BC_STATE_GET_NVM_CFG1
BNX2_BC_STATE_GET_NVM_CFG1
BNX2_BC_STATE_GET_NVM_CFG2
BNX2_BC_STATE_GET_NVM_CFG2
BNX2_BC_STATE_GOING_BC2
BNX2_BC_STATE_GOING_BC2
BNX2_BC_STATE_GOING_DIAG
BNX2_BC_STATE_GOING_DIAG
BNX2_BC_STATE_INIT_VID
BNX2_BC_STATE_INIT_VID
BNX2_BC_STATE_LOAD_BC2
BNX2_BC_STATE_LOAD_BC2
BNX2_BC_STATE_PROG_BAR
BNX2_BC_STATE_PROG_BAR
BNX2_BC_STATE_RESET_TYPE
BNX2_BC_STATE_RESET_TYPE
BNX2_BC_STATE_RESET_TYPE_DRV_DI
BNX2_BC_STATE_RESET_TYPE_DRV_DI
BNX2_BC_STATE_RESET_TYPE_DRV_MA
BNX2_BC_STATE_RESET_TYPE_DRV_MA
BNX2_BC_STATE_RESET_TYPE_DRV_RE
BNX2_BC_STATE_RESET_TYPE_DRV_RE
BNX2_BC_STATE_RESET_TYPE_DRV_SH
BNX2_BC_STATE_RESET_TYPE_DRV_SH
BNX2_BC_STATE_RESET_TYPE_DRV_UN
BNX2_BC_STATE_RESET_TYPE_DRV_UN
BNX2_BC_STATE_RESET_TYPE_DRV_WO
BNX2_BC_STATE_RESET_TYPE_DRV_WO
BNX2_BC_STATE_RESET_TYPE_NONE
BNX2_BC_STATE_RESET_TYPE_NONE
BNX2_BC_STATE_RESET_TYPE_PCI
BNX2_BC_STATE_RESET_TYPE_PCI
BNX2_BC_STATE_RESET_TYPE_SIG
BNX2_BC_STATE_RESET_TYPE_SIG
BNX2_BC_STATE_RESET_TYPE_SIG_MA
BNX2_BC_STATE_RESET_TYPE_SIG_MA
BNX2_BC_STATE_RESET_TYPE_VALUE(msg)
BNX2_BC_STATE_RESET_TYPE_VALUE(msg)
BNX2_BC_STATE_RESET_TYPE_VAUX
BNX2_BC_STATE_RESET_TYPE_VAUX
BNX2_BC_STATE_RT_DRV_CMD
BNX2_BC_STATE_RT_DRV_CMD
BNX2_BC_STATE_RT_DRV_PULSE
BNX2_BC_STATE_RT_DRV_PULSE
BNX2_BC_STATE_RT_FINAL_INIT
BNX2_BC_STATE_RT_FINAL_INIT
BNX2_BC_STATE_RT_FIOEVTS
BNX2_BC_STATE_RT_FIOEVTS
BNX2_BC_STATE_RT_GOING_D3
BNX2_BC_STATE_RT_GOING_D3
BNX2_BC_STATE_RT_LOW_POWER
BNX2_BC_STATE_RT_LOW_POWER
BNX2_BC_STATE_RT_OTHER_FW
BNX2_BC_STATE_RT_OTHER_FW
BNX2_BC_STATE_RT_SET_WOL
BNX2_BC_STATE_RT_SET_WOL
BNX2_BC_STATE_RT_WKARND
BNX2_BC_STATE_RT_WKARND
BNX2_BC_STATE_SIGN
BNX2_BC_STATE_SIGN
BNX2_BC_STATE_SIGN_MASK
BNX2_BC_STATE_SIGN_MASK
BNX2_COM_COMQ_FTQ_CMD
BNX2_COM_COMQ_FTQ_CMD
BNX2_COM_COMQ_FTQ_CMD_ADD_DATA
BNX2_COM_COMQ_FTQ_CMD_ADD_DATA
BNX2_COM_COMQ_FTQ_CMD_ADD_INTER
BNX2_COM_COMQ_FTQ_CMD_ADD_INTER
BNX2_COM_COMQ_FTQ_CMD_BUSY
BNX2_COM_COMQ_FTQ_CMD_BUSY
BNX2_COM_COMQ_FTQ_CMD_INTERVENE
BNX2_COM_COMQ_FTQ_CMD_INTERVENE
BNX2_COM_COMQ_FTQ_CMD_OFFSET
BNX2_COM_COMQ_FTQ_CMD_OFFSET
BNX2_COM_COMQ_FTQ_CMD_POP
BNX2_COM_COMQ_FTQ_CMD_POP
BNX2_COM_COMQ_FTQ_CMD_RD_DATA
BNX2_COM_COMQ_FTQ_CMD_RD_DATA
BNX2_COM_COMQ_FTQ_CMD_SFT_RESET
BNX2_COM_COMQ_FTQ_CMD_SFT_RESET
BNX2_COM_COMQ_FTQ_CMD_WR_TOP
BNX2_COM_COMQ_FTQ_CMD_WR_TOP
BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0
BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0
BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1
BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1
BNX2_COM_COMQ_FTQ_CTL
BNX2_COM_COMQ_FTQ_CTL
BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH
BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH
BNX2_COM_COMQ_FTQ_CTL_FORCE_INT
BNX2_COM_COMQ_FTQ_CTL_FORCE_INT
BNX2_COM_COMQ_FTQ_CTL_INTERVENE
BNX2_COM_COMQ_FTQ_CTL_INTERVENE
BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH
BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH
BNX2_COM_COMQ_FTQ_CTL_OVERFLOW
BNX2_COM_COMQ_FTQ_CTL_OVERFLOW
BNX2_COM_COMQ_FTQ_DATA
BNX2_COM_COMQ_FTQ_DATA
BNX2_COM_COMTQ_FTQ_CMD
BNX2_COM_COMTQ_FTQ_CMD
BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA
BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA
BNX2_COM_COMTQ_FTQ_CMD_ADD_INTE
BNX2_COM_COMTQ_FTQ_CMD_ADD_INTE
BNX2_COM_COMTQ_FTQ_CMD_BUSY
BNX2_COM_COMTQ_FTQ_CMD_BUSY
BNX2_COM_COMTQ_FTQ_CMD_INTERVEN
BNX2_COM_COMTQ_FTQ_CMD_INTERVEN
BNX2_COM_COMTQ_FTQ_CMD_OFFSET
BNX2_COM_COMTQ_FTQ_CMD_OFFSET
BNX2_COM_COMTQ_FTQ_CMD_POP
BNX2_COM_COMTQ_FTQ_CMD_POP
BNX2_COM_COMTQ_FTQ_CMD_RD_DATA
BNX2_COM_COMTQ_FTQ_CMD_RD_DATA
BNX2_COM_COMTQ_FTQ_CMD_SFT_RESE
BNX2_COM_COMTQ_FTQ_CMD_SFT_RESE
BNX2_COM_COMTQ_FTQ_CMD_WR_TOP
BNX2_COM_COMTQ_FTQ_CMD_WR_TOP
BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0
BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0
BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1
BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1
BNX2_COM_COMTQ_FTQ_CTL
BNX2_COM_COMTQ_FTQ_CTL
BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPT
BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPT
BNX2_COM_COMTQ_FTQ_CTL_FORCE_IN
BNX2_COM_COMTQ_FTQ_CTL_FORCE_IN
BNX2_COM_COMTQ_FTQ_CTL_INTERVEN
BNX2_COM_COMTQ_FTQ_CTL_INTERVEN
BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPT
BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPT
BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW
BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW
BNX2_COM_COMTQ_FTQ_DATA
BNX2_COM_COMTQ_FTQ_DATA
BNX2_COM_COMXQ_FTQ_CMD
BNX2_COM_COMXQ_FTQ_CMD
BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA
BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA
BNX2_COM_COMXQ_FTQ_CMD_ADD_INTE
BNX2_COM_COMXQ_FTQ_CMD_ADD_INTE
BNX2_COM_COMXQ_FTQ_CMD_BUSY
BNX2_COM_COMXQ_FTQ_CMD_BUSY
BNX2_COM_COMXQ_FTQ_CMD_INTERVEN
BNX2_COM_COMXQ_FTQ_CMD_INTERVEN
BNX2_COM_COMXQ_FTQ_CMD_OFFSET
BNX2_COM_COMXQ_FTQ_CMD_OFFSET
BNX2_COM_COMXQ_FTQ_CMD_POP
BNX2_COM_COMXQ_FTQ_CMD_POP
BNX2_COM_COMXQ_FTQ_CMD_RD_DATA
BNX2_COM_COMXQ_FTQ_CMD_RD_DATA
BNX2_COM_COMXQ_FTQ_CMD_SFT_RESE
BNX2_COM_COMXQ_FTQ_CMD_SFT_RESE
BNX2_COM_COMXQ_FTQ_CMD_WR_TOP
BNX2_COM_COMXQ_FTQ_CMD_WR_TOP
BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0
BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0
BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1
BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1
BNX2_COM_COMXQ_FTQ_CTL
BNX2_COM_COMXQ_FTQ_CTL
BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPT
BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPT
BNX2_COM_COMXQ_FTQ_CTL_FORCE_IN
BNX2_COM_COMXQ_FTQ_CTL_FORCE_IN
BNX2_COM_COMXQ_FTQ_CTL_INTERVEN
BNX2_COM_COMXQ_FTQ_CTL_INTERVEN
BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPT
BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPT
BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW
BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW
BNX2_COM_COMXQ_FTQ_DATA
BNX2_COM_COMXQ_FTQ_DATA
BNX2_COM_CPU_DATA_ACCESS
BNX2_COM_CPU_DATA_ACCESS
BNX2_COM_CPU_DEBUG_VECT_PEEK
BNX2_COM_CPU_DEBUG_VECT_PEEK
BNX2_COM_CPU_DEBUG_VECT_PEEK_1_
BNX2_COM_CPU_DEBUG_VECT_PEEK_1_
BNX2_COM_CPU_DEBUG_VECT_PEEK_1_
BNX2_COM_CPU_DEBUG_VECT_PEEK_1_
BNX2_COM_CPU_DEBUG_VECT_PEEK_1_
BNX2_COM_CPU_DEBUG_VECT_PEEK_1_
BNX2_COM_CPU_DEBUG_VECT_PEEK_2_
BNX2_COM_CPU_DEBUG_VECT_PEEK_2_
BNX2_COM_CPU_DEBUG_VECT_PEEK_2_
BNX2_COM_CPU_DEBUG_VECT_PEEK_2_
BNX2_COM_CPU_DEBUG_VECT_PEEK_2_
BNX2_COM_CPU_DEBUG_VECT_PEEK_2_
BNX2_COM_CPU_EVENT_MASK
BNX2_COM_CPU_EVENT_MASK
BNX2_COM_CPU_EVENT_MASK_ALIGN_H
BNX2_COM_CPU_EVENT_MASK_ALIGN_H
BNX2_COM_CPU_EVENT_MASK_BAD_DAT
BNX2_COM_CPU_EVENT_MASK_BAD_DAT
BNX2_COM_CPU_EVENT_MASK_BAD_INS
BNX2_COM_CPU_EVENT_MASK_BAD_INS
BNX2_COM_CPU_EVENT_MASK_BAD_PC_
BNX2_COM_CPU_EVENT_MASK_BAD_PC_
BNX2_COM_CPU_EVENT_MASK_BREAKPO
BNX2_COM_CPU_EVENT_MASK_BREAKPO
BNX2_COM_CPU_EVENT_MASK_FIO_ABO
BNX2_COM_CPU_EVENT_MASK_FIO_ABO
BNX2_COM_CPU_EVENT_MASK_INTERRU
BNX2_COM_CPU_EVENT_MASK_INTERRU
BNX2_COM_CPU_EVENT_MASK_PAGE_0_
BNX2_COM_CPU_EVENT_MASK_PAGE_0_
BNX2_COM_CPU_EVENT_MASK_PAGE_0_
BNX2_COM_CPU_EVENT_MASK_PAGE_0_
BNX2_COM_CPU_EVENT_MASK_SOFT_HA
BNX2_COM_CPU_EVENT_MASK_SOFT_HA
BNX2_COM_CPU_EVENT_MASK_SPAD_UN
BNX2_COM_CPU_EVENT_MASK_SPAD_UN
BNX2_COM_CPU_HW_BREAKPOINT
BNX2_COM_CPU_HW_BREAKPOINT
BNX2_COM_CPU_HW_BREAKPOINT_ADDR
BNX2_COM_CPU_HW_BREAKPOINT_ADDR
BNX2_COM_CPU_HW_BREAKPOINT_DISA
BNX2_COM_CPU_HW_BREAKPOINT_DISA
BNX2_COM_CPU_INSTRUCTION
BNX2_COM_CPU_INSTRUCTION
BNX2_COM_CPU_INTERRUPT_ENABLE
BNX2_COM_CPU_INTERRUPT_ENABLE
BNX2_COM_CPU_INTERRUPT_SAVED_PC
BNX2_COM_CPU_INTERRUPT_SAVED_PC
BNX2_COM_CPU_INTERRUPT_VECTOR
BNX2_COM_CPU_INTERRUPT_VECTOR
BNX2_COM_CPU_LAST_BRANCH_ADDR
BNX2_COM_CPU_LAST_BRANCH_ADDR
BNX2_COM_CPU_LAST_BRANCH_ADDR_L
BNX2_COM_CPU_LAST_BRANCH_ADDR_L
BNX2_COM_CPU_LAST_BRANCH_ADDR_T
BNX2_COM_CPU_LAST_BRANCH_ADDR_T
BNX2_COM_CPU_LAST_BRANCH_ADDR_T
BNX2_COM_CPU_LAST_BRANCH_ADDR_T
BNX2_COM_CPU_LAST_BRANCH_ADDR_T
BNX2_COM_CPU_LAST_BRANCH_ADDR_T
BNX2_COM_CPU_MODE
BNX2_COM_CPU_MODE
BNX2_COM_CPU_MODE_BAD_DATA_HALT
BNX2_COM_CPU_MODE_BAD_DATA_HALT
BNX2_COM_CPU_MODE_BAD_INST_HALT
BNX2_COM_CPU_MODE_BAD_INST_HALT
BNX2_COM_CPU_MODE_FIO_ABORT_HAL
BNX2_COM_CPU_MODE_FIO_ABORT_HAL
BNX2_COM_CPU_MODE_INTERRUPT_ENA
BNX2_COM_CPU_MODE_INTERRUPT_ENA
BNX2_COM_CPU_MODE_LOCAL_RST
BNX2_COM_CPU_MODE_LOCAL_RST
BNX2_COM_CPU_MODE_MSG_BIT1
BNX2_COM_CPU_MODE_MSG_BIT1
BNX2_COM_CPU_MODE_PAGE_0_DATA_E
BNX2_COM_CPU_MODE_PAGE_0_DATA_E
BNX2_COM_CPU_MODE_PAGE_0_INST_E
BNX2_COM_CPU_MODE_PAGE_0_INST_E
BNX2_COM_CPU_MODE_SOFT_HALT
BNX2_COM_CPU_MODE_SOFT_HALT
BNX2_COM_CPU_MODE_SPAD_UNDERFLO
BNX2_COM_CPU_MODE_SPAD_UNDERFLO
BNX2_COM_CPU_MODE_STEP_ENA
BNX2_COM_CPU_MODE_STEP_ENA
BNX2_COM_CPU_PROGRAM_COUNTER
BNX2_COM_CPU_PROGRAM_COUNTER
BNX2_COM_CPU_REG_FILE
BNX2_COM_CPU_REG_FILE
BNX2_COM_CPU_STATE
BNX2_COM_CPU_STATE
BNX2_COM_CPU_STATE_ALIGN_HALTED
BNX2_COM_CPU_STATE_ALIGN_HALTED
BNX2_COM_CPU_STATE_BAD_DATA_ADD
BNX2_COM_CPU_STATE_BAD_DATA_ADD
BNX2_COM_CPU_STATE_BAD_INST_HAL
BNX2_COM_CPU_STATE_BAD_INST_HAL
BNX2_COM_CPU_STATE_BAD_pc_HALTE
BNX2_COM_CPU_STATE_BAD_pc_HALTE
BNX2_COM_CPU_STATE_BLOCKED_READ
BNX2_COM_CPU_STATE_BLOCKED_READ
BNX2_COM_CPU_STATE_BREAKPOINT
BNX2_COM_CPU_STATE_BREAKPOINT
BNX2_COM_CPU_STATE_DATA_ACCESS_
BNX2_COM_CPU_STATE_DATA_ACCESS_
BNX2_COM_CPU_STATE_FIO_ABORT_HA
BNX2_COM_CPU_STATE_FIO_ABORT_HA
BNX2_COM_CPU_STATE_INST_FETCH_S
BNX2_COM_CPU_STATE_INST_FETCH_S
BNX2_COM_CPU_STATE_INTERRRUPT
BNX2_COM_CPU_STATE_INTERRRUPT
BNX2_COM_CPU_STATE_PAGE_0_DATA_
BNX2_COM_CPU_STATE_PAGE_0_DATA_
BNX2_COM_CPU_STATE_PAGE_0_INST_
BNX2_COM_CPU_STATE_PAGE_0_INST_
BNX2_COM_CPU_STATE_SOFT_HALTED
BNX2_COM_CPU_STATE_SOFT_HALTED
BNX2_COM_CPU_STATE_SPAD_UNDERFL
BNX2_COM_CPU_STATE_SPAD_UNDERFL
BNX2_COM_SCRATCH
BNX2_COM_SCRATCH
bnx2_copper_linkup
bnx2_copper_linkup
BNX2_CP_CPQ_FTQ_CMD
BNX2_CP_CPQ_FTQ_CMD
BNX2_CP_CPQ_FTQ_CMD_ADD_DATA
BNX2_CP_CPQ_FTQ_CMD_ADD_DATA
BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVE
BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVE
BNX2_CP_CPQ_FTQ_CMD_BUSY
BNX2_CP_CPQ_FTQ_CMD_BUSY
BNX2_CP_CPQ_FTQ_CMD_INTERVENE_C
BNX2_CP_CPQ_FTQ_CMD_INTERVENE_C
BNX2_CP_CPQ_FTQ_CMD_OFFSET
BNX2_CP_CPQ_FTQ_CMD_OFFSET
BNX2_CP_CPQ_FTQ_CMD_POP
BNX2_CP_CPQ_FTQ_CMD_POP
BNX2_CP_CPQ_FTQ_CMD_RD_DATA
BNX2_CP_CPQ_FTQ_CMD_RD_DATA
BNX2_CP_CPQ_FTQ_CMD_SFT_RESET
BNX2_CP_CPQ_FTQ_CMD_SFT_RESET
BNX2_CP_CPQ_FTQ_CMD_WR_TOP
BNX2_CP_CPQ_FTQ_CMD_WR_TOP
BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0
BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0
BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1
BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1
BNX2_CP_CPQ_FTQ_CTL
BNX2_CP_CPQ_FTQ_CTL
BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH
BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH
BNX2_CP_CPQ_FTQ_CTL_FORCE_INTER
BNX2_CP_CPQ_FTQ_CTL_FORCE_INTER
BNX2_CP_CPQ_FTQ_CTL_INTERVENE
BNX2_CP_CPQ_FTQ_CTL_INTERVENE
BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH
BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH
BNX2_CP_CPQ_FTQ_CTL_OVERFLOW
BNX2_CP_CPQ_FTQ_CTL_OVERFLOW
BNX2_CP_CPQ_FTQ_DATA
BNX2_CP_CPQ_FTQ_DATA
BNX2_CP_CPU_DATA_ACCESS
BNX2_CP_CPU_DATA_ACCESS
BNX2_CP_CPU_DEBUG_VECT_PEEK
BNX2_CP_CPU_DEBUG_VECT_PEEK
BNX2_CP_CPU_DEBUG_VECT_PEEK_1_P
BNX2_CP_CPU_DEBUG_VECT_PEEK_1_P
BNX2_CP_CPU_DEBUG_VECT_PEEK_1_S
BNX2_CP_CPU_DEBUG_VECT_PEEK_1_S
BNX2_CP_CPU_DEBUG_VECT_PEEK_1_V
BNX2_CP_CPU_DEBUG_VECT_PEEK_1_V
BNX2_CP_CPU_DEBUG_VECT_PEEK_2_P
BNX2_CP_CPU_DEBUG_VECT_PEEK_2_P
BNX2_CP_CPU_DEBUG_VECT_PEEK_2_S
BNX2_CP_CPU_DEBUG_VECT_PEEK_2_S
BNX2_CP_CPU_DEBUG_VECT_PEEK_2_V
BNX2_CP_CPU_DEBUG_VECT_PEEK_2_V
BNX2_CP_CPU_EVENT_MASK
BNX2_CP_CPU_EVENT_MASK
BNX2_CP_CPU_EVENT_MASK_ALIGN_HA
BNX2_CP_CPU_EVENT_MASK_ALIGN_HA
BNX2_CP_CPU_EVENT_MASK_BAD_DATA
BNX2_CP_CPU_EVENT_MASK_BAD_DATA
BNX2_CP_CPU_EVENT_MASK_BAD_INST
BNX2_CP_CPU_EVENT_MASK_BAD_INST
BNX2_CP_CPU_EVENT_MASK_BAD_PC_H
BNX2_CP_CPU_EVENT_MASK_BAD_PC_H
BNX2_CP_CPU_EVENT_MASK_BREAKPOI
BNX2_CP_CPU_EVENT_MASK_BREAKPOI
BNX2_CP_CPU_EVENT_MASK_FIO_ABOR
BNX2_CP_CPU_EVENT_MASK_FIO_ABOR
BNX2_CP_CPU_EVENT_MASK_INTERRUP
BNX2_CP_CPU_EVENT_MASK_INTERRUP
BNX2_CP_CPU_EVENT_MASK_PAGE_0_D
BNX2_CP_CPU_EVENT_MASK_PAGE_0_D
BNX2_CP_CPU_EVENT_MASK_PAGE_0_I
BNX2_CP_CPU_EVENT_MASK_PAGE_0_I
BNX2_CP_CPU_EVENT_MASK_SOFT_HAL
BNX2_CP_CPU_EVENT_MASK_SOFT_HAL
BNX2_CP_CPU_EVENT_MASK_SPAD_UND
BNX2_CP_CPU_EVENT_MASK_SPAD_UND
BNX2_CP_CPU_HW_BREAKPOINT
BNX2_CP_CPU_HW_BREAKPOINT
BNX2_CP_CPU_HW_BREAKPOINT_ADDRE
BNX2_CP_CPU_HW_BREAKPOINT_ADDRE
BNX2_CP_CPU_HW_BREAKPOINT_DISAB
BNX2_CP_CPU_HW_BREAKPOINT_DISAB
BNX2_CP_CPU_INSTRUCTION
BNX2_CP_CPU_INSTRUCTION
BNX2_CP_CPU_INTERRUPT_ENABLE
BNX2_CP_CPU_INTERRUPT_ENABLE
BNX2_CP_CPU_INTERRUPT_SAVED_PC
BNX2_CP_CPU_INTERRUPT_SAVED_PC
BNX2_CP_CPU_INTERRUPT_VECTOR
BNX2_CP_CPU_INTERRUPT_VECTOR
BNX2_CP_CPU_LAST_BRANCH_ADDR
BNX2_CP_CPU_LAST_BRANCH_ADDR
BNX2_CP_CPU_LAST_BRANCH_ADDR_LB
BNX2_CP_CPU_LAST_BRANCH_ADDR_LB
BNX2_CP_CPU_LAST_BRANCH_ADDR_TY
BNX2_CP_CPU_LAST_BRANCH_ADDR_TY
BNX2_CP_CPU_LAST_BRANCH_ADDR_TY
BNX2_CP_CPU_LAST_BRANCH_ADDR_TY
BNX2_CP_CPU_LAST_BRANCH_ADDR_TY
BNX2_CP_CPU_LAST_BRANCH_ADDR_TY
BNX2_CP_CPU_MODE
BNX2_CP_CPU_MODE
BNX2_CP_CPU_MODE_BAD_DATA_HALT_
BNX2_CP_CPU_MODE_BAD_DATA_HALT_
BNX2_CP_CPU_MODE_BAD_INST_HALT_
BNX2_CP_CPU_MODE_BAD_INST_HALT_
BNX2_CP_CPU_MODE_FIO_ABORT_HALT
BNX2_CP_CPU_MODE_FIO_ABORT_HALT
BNX2_CP_CPU_MODE_INTERRUPT_ENA
BNX2_CP_CPU_MODE_INTERRUPT_ENA
BNX2_CP_CPU_MODE_LOCAL_RST
BNX2_CP_CPU_MODE_LOCAL_RST
BNX2_CP_CPU_MODE_MSG_BIT1
BNX2_CP_CPU_MODE_MSG_BIT1
BNX2_CP_CPU_MODE_PAGE_0_DATA_EN
BNX2_CP_CPU_MODE_PAGE_0_DATA_EN
BNX2_CP_CPU_MODE_PAGE_0_INST_EN
BNX2_CP_CPU_MODE_PAGE_0_INST_EN
BNX2_CP_CPU_MODE_SOFT_HALT
BNX2_CP_CPU_MODE_SOFT_HALT
BNX2_CP_CPU_MODE_SPAD_UNDERFLOW
BNX2_CP_CPU_MODE_SPAD_UNDERFLOW
BNX2_CP_CPU_MODE_STEP_ENA
BNX2_CP_CPU_MODE_STEP_ENA
BNX2_CP_CPU_PROGRAM_COUNTER
BNX2_CP_CPU_PROGRAM_COUNTER
BNX2_CP_CPU_REG_FILE
BNX2_CP_CPU_REG_FILE
BNX2_CP_CPU_STATE
BNX2_CP_CPU_STATE
BNX2_CP_CPU_STATE_ALIGN_HALTED
BNX2_CP_CPU_STATE_ALIGN_HALTED
BNX2_CP_CPU_STATE_BAD_DATA_ADDR
BNX2_CP_CPU_STATE_BAD_DATA_ADDR
BNX2_CP_CPU_STATE_BAD_INST_HALT
BNX2_CP_CPU_STATE_BAD_INST_HALT
BNX2_CP_CPU_STATE_BAD_pc_HALTED
BNX2_CP_CPU_STATE_BAD_pc_HALTED
BNX2_CP_CPU_STATE_BLOCKED_READ
BNX2_CP_CPU_STATE_BLOCKED_READ
BNX2_CP_CPU_STATE_BREAKPOINT
BNX2_CP_CPU_STATE_BREAKPOINT
BNX2_CP_CPU_STATE_DATA_ACCESS_S
BNX2_CP_CPU_STATE_DATA_ACCESS_S
BNX2_CP_CPU_STATE_FIO_ABORT_HAL
BNX2_CP_CPU_STATE_FIO_ABORT_HAL
BNX2_CP_CPU_STATE_INST_FETCH_ST
BNX2_CP_CPU_STATE_INST_FETCH_ST
BNX2_CP_CPU_STATE_INTERRRUPT
BNX2_CP_CPU_STATE_INTERRRUPT
BNX2_CP_CPU_STATE_PAGE_0_DATA_H
BNX2_CP_CPU_STATE_PAGE_0_DATA_H
BNX2_CP_CPU_STATE_PAGE_0_INST_H
BNX2_CP_CPU_STATE_PAGE_0_INST_H
BNX2_CP_CPU_STATE_SOFT_HALTED
BNX2_CP_CPU_STATE_SOFT_HALTED
BNX2_CP_CPU_STATE_SPAD_UNDERFLO
BNX2_CP_CPU_STATE_SPAD_UNDERFLO
BNX2_CP_SCRATCH
BNX2_CP_SCRATCH
BNX2_CTX_ACCESS_STATUS
BNX2_CTX_ACCESS_STATUS
BNX2_CTX_ACCESS_STATUS_ACCESSME
BNX2_CTX_ACCESS_STATUS_ACCESSME
BNX2_CTX_ACCESS_STATUS_ACCESSME
BNX2_CTX_ACCESS_STATUS_ACCESSME
BNX2_CTX_ACCESS_STATUS_MASTEREN
BNX2_CTX_ACCESS_STATUS_MASTEREN
BNX2_CTX_ACCESS_STATUS_PAGETABL
BNX2_CTX_ACCESS_STATUS_PAGETABL
BNX2_CTX_ACCESS_STATUS_QUALIFIE
BNX2_CTX_ACCESS_STATUS_QUALIFIE
BNX2_CTX_CHNL_LOCK_STATUS_0
BNX2_CTX_CHNL_LOCK_STATUS_0
BNX2_CTX_CHNL_LOCK_STATUS_0_CID
BNX2_CTX_CHNL_LOCK_STATUS_0_CID
BNX2_CTX_CHNL_LOCK_STATUS_0_MOD
BNX2_CTX_CHNL_LOCK_STATUS_0_MOD
BNX2_CTX_CHNL_LOCK_STATUS_0_TYP
BNX2_CTX_CHNL_LOCK_STATUS_0_TYP
BNX2_CTX_CHNL_LOCK_STATUS_1
BNX2_CTX_CHNL_LOCK_STATUS_1
BNX2_CTX_CHNL_LOCK_STATUS_2
BNX2_CTX_CHNL_LOCK_STATUS_2
BNX2_CTX_CHNL_LOCK_STATUS_3
BNX2_CTX_CHNL_LOCK_STATUS_3
BNX2_CTX_CHNL_LOCK_STATUS_4
BNX2_CTX_CHNL_LOCK_STATUS_4
BNX2_CTX_CHNL_LOCK_STATUS_5
BNX2_CTX_CHNL_LOCK_STATUS_5
BNX2_CTX_CHNL_LOCK_STATUS_6
BNX2_CTX_CHNL_LOCK_STATUS_6
BNX2_CTX_CHNL_LOCK_STATUS_7
BNX2_CTX_CHNL_LOCK_STATUS_7
BNX2_CTX_CHNL_LOCK_STATUS_8
BNX2_CTX_CHNL_LOCK_STATUS_8
BNX2_CTX_COMMAND
BNX2_CTX_COMMAND
BNX2_CTX_COMMAND_ENABLED
BNX2_CTX_COMMAND_ENABLED
BNX2_CTX_DATA
BNX2_CTX_DATA
BNX2_CTX_DATA_ADR
BNX2_CTX_DATA_ADR
BNX2_CTX_DATA_ADR_DATA_ADR
BNX2_CTX_DATA_ADR_DATA_ADR
BNX2_CTX_DBG_LOCK_STATUS
BNX2_CTX_DBG_LOCK_STATUS
BNX2_CTX_DBG_LOCK_STATUS_MATCH
BNX2_CTX_DBG_LOCK_STATUS_MATCH
BNX2_CTX_DBG_LOCK_STATUS_SM
BNX2_CTX_DBG_LOCK_STATUS_SM
BNX2_CTX_LOCK
BNX2_CTX_LOCK
BNX2_CTX_LOCK_CID_VALUE
BNX2_CTX_LOCK_CID_VALUE
BNX2_CTX_LOCK_GRANTED
BNX2_CTX_LOCK_GRANTED
BNX2_CTX_LOCK_MODE
BNX2_CTX_LOCK_MODE
BNX2_CTX_LOCK_MODE_IMMEDIATE
BNX2_CTX_LOCK_MODE_IMMEDIATE
BNX2_CTX_LOCK_MODE_SURE
BNX2_CTX_LOCK_MODE_SURE
BNX2_CTX_LOCK_MODE_UNLOCK
BNX2_CTX_LOCK_MODE_UNLOCK
BNX2_CTX_LOCK_REQ
BNX2_CTX_LOCK_REQ
BNX2_CTX_LOCK_STATUS
BNX2_CTX_LOCK_STATUS
BNX2_CTX_LOCK_TYPE
BNX2_CTX_LOCK_TYPE
BNX2_CTX_LOCK_TYPE_LOCK_TYPE_CO
BNX2_CTX_LOCK_TYPE_LOCK_TYPE_CO
BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PR
BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PR
BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TI
BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TI
BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX
BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX
BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VO
BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VO
BNX2_CTX_PAGE_TBL
BNX2_CTX_PAGE_TBL
BNX2_CTX_PAGE_TBL_PAGE_TBL
BNX2_CTX_PAGE_TBL_PAGE_TBL
BNX2_CTX_STATUS
BNX2_CTX_STATUS
BNX2_CTX_STATUS_ACC_STALL_STAT
BNX2_CTX_STATUS_ACC_STALL_STAT
BNX2_CTX_STATUS_LOCK_STALL_STAT
BNX2_CTX_STATUS_LOCK_STALL_STAT
BNX2_CTX_STATUS_LOCK_WAIT
BNX2_CTX_STATUS_LOCK_WAIT
BNX2_CTX_STATUS_READ_STAT
BNX2_CTX_STATUS_READ_STAT
BNX2_CTX_STATUS_WRITE_STAT
BNX2_CTX_STATUS_WRITE_STAT
BNX2_CTX_VIRT_ADDR
BNX2_CTX_VIRT_ADDR
BNX2_CTX_VIRT_ADDR_VIRT_ADDR
BNX2_CTX_VIRT_ADDR_VIRT_ADDR
bnx2_ctx_wr
bnx2_ctx_wr
BNX2_DEV_INFO_BC_REV
BNX2_DEV_INFO_BC_REV
BNX2_DEV_INFO_DRV_ALWAYS_ALIVE
BNX2_DEV_INFO_DRV_ALWAYS_ALIVE
BNX2_DEV_INFO_FEATURE_CFG_VALID
BNX2_DEV_INFO_FEATURE_CFG_VALID
BNX2_DEV_INFO_FORMAT_REV
BNX2_DEV_INFO_FORMAT_REV
BNX2_DEV_INFO_FORMAT_REV_ID
BNX2_DEV_INFO_FORMAT_REV_ID
BNX2_DEV_INFO_FORMAT_REV_MASK
BNX2_DEV_INFO_FORMAT_REV_MASK
BNX2_DEV_INFO_PER_PORT_HW_CONFI
BNX2_DEV_INFO_PER_PORT_HW_CONFI
BNX2_DEV_INFO_SECONDARY_PORT
BNX2_DEV_INFO_SECONDARY_PORT
BNX2_DEV_INFO_SIGNATURE
BNX2_DEV_INFO_SIGNATURE
BNX2_DEV_INFO_SIGNATURE_MAGIC
BNX2_DEV_INFO_SIGNATURE_MAGIC
BNX2_DEV_INFO_SIGNATURE_MAGIC_M
BNX2_DEV_INFO_SIGNATURE_MAGIC_M
bnx2_disable
bnx2_disable
bnx2_disable_int
bnx2_disable_int
bnx2_disable_nvram_access
bnx2_disable_nvram_access
BNX2_DMA_ARB_STAT_00
BNX2_DMA_ARB_STAT_00
BNX2_DMA_ARB_STAT_00_CUR_BINMST
BNX2_DMA_ARB_STAT_00_CUR_BINMST
BNX2_DMA_ARB_STAT_00_MASTER
BNX2_DMA_ARB_STAT_00_MASTER
BNX2_DMA_ARB_STAT_00_MASTER_ENC
BNX2_DMA_ARB_STAT_00_MASTER_ENC
BNX2_DMA_ARB_STAT_01
BNX2_DMA_ARB_STAT_01
BNX2_DMA_ARB_STAT_01_HPB_RPTR
BNX2_DMA_ARB_STAT_01_HPB_RPTR
BNX2_DMA_ARB_STAT_01_HPB_WPTR
BNX2_DMA_ARB_STAT_01_HPB_WPTR
BNX2_DMA_ARB_STAT_01_HPR_RPTR
BNX2_DMA_ARB_STAT_01_HPR_RPTR
BNX2_DMA_ARB_STAT_01_HPR_WPTR
BNX2_DMA_ARB_STAT_01_HPR_WPTR
BNX2_DMA_ARB_STAT_01_LPB_RPTR
BNX2_DMA_ARB_STAT_01_LPB_RPTR
BNX2_DMA_ARB_STAT_01_LPB_WPTR
BNX2_DMA_ARB_STAT_01_LPB_WPTR
BNX2_DMA_ARB_STAT_01_LPR_RPTR
BNX2_DMA_ARB_STAT_01_LPR_RPTR
BNX2_DMA_ARB_STAT_01_LPR_WPTR
BNX2_DMA_ARB_STAT_01_LPR_WPTR
BNX2_DMA_BLACKOUT
BNX2_DMA_BLACKOUT
BNX2_DMA_BLACKOUT_2ND_RD_RETRY_
BNX2_DMA_BLACKOUT_2ND_RD_RETRY_
BNX2_DMA_BLACKOUT_RD_RETRY_BLAC
BNX2_DMA_BLACKOUT_RD_RETRY_BLAC
BNX2_DMA_BLACKOUT_WR_RETRY_BLAC
BNX2_DMA_BLACKOUT_WR_RETRY_BLAC
BNX2_DMA_COMMAND
BNX2_DMA_COMMAND
BNX2_DMA_COMMAND_ENABLE
BNX2_DMA_COMMAND_ENABLE
BNX2_DMA_CONFIG
BNX2_DMA_CONFIG
BNX2_DMA_CONFIG_BIG_SIZE
BNX2_DMA_CONFIG_BIG_SIZE
BNX2_DMA_CONFIG_BIG_SIZE_128
BNX2_DMA_CONFIG_BIG_SIZE_128
BNX2_DMA_CONFIG_BIG_SIZE_256
BNX2_DMA_CONFIG_BIG_SIZE_256
BNX2_DMA_CONFIG_BIG_SIZE_512
BNX2_DMA_CONFIG_BIG_SIZE_512
BNX2_DMA_CONFIG_BIG_SIZE_64
BNX2_DMA_CONFIG_BIG_SIZE_64
BNX2_DMA_CONFIG_BIG_SIZE_NONE
BNX2_DMA_CONFIG_BIG_SIZE_NONE
BNX2_DMA_CONFIG_CNTL_BYTE_SWAP
BNX2_DMA_CONFIG_CNTL_BYTE_SWAP
BNX2_DMA_CONFIG_CNTL_FPGA_MODE
BNX2_DMA_CONFIG_CNTL_FPGA_MODE
BNX2_DMA_CONFIG_CNTL_PCI_COMP_D
BNX2_DMA_CONFIG_CNTL_PCI_COMP_D
BNX2_DMA_CONFIG_CNTL_PING_PONG_
BNX2_DMA_CONFIG_CNTL_PING_PONG_
BNX2_DMA_CONFIG_CNTL_TWO_DMA
BNX2_DMA_CONFIG_CNTL_TWO_DMA
BNX2_DMA_CONFIG_CNTL_WORD_SWAP
BNX2_DMA_CONFIG_CNTL_WORD_SWAP
BNX2_DMA_CONFIG_DATA_BYTE_SWAP
BNX2_DMA_CONFIG_DATA_BYTE_SWAP
BNX2_DMA_CONFIG_DATA_WORD_SWAP
BNX2_DMA_CONFIG_DATA_WORD_SWAP
BNX2_DMA_CONFIG_NO_RCHANS_IN_US
BNX2_DMA_CONFIG_NO_RCHANS_IN_US
BNX2_DMA_CONFIG_NO_WCHANS_IN_US
BNX2_DMA_CONFIG_NO_WCHANS_IN_US
BNX2_DMA_CONFIG_ONE_DMA
BNX2_DMA_CONFIG_ONE_DMA
BNX2_DMA_CONFIG_PCI_CLK_CMP_BIT
BNX2_DMA_CONFIG_PCI_CLK_CMP_BIT
BNX2_DMA_CONFIG_PCI_FAST_CLK_CM
BNX2_DMA_CONFIG_PCI_FAST_CLK_CM
BNX2_DMA_FUSE_CTRL0_CMD
BNX2_DMA_FUSE_CTRL0_CMD
BNX2_DMA_FUSE_CTRL0_CMD_LOAD
BNX2_DMA_FUSE_CTRL0_CMD_LOAD
BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_D
BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_D
BNX2_DMA_FUSE_CTRL0_CMD_SEL
BNX2_DMA_FUSE_CTRL0_CMD_SEL
BNX2_DMA_FUSE_CTRL0_CMD_SHIFT
BNX2_DMA_FUSE_CTRL0_CMD_SHIFT
BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_D
BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_D
BNX2_DMA_FUSE_CTRL0_DATA
BNX2_DMA_FUSE_CTRL0_DATA
BNX2_DMA_FUSE_CTRL1_CMD
BNX2_DMA_FUSE_CTRL1_CMD
BNX2_DMA_FUSE_CTRL1_CMD_LOAD
BNX2_DMA_FUSE_CTRL1_CMD_LOAD
BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_D
BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_D
BNX2_DMA_FUSE_CTRL1_CMD_SEL
BNX2_DMA_FUSE_CTRL1_CMD_SEL
BNX2_DMA_FUSE_CTRL1_CMD_SHIFT
BNX2_DMA_FUSE_CTRL1_CMD_SHIFT
BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_D
BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_D
BNX2_DMA_FUSE_CTRL1_DATA
BNX2_DMA_FUSE_CTRL1_DATA
BNX2_DMA_FUSE_CTRL2_CMD
BNX2_DMA_FUSE_CTRL2_CMD
BNX2_DMA_FUSE_CTRL2_CMD_LOAD
BNX2_DMA_FUSE_CTRL2_CMD_LOAD
BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_D
BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_D
BNX2_DMA_FUSE_CTRL2_CMD_SEL
BNX2_DMA_FUSE_CTRL2_CMD_SEL
BNX2_DMA_FUSE_CTRL2_CMD_SHIFT
BNX2_DMA_FUSE_CTRL2_CMD_SHIFT
BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_D
BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_D
BNX2_DMA_FUSE_CTRL2_DATA
BNX2_DMA_FUSE_CTRL2_DATA
BNX2_DMA_RCHAN_ASSIGNMENT
BNX2_DMA_RCHAN_ASSIGNMENT
BNX2_DMA_RCHAN_ASSIGNMENT_0
BNX2_DMA_RCHAN_ASSIGNMENT_0
BNX2_DMA_RCHAN_ASSIGNMENT_1
BNX2_DMA_RCHAN_ASSIGNMENT_1
BNX2_DMA_RCHAN_ASSIGNMENT_2
BNX2_DMA_RCHAN_ASSIGNMENT_2
BNX2_DMA_RCHAN_ASSIGNMENT_3
BNX2_DMA_RCHAN_ASSIGNMENT_3
BNX2_DMA_RCHAN_ASSIGNMENT_4
BNX2_DMA_RCHAN_ASSIGNMENT_4
BNX2_DMA_RCHAN_ASSIGNMENT_5
BNX2_DMA_RCHAN_ASSIGNMENT_5
BNX2_DMA_RCHAN_ASSIGNMENT_6
BNX2_DMA_RCHAN_ASSIGNMENT_6
BNX2_DMA_RCHAN_ASSIGNMENT_7
BNX2_DMA_RCHAN_ASSIGNMENT_7
BNX2_DMA_RCHAN_STAT
BNX2_DMA_RCHAN_STAT
BNX2_DMA_RCHAN_STAT_00
BNX2_DMA_RCHAN_STAT_00
BNX2_DMA_RCHAN_STAT_00_RCHAN_ST
BNX2_DMA_RCHAN_STAT_00_RCHAN_ST
BNX2_DMA_RCHAN_STAT_01
BNX2_DMA_RCHAN_STAT_01
BNX2_DMA_RCHAN_STAT_01_RCHAN_ST
BNX2_DMA_RCHAN_STAT_01_RCHAN_ST
BNX2_DMA_RCHAN_STAT_02
BNX2_DMA_RCHAN_STAT_02
BNX2_DMA_RCHAN_STAT_02_BYTE_SWA
BNX2_DMA_RCHAN_STAT_02_BYTE_SWA
BNX2_DMA_RCHAN_STAT_02_LENGTH
BNX2_DMA_RCHAN_STAT_02_LENGTH
BNX2_DMA_RCHAN_STAT_02_PRIORITY
BNX2_DMA_RCHAN_STAT_02_PRIORITY
BNX2_DMA_RCHAN_STAT_02_WORD_SWA
BNX2_DMA_RCHAN_STAT_02_WORD_SWA
BNX2_DMA_RCHAN_STAT_10
BNX2_DMA_RCHAN_STAT_10
BNX2_DMA_RCHAN_STAT_11
BNX2_DMA_RCHAN_STAT_11
BNX2_DMA_RCHAN_STAT_12
BNX2_DMA_RCHAN_STAT_12
BNX2_DMA_RCHAN_STAT_20
BNX2_DMA_RCHAN_STAT_20
BNX2_DMA_RCHAN_STAT_21
BNX2_DMA_RCHAN_STAT_21
BNX2_DMA_RCHAN_STAT_22
BNX2_DMA_RCHAN_STAT_22
BNX2_DMA_RCHAN_STAT_30
BNX2_DMA_RCHAN_STAT_30
BNX2_DMA_RCHAN_STAT_31
BNX2_DMA_RCHAN_STAT_31
BNX2_DMA_RCHAN_STAT_32
BNX2_DMA_RCHAN_STAT_32
BNX2_DMA_RCHAN_STAT_40
BNX2_DMA_RCHAN_STAT_40
BNX2_DMA_RCHAN_STAT_41
BNX2_DMA_RCHAN_STAT_41
BNX2_DMA_RCHAN_STAT_42
BNX2_DMA_RCHAN_STAT_42
BNX2_DMA_RCHAN_STAT_50
BNX2_DMA_RCHAN_STAT_50
BNX2_DMA_RCHAN_STAT_51
BNX2_DMA_RCHAN_STAT_51
BNX2_DMA_RCHAN_STAT_52
BNX2_DMA_RCHAN_STAT_52
BNX2_DMA_RCHAN_STAT_60
BNX2_DMA_RCHAN_STAT_60
BNX2_DMA_RCHAN_STAT_61
BNX2_DMA_RCHAN_STAT_61
BNX2_DMA_RCHAN_STAT_62
BNX2_DMA_RCHAN_STAT_62
BNX2_DMA_RCHAN_STAT_70
BNX2_DMA_RCHAN_STAT_70
BNX2_DMA_RCHAN_STAT_71
BNX2_DMA_RCHAN_STAT_71
BNX2_DMA_RCHAN_STAT_72
BNX2_DMA_RCHAN_STAT_72
BNX2_DMA_RCHAN_STAT_COMP_CODE_0
BNX2_DMA_RCHAN_STAT_COMP_CODE_0
BNX2_DMA_RCHAN_STAT_COMP_CODE_1
BNX2_DMA_RCHAN_STAT_COMP_CODE_1
BNX2_DMA_RCHAN_STAT_COMP_CODE_2
BNX2_DMA_RCHAN_STAT_COMP_CODE_2
BNX2_DMA_RCHAN_STAT_COMP_CODE_3
BNX2_DMA_RCHAN_STAT_COMP_CODE_3
BNX2_DMA_RCHAN_STAT_COMP_CODE_4
BNX2_DMA_RCHAN_STAT_COMP_CODE_4
BNX2_DMA_RCHAN_STAT_COMP_CODE_5
BNX2_DMA_RCHAN_STAT_COMP_CODE_5
BNX2_DMA_RCHAN_STAT_COMP_CODE_6
BNX2_DMA_RCHAN_STAT_COMP_CODE_6
BNX2_DMA_RCHAN_STAT_COMP_CODE_7
BNX2_DMA_RCHAN_STAT_COMP_CODE_7
BNX2_DMA_RCHAN_STAT_PAR_ERR_0
BNX2_DMA_RCHAN_STAT_PAR_ERR_0
BNX2_DMA_RCHAN_STAT_PAR_ERR_1
BNX2_DMA_RCHAN_STAT_PAR_ERR_1
BNX2_DMA_RCHAN_STAT_PAR_ERR_2
BNX2_DMA_RCHAN_STAT_PAR_ERR_2
BNX2_DMA_RCHAN_STAT_PAR_ERR_3
BNX2_DMA_RCHAN_STAT_PAR_ERR_3
BNX2_DMA_RCHAN_STAT_PAR_ERR_4
BNX2_DMA_RCHAN_STAT_PAR_ERR_4
BNX2_DMA_RCHAN_STAT_PAR_ERR_5
BNX2_DMA_RCHAN_STAT_PAR_ERR_5
BNX2_DMA_RCHAN_STAT_PAR_ERR_6
BNX2_DMA_RCHAN_STAT_PAR_ERR_6
BNX2_DMA_RCHAN_STAT_PAR_ERR_7
BNX2_DMA_RCHAN_STAT_PAR_ERR_7
BNX2_DMA_STATUS
BNX2_DMA_STATUS
BNX2_DMA_STATUS_BIG_READ_DELAY_
BNX2_DMA_STATUS_BIG_READ_DELAY_
BNX2_DMA_STATUS_BIG_READ_RETRY_
BNX2_DMA_STATUS_BIG_READ_RETRY_
BNX2_DMA_STATUS_BIG_READ_TRANSF
BNX2_DMA_STATUS_BIG_READ_TRANSF
BNX2_DMA_STATUS_BIG_WRITE_DELAY
BNX2_DMA_STATUS_BIG_WRITE_DELAY
BNX2_DMA_STATUS_BIG_WRITE_RETRY
BNX2_DMA_STATUS_BIG_WRITE_RETRY
BNX2_DMA_STATUS_BIG_WRITE_TRANS
BNX2_DMA_STATUS_BIG_WRITE_TRANS
BNX2_DMA_STATUS_PAR_ERROR_STATE
BNX2_DMA_STATUS_PAR_ERROR_STATE
BNX2_DMA_STATUS_READ_DELAY_PCI_
BNX2_DMA_STATUS_READ_DELAY_PCI_
BNX2_DMA_STATUS_READ_TRANSFERS_
BNX2_DMA_STATUS_READ_TRANSFERS_
BNX2_DMA_STATUS_WRITE_DELAY_PCI
BNX2_DMA_STATUS_WRITE_DELAY_PCI
BNX2_DMA_STATUS_WRITE_TRANSFERS
BNX2_DMA_STATUS_WRITE_TRANSFERS
BNX2_DMA_WCHAN_ASSIGNMENT
BNX2_DMA_WCHAN_ASSIGNMENT
BNX2_DMA_WCHAN_ASSIGNMENT_0
BNX2_DMA_WCHAN_ASSIGNMENT_0
BNX2_DMA_WCHAN_ASSIGNMENT_1
BNX2_DMA_WCHAN_ASSIGNMENT_1
BNX2_DMA_WCHAN_ASSIGNMENT_2
BNX2_DMA_WCHAN_ASSIGNMENT_2
BNX2_DMA_WCHAN_ASSIGNMENT_3
BNX2_DMA_WCHAN_ASSIGNMENT_3
BNX2_DMA_WCHAN_ASSIGNMENT_4
BNX2_DMA_WCHAN_ASSIGNMENT_4
BNX2_DMA_WCHAN_ASSIGNMENT_5
BNX2_DMA_WCHAN_ASSIGNMENT_5
BNX2_DMA_WCHAN_ASSIGNMENT_6
BNX2_DMA_WCHAN_ASSIGNMENT_6
BNX2_DMA_WCHAN_ASSIGNMENT_7
BNX2_DMA_WCHAN_ASSIGNMENT_7
BNX2_DMA_WCHAN_STAT
BNX2_DMA_WCHAN_STAT
BNX2_DMA_WCHAN_STAT_00
BNX2_DMA_WCHAN_STAT_00
BNX2_DMA_WCHAN_STAT_00_WCHAN_ST
BNX2_DMA_WCHAN_STAT_00_WCHAN_ST
BNX2_DMA_WCHAN_STAT_01
BNX2_DMA_WCHAN_STAT_01
BNX2_DMA_WCHAN_STAT_01_WCHAN_ST
BNX2_DMA_WCHAN_STAT_01_WCHAN_ST
BNX2_DMA_WCHAN_STAT_02
BNX2_DMA_WCHAN_STAT_02
BNX2_DMA_WCHAN_STAT_02_BYTE_SWA
BNX2_DMA_WCHAN_STAT_02_BYTE_SWA
BNX2_DMA_WCHAN_STAT_02_LENGTH
BNX2_DMA_WCHAN_STAT_02_LENGTH
BNX2_DMA_WCHAN_STAT_02_PRIORITY
BNX2_DMA_WCHAN_STAT_02_PRIORITY
BNX2_DMA_WCHAN_STAT_02_WORD_SWA
BNX2_DMA_WCHAN_STAT_02_WORD_SWA
BNX2_DMA_WCHAN_STAT_10
BNX2_DMA_WCHAN_STAT_10
BNX2_DMA_WCHAN_STAT_11
BNX2_DMA_WCHAN_STAT_11
BNX2_DMA_WCHAN_STAT_12
BNX2_DMA_WCHAN_STAT_12
BNX2_DMA_WCHAN_STAT_20
BNX2_DMA_WCHAN_STAT_20
BNX2_DMA_WCHAN_STAT_21
BNX2_DMA_WCHAN_STAT_21
BNX2_DMA_WCHAN_STAT_22
BNX2_DMA_WCHAN_STAT_22
BNX2_DMA_WCHAN_STAT_30
BNX2_DMA_WCHAN_STAT_30
BNX2_DMA_WCHAN_STAT_31
BNX2_DMA_WCHAN_STAT_31
BNX2_DMA_WCHAN_STAT_32
BNX2_DMA_WCHAN_STAT_32
BNX2_DMA_WCHAN_STAT_40
BNX2_DMA_WCHAN_STAT_40
BNX2_DMA_WCHAN_STAT_41
BNX2_DMA_WCHAN_STAT_41
BNX2_DMA_WCHAN_STAT_42
BNX2_DMA_WCHAN_STAT_42
BNX2_DMA_WCHAN_STAT_50
BNX2_DMA_WCHAN_STAT_50
BNX2_DMA_WCHAN_STAT_51
BNX2_DMA_WCHAN_STAT_51
BNX2_DMA_WCHAN_STAT_52
BNX2_DMA_WCHAN_STAT_52
BNX2_DMA_WCHAN_STAT_60
BNX2_DMA_WCHAN_STAT_60
BNX2_DMA_WCHAN_STAT_61
BNX2_DMA_WCHAN_STAT_61
BNX2_DMA_WCHAN_STAT_62
BNX2_DMA_WCHAN_STAT_62
BNX2_DMA_WCHAN_STAT_70
BNX2_DMA_WCHAN_STAT_70
BNX2_DMA_WCHAN_STAT_71
BNX2_DMA_WCHAN_STAT_71
BNX2_DMA_WCHAN_STAT_72
BNX2_DMA_WCHAN_STAT_72
BNX2_DMA_WCHAN_STAT_COMP_CODE_0
BNX2_DMA_WCHAN_STAT_COMP_CODE_0
BNX2_DMA_WCHAN_STAT_COMP_CODE_1
BNX2_DMA_WCHAN_STAT_COMP_CODE_1
BNX2_DMA_WCHAN_STAT_COMP_CODE_2
BNX2_DMA_WCHAN_STAT_COMP_CODE_2
BNX2_DMA_WCHAN_STAT_COMP_CODE_3
BNX2_DMA_WCHAN_STAT_COMP_CODE_3
BNX2_DMA_WCHAN_STAT_COMP_CODE_4
BNX2_DMA_WCHAN_STAT_COMP_CODE_4
BNX2_DMA_WCHAN_STAT_COMP_CODE_5
BNX2_DMA_WCHAN_STAT_COMP_CODE_5
BNX2_DMA_WCHAN_STAT_COMP_CODE_6
BNX2_DMA_WCHAN_STAT_COMP_CODE_6
BNX2_DMA_WCHAN_STAT_COMP_CODE_7
BNX2_DMA_WCHAN_STAT_COMP_CODE_7
BNX2_DMA_WCHAN_STAT_PAR_ERR_0
BNX2_DMA_WCHAN_STAT_PAR_ERR_0
BNX2_DMA_WCHAN_STAT_PAR_ERR_1
BNX2_DMA_WCHAN_STAT_PAR_ERR_1
BNX2_DMA_WCHAN_STAT_PAR_ERR_2
BNX2_DMA_WCHAN_STAT_PAR_ERR_2
BNX2_DMA_WCHAN_STAT_PAR_ERR_3
BNX2_DMA_WCHAN_STAT_PAR_ERR_3
BNX2_DMA_WCHAN_STAT_PAR_ERR_4
BNX2_DMA_WCHAN_STAT_PAR_ERR_4
BNX2_DMA_WCHAN_STAT_PAR_ERR_5
BNX2_DMA_WCHAN_STAT_PAR_ERR_5
BNX2_DMA_WCHAN_STAT_PAR_ERR_6
BNX2_DMA_WCHAN_STAT_PAR_ERR_6
BNX2_DMA_WCHAN_STAT_PAR_ERR_7
BNX2_DMA_WCHAN_STAT_PAR_ERR_7
BNX2_DRV_MB
BNX2_DRV_MB
BNX2_DRV_MSG_CODE
BNX2_DRV_MSG_CODE
BNX2_DRV_MSG_CODE_DIAG
BNX2_DRV_MSG_CODE_DIAG
BNX2_DRV_MSG_CODE_FW_TIMEOUT
BNX2_DRV_MSG_CODE_FW_TIMEOUT
BNX2_DRV_MSG_CODE_PULSE
BNX2_DRV_MSG_CODE_PULSE
BNX2_DRV_MSG_CODE_RESET
BNX2_DRV_MSG_CODE_RESET
BNX2_DRV_MSG_CODE_SHUTDOWN
BNX2_DRV_MSG_CODE_SHUTDOWN
BNX2_DRV_MSG_CODE_SUSPEND_NO_WO
BNX2_DRV_MSG_CODE_SUSPEND_NO_WO
BNX2_DRV_MSG_CODE_SUSPEND_WOL
BNX2_DRV_MSG_CODE_SUSPEND_WOL
BNX2_DRV_MSG_CODE_UNLOAD
BNX2_DRV_MSG_CODE_UNLOAD
BNX2_DRV_MSG_DATA
BNX2_DRV_MSG_DATA
BNX2_DRV_MSG_DATA_PULSE_CODE_AL
BNX2_DRV_MSG_DATA_PULSE_CODE_AL
BNX2_DRV_MSG_DATA_WAIT0
BNX2_DRV_MSG_DATA_WAIT0
BNX2_DRV_MSG_DATA_WAIT1
BNX2_DRV_MSG_DATA_WAIT1
BNX2_DRV_MSG_DATA_WAIT2
BNX2_DRV_MSG_DATA_WAIT2
BNX2_DRV_MSG_DATA_WAIT3
BNX2_DRV_MSG_DATA_WAIT3
BNX2_DRV_MSG_SEQ
BNX2_DRV_MSG_SEQ
BNX2_DRV_PULSE_MB
BNX2_DRV_PULSE_MB
BNX2_DRV_PULSE_SEQ_MASK
BNX2_DRV_PULSE_SEQ_MASK
BNX2_DRV_RESET_SIGNATURE
BNX2_DRV_RESET_SIGNATURE
BNX2_DRV_RESET_SIGNATURE_MAGIC	HAVK
BNX2_DRV_RESET_SIGNATURE_MAGIC	HAVK
BNX2_EMAC_ATTENTION_ENA
BNX2_EMAC_ATTENTION_ENA
BNX2_EMAC_ATTENTION_ENA_AP_ERRO
BNX2_EMAC_ATTENTION_ENA_AP_ERRO
BNX2_EMAC_ATTENTION_ENA_LINK
BNX2_EMAC_ATTENTION_ENA_LINK
BNX2_EMAC_ATTENTION_ENA_MI_COMP
BNX2_EMAC_ATTENTION_ENA_MI_COMP
BNX2_EMAC_ATTENTION_ENA_MI_INT
BNX2_EMAC_ATTENTION_ENA_MI_INT
BNX2_EMAC_BACKOFF_SEED
BNX2_EMAC_BACKOFF_SEED
BNX2_EMAC_BACKOFF_SEED_EMAC_BAC
BNX2_EMAC_BACKOFF_SEED_EMAC_BAC
BNX2_EMAC_LED
BNX2_EMAC_LED
BNX2_EMAC_LED_1000MB
BNX2_EMAC_LED_1000MB
BNX2_EMAC_LED_1000MB_OVERRIDE
BNX2_EMAC_LED_1000MB_OVERRIDE
BNX2_EMAC_LED_100MB
BNX2_EMAC_LED_100MB
BNX2_EMAC_LED_100MB_OVERRIDE
BNX2_EMAC_LED_100MB_OVERRIDE
BNX2_EMAC_LED_10MB
BNX2_EMAC_LED_10MB
BNX2_EMAC_LED_10MB_OVERRIDE
BNX2_EMAC_LED_10MB_OVERRIDE
BNX2_EMAC_LED_BLNK_RATE
BNX2_EMAC_LED_BLNK_RATE
BNX2_EMAC_LED_BLNK_RATE_ENA
BNX2_EMAC_LED_BLNK_RATE_ENA
BNX2_EMAC_LED_BLNK_TRAFFIC
BNX2_EMAC_LED_BLNK_TRAFFIC
BNX2_EMAC_LED_OVERRIDE
BNX2_EMAC_LED_OVERRIDE
BNX2_EMAC_LED_TRAFFIC
BNX2_EMAC_LED_TRAFFIC
BNX2_EMAC_LED_TRAFFIC_OVERRIDE
BNX2_EMAC_LED_TRAFFIC_OVERRIDE
BNX2_EMAC_LED_TRAFFIC_STAT
BNX2_EMAC_LED_TRAFFIC_STAT
BNX2_EMAC_MAC_MATCH0
BNX2_EMAC_MAC_MATCH0
BNX2_EMAC_MAC_MATCH1
BNX2_EMAC_MAC_MATCH1
BNX2_EMAC_MAC_MATCH10
BNX2_EMAC_MAC_MATCH10
BNX2_EMAC_MAC_MATCH11
BNX2_EMAC_MAC_MATCH11
BNX2_EMAC_MAC_MATCH12
BNX2_EMAC_MAC_MATCH12
BNX2_EMAC_MAC_MATCH13
BNX2_EMAC_MAC_MATCH13
BNX2_EMAC_MAC_MATCH14
BNX2_EMAC_MAC_MATCH14
BNX2_EMAC_MAC_MATCH15
BNX2_EMAC_MAC_MATCH15
BNX2_EMAC_MAC_MATCH16
BNX2_EMAC_MAC_MATCH16
BNX2_EMAC_MAC_MATCH17
BNX2_EMAC_MAC_MATCH17
BNX2_EMAC_MAC_MATCH18
BNX2_EMAC_MAC_MATCH18
BNX2_EMAC_MAC_MATCH19
BNX2_EMAC_MAC_MATCH19
BNX2_EMAC_MAC_MATCH2
BNX2_EMAC_MAC_MATCH2
BNX2_EMAC_MAC_MATCH20
BNX2_EMAC_MAC_MATCH20
BNX2_EMAC_MAC_MATCH21
BNX2_EMAC_MAC_MATCH21
BNX2_EMAC_MAC_MATCH22
BNX2_EMAC_MAC_MATCH22
BNX2_EMAC_MAC_MATCH23
BNX2_EMAC_MAC_MATCH23
BNX2_EMAC_MAC_MATCH24
BNX2_EMAC_MAC_MATCH24
BNX2_EMAC_MAC_MATCH25
BNX2_EMAC_MAC_MATCH25
BNX2_EMAC_MAC_MATCH26
BNX2_EMAC_MAC_MATCH26
BNX2_EMAC_MAC_MATCH27
BNX2_EMAC_MAC_MATCH27
BNX2_EMAC_MAC_MATCH28
BNX2_EMAC_MAC_MATCH28
BNX2_EMAC_MAC_MATCH29
BNX2_EMAC_MAC_MATCH29
BNX2_EMAC_MAC_MATCH3
BNX2_EMAC_MAC_MATCH3
BNX2_EMAC_MAC_MATCH30
BNX2_EMAC_MAC_MATCH30
BNX2_EMAC_MAC_MATCH31
BNX2_EMAC_MAC_MATCH31
BNX2_EMAC_MAC_MATCH4
BNX2_EMAC_MAC_MATCH4
BNX2_EMAC_MAC_MATCH5
BNX2_EMAC_MAC_MATCH5
BNX2_EMAC_MAC_MATCH6
BNX2_EMAC_MAC_MATCH6
BNX2_EMAC_MAC_MATCH7
BNX2_EMAC_MAC_MATCH7
BNX2_EMAC_MAC_MATCH8
BNX2_EMAC_MAC_MATCH8
BNX2_EMAC_MAC_MATCH9
BNX2_EMAC_MAC_MATCH9
BNX2_EMAC_MDIO_AUTO_STATUS
BNX2_EMAC_MDIO_AUTO_STATUS
BNX2_EMAC_MDIO_AUTO_STATUS_AUTO
BNX2_EMAC_MDIO_AUTO_STATUS_AUTO
BNX2_EMAC_MDIO_COMM
BNX2_EMAC_MDIO_COMM
BNX2_EMAC_MDIO_COMM_COMMAND
BNX2_EMAC_MDIO_COMM_COMMAND
BNX2_EMAC_MDIO_COMM_COMMAND_REA
BNX2_EMAC_MDIO_COMM_COMMAND_REA
BNX2_EMAC_MDIO_COMM_COMMAND_UND
BNX2_EMAC_MDIO_COMM_COMMAND_UND
BNX2_EMAC_MDIO_COMM_COMMAND_UND
BNX2_EMAC_MDIO_COMM_COMMAND_UND
BNX2_EMAC_MDIO_COMM_COMMAND_WRI
BNX2_EMAC_MDIO_COMM_COMMAND_WRI
BNX2_EMAC_MDIO_COMM_DATA
BNX2_EMAC_MDIO_COMM_DATA
BNX2_EMAC_MDIO_COMM_DISEXT
BNX2_EMAC_MDIO_COMM_DISEXT
BNX2_EMAC_MDIO_COMM_FAIL
BNX2_EMAC_MDIO_COMM_FAIL
BNX2_EMAC_MDIO_COMM_PHY_ADDR
BNX2_EMAC_MDIO_COMM_PHY_ADDR
BNX2_EMAC_MDIO_COMM_REG_ADDR
BNX2_EMAC_MDIO_COMM_REG_ADDR
BNX2_EMAC_MDIO_COMM_START_BUSY
BNX2_EMAC_MDIO_COMM_START_BUSY
BNX2_EMAC_MDIO_MODE
BNX2_EMAC_MDIO_MODE
BNX2_EMAC_MDIO_MODE_AUTO_POLL
BNX2_EMAC_MDIO_MODE_AUTO_POLL
BNX2_EMAC_MDIO_MODE_BIT_BANG
BNX2_EMAC_MDIO_MODE_BIT_BANG
BNX2_EMAC_MDIO_MODE_CLOCK_CNT
BNX2_EMAC_MDIO_MODE_CLOCK_CNT
BNX2_EMAC_MDIO_MODE_MDC
BNX2_EMAC_MDIO_MODE_MDC
BNX2_EMAC_MDIO_MODE_MDINT
BNX2_EMAC_MDIO_MODE_MDINT
BNX2_EMAC_MDIO_MODE_MDIO
BNX2_EMAC_MDIO_MODE_MDIO
BNX2_EMAC_MDIO_MODE_MDIO_OE
BNX2_EMAC_MDIO_MODE_MDIO_OE
BNX2_EMAC_MDIO_MODE_SHORT_PREAM
BNX2_EMAC_MDIO_MODE_SHORT_PREAM
BNX2_EMAC_MDIO_STATUS
BNX2_EMAC_MDIO_STATUS
BNX2_EMAC_MDIO_STATUS_10MB
BNX2_EMAC_MDIO_STATUS_10MB
BNX2_EMAC_MDIO_STATUS_LINK
BNX2_EMAC_MDIO_STATUS_LINK
BNX2_EMAC_MODE
BNX2_EMAC_MODE
BNX2_EMAC_MODE_25G
BNX2_EMAC_MODE_25G
BNX2_EMAC_MODE_ACPI_RCVD
BNX2_EMAC_MODE_ACPI_RCVD
BNX2_EMAC_MODE_EXT_LINK_POL
BNX2_EMAC_MODE_EXT_LINK_POL
BNX2_EMAC_MODE_FORCE_LINK
BNX2_EMAC_MODE_FORCE_LINK
BNX2_EMAC_MODE_HALF_DUPLEX
BNX2_EMAC_MODE_HALF_DUPLEX
BNX2_EMAC_MODE_MAC_LOOP
BNX2_EMAC_MODE_MAC_LOOP
BNX2_EMAC_MODE_MAX_DEFER_DROP_E
BNX2_EMAC_MODE_MAX_DEFER_DROP_E
BNX2_EMAC_MODE_MPKT
BNX2_EMAC_MODE_MPKT
BNX2_EMAC_MODE_MPKT_RCVD
BNX2_EMAC_MODE_MPKT_RCVD
BNX2_EMAC_MODE_PORT
BNX2_EMAC_MODE_PORT
BNX2_EMAC_MODE_PORT_GMII
BNX2_EMAC_MODE_PORT_GMII
BNX2_EMAC_MODE_PORT_MII
BNX2_EMAC_MODE_PORT_MII
BNX2_EMAC_MODE_PORT_MII_10
BNX2_EMAC_MODE_PORT_MII_10
BNX2_EMAC_MODE_PORT_NONE
BNX2_EMAC_MODE_PORT_NONE
BNX2_EMAC_MODE_RESET
BNX2_EMAC_MODE_RESET
BNX2_EMAC_MODE_TAGGED_MAC_CTL
BNX2_EMAC_MODE_TAGGED_MAC_CTL
BNX2_EMAC_MODE_TX_BURST
BNX2_EMAC_MODE_TX_BURST
BNX2_EMAC_MULTICAST_HASH0
BNX2_EMAC_MULTICAST_HASH0
BNX2_EMAC_MULTICAST_HASH1
BNX2_EMAC_MULTICAST_HASH1
BNX2_EMAC_MULTICAST_HASH2
BNX2_EMAC_MULTICAST_HASH2
BNX2_EMAC_MULTICAST_HASH3
BNX2_EMAC_MULTICAST_HASH3
BNX2_EMAC_MULTICAST_HASH4
BNX2_EMAC_MULTICAST_HASH4
BNX2_EMAC_MULTICAST_HASH5
BNX2_EMAC_MULTICAST_HASH5
BNX2_EMAC_MULTICAST_HASH6
BNX2_EMAC_MULTICAST_HASH6
BNX2_EMAC_MULTICAST_HASH7
BNX2_EMAC_MULTICAST_HASH7
BNX2_EMAC_RX_MODE
BNX2_EMAC_RX_MODE
BNX2_EMAC_RX_MODE_ACCEPT_OVERSI
BNX2_EMAC_RX_MODE_ACCEPT_OVERSI
BNX2_EMAC_RX_MODE_ACCEPT_RUNTS
BNX2_EMAC_RX_MODE_ACCEPT_RUNTS
BNX2_EMAC_RX_MODE_FILT_BROADCAS
BNX2_EMAC_RX_MODE_FILT_BROADCAS
BNX2_EMAC_RX_MODE_FLOW_EN
BNX2_EMAC_RX_MODE_FLOW_EN
BNX2_EMAC_RX_MODE_KEEP_MAC_CONT
BNX2_EMAC_RX_MODE_KEEP_MAC_CONT
BNX2_EMAC_RX_MODE_KEEP_PAUSE
BNX2_EMAC_RX_MODE_KEEP_PAUSE
BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
BNX2_EMAC_RX_MODE_LLC_CHK
BNX2_EMAC_RX_MODE_LLC_CHK
BNX2_EMAC_RX_MODE_NO_CRC_CHK
BNX2_EMAC_RX_MODE_NO_CRC_CHK
BNX2_EMAC_RX_MODE_PROMISCUOUS
BNX2_EMAC_RX_MODE_PROMISCUOUS
BNX2_EMAC_RX_MODE_RESET
BNX2_EMAC_RX_MODE_RESET
BNX2_EMAC_RX_MODE_SORT_MODE
BNX2_EMAC_RX_MODE_SORT_MODE
BNX2_EMAC_RX_MTU_SIZE
BNX2_EMAC_RX_MTU_SIZE
BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA
BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA
BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE
BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE
BNX2_EMAC_RX_STAT_AC0
BNX2_EMAC_RX_STAT_AC0
BNX2_EMAC_RX_STAT_AC1
BNX2_EMAC_RX_STAT_AC1
BNX2_EMAC_RX_STAT_AC10
BNX2_EMAC_RX_STAT_AC10
BNX2_EMAC_RX_STAT_AC11
BNX2_EMAC_RX_STAT_AC11
BNX2_EMAC_RX_STAT_AC12
BNX2_EMAC_RX_STAT_AC12
BNX2_EMAC_RX_STAT_AC13
BNX2_EMAC_RX_STAT_AC13
BNX2_EMAC_RX_STAT_AC14
BNX2_EMAC_RX_STAT_AC14
BNX2_EMAC_RX_STAT_AC15
BNX2_EMAC_RX_STAT_AC15
BNX2_EMAC_RX_STAT_AC16
BNX2_EMAC_RX_STAT_AC16
BNX2_EMAC_RX_STAT_AC17
BNX2_EMAC_RX_STAT_AC17
BNX2_EMAC_RX_STAT_AC18
BNX2_EMAC_RX_STAT_AC18
BNX2_EMAC_RX_STAT_AC19
BNX2_EMAC_RX_STAT_AC19
BNX2_EMAC_RX_STAT_AC2
BNX2_EMAC_RX_STAT_AC2
BNX2_EMAC_RX_STAT_AC20
BNX2_EMAC_RX_STAT_AC20
BNX2_EMAC_RX_STAT_AC21
BNX2_EMAC_RX_STAT_AC21
BNX2_EMAC_RX_STAT_AC22
BNX2_EMAC_RX_STAT_AC22
BNX2_EMAC_RX_STAT_AC3
BNX2_EMAC_RX_STAT_AC3
BNX2_EMAC_RX_STAT_AC4
BNX2_EMAC_RX_STAT_AC4
BNX2_EMAC_RX_STAT_AC5
BNX2_EMAC_RX_STAT_AC5
BNX2_EMAC_RX_STAT_AC6
BNX2_EMAC_RX_STAT_AC6
BNX2_EMAC_RX_STAT_AC7
BNX2_EMAC_RX_STAT_AC7
BNX2_EMAC_RX_STAT_AC8
BNX2_EMAC_RX_STAT_AC8
BNX2_EMAC_RX_STAT_AC9
BNX2_EMAC_RX_STAT_AC9
BNX2_EMAC_RX_STAT_DOT3STATSALIG
BNX2_EMAC_RX_STAT_DOT3STATSALIG
BNX2_EMAC_RX_STAT_DOT3STATSCARR
BNX2_EMAC_RX_STAT_DOT3STATSCARR
BNX2_EMAC_RX_STAT_DOT3STATSFCSE
BNX2_EMAC_RX_STAT_DOT3STATSFCSE
BNX2_EMAC_RX_STAT_DOT3STATSFRAM
BNX2_EMAC_RX_STAT_DOT3STATSFRAM
BNX2_EMAC_RX_STAT_ETHERSTATSFRA
BNX2_EMAC_RX_STAT_ETHERSTATSFRA
BNX2_EMAC_RX_STAT_ETHERSTATSJAB
BNX2_EMAC_RX_STAT_ETHERSTATSJAB
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSPKT
BNX2_EMAC_RX_STAT_ETHERSTATSUND
BNX2_EMAC_RX_STAT_ETHERSTATSUND
BNX2_EMAC_RX_STAT_IFHCINBADOCTE
BNX2_EMAC_RX_STAT_IFHCINBADOCTE
BNX2_EMAC_RX_STAT_IFHCINBROADCA
BNX2_EMAC_RX_STAT_IFHCINBROADCA
BNX2_EMAC_RX_STAT_IFHCINMULTICA
BNX2_EMAC_RX_STAT_IFHCINMULTICA
BNX2_EMAC_RX_STAT_IFHCINOCTETS
BNX2_EMAC_RX_STAT_IFHCINOCTETS
BNX2_EMAC_RX_STAT_IFHCINUCASTPK
BNX2_EMAC_RX_STAT_IFHCINUCASTPK
BNX2_EMAC_RX_STAT_MACCONTROLFRA
BNX2_EMAC_RX_STAT_MACCONTROLFRA
BNX2_EMAC_RX_STAT_XOFFPAUSEFRAM
BNX2_EMAC_RX_STAT_XOFFPAUSEFRAM
BNX2_EMAC_RX_STAT_XOFFSTATEENTE
BNX2_EMAC_RX_STAT_XOFFSTATEENTE
BNX2_EMAC_RX_STAT_XONPAUSEFRAME
BNX2_EMAC_RX_STAT_XONPAUSEFRAME
BNX2_EMAC_RX_STATUS
BNX2_EMAC_RX_STATUS
BNX2_EMAC_RX_STATUS_FF_RECEIVED
BNX2_EMAC_RX_STATUS_FF_RECEIVED
BNX2_EMAC_RX_STATUS_FFED
BNX2_EMAC_RX_STATUS_FFED
BNX2_EMAC_RX_STATUS_N_RECEIVED
BNX2_EMAC_RX_STATUS_N_RECEIVED
BNX2_EMAC_RXMAC_DEBUG0
BNX2_EMAC_RXMAC_DEBUG0
BNX2_EMAC_RXMAC_DEBUG1
BNX2_EMAC_RXMAC_DEBUG1
BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ER
BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ER
BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC
BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC
BNX2_EMAC_RXMAC_DEBUG1_BYTE_COU
BNX2_EMAC_RXMAC_DEBUG1_BYTE_COU
BNX2_EMAC_RXMAC_DEBUG1_LAST_DAT
BNX2_EMAC_RXMAC_DEBUG1_LAST_DAT
BNX2_EMAC_RXMAC_DEBUG1_LENGTH_N
BNX2_EMAC_RXMAC_DEBUG1_LENGTH_N
BNX2_EMAC_RXMAC_DEBUG1_LENGTH_O
BNX2_EMAC_RXMAC_DEBUG1_LENGTH_O
BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE
BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE
BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR
BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR
BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIM
BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIM
BNX2_EMAC_RXMAC_DEBUG2
BNX2_EMAC_RXMAC_DEBUG2
BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN
BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN
BNX2_EMAC_RXMAC_DEBUG2_FALSEC
BNX2_EMAC_RXMAC_DEBUG2_FALSEC
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_IDI_STAT
BNX2_EMAC_RXMAC_DEBUG2_PAUSE_ST
BNX2_EMAC_RXMAC_DEBUG2_PAUSE_ST
BNX2_EMAC_RXMAC_DEBUG2_PAUSE_ST
BNX2_EMAC_RXMAC_DEBUG2_PAUSE_ST
BNX2_EMAC_RXMAC_DEBUG2_PAUSE_ST
BNX2_EMAC_RXMAC_DEBUG2_PAUSE_ST
BNX2_EMAC_RXMAC_DEBUG2_QUANTA
BNX2_EMAC_RXMAC_DEBUG2_QUANTA
BNX2_EMAC_RXMAC_DEBUG2_SE_COUNT
BNX2_EMAC_RXMAC_DEBUG2_SE_COUNT
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
BNX2_EMAC_RXMAC_DEBUG2_TAGGED
BNX2_EMAC_RXMAC_DEBUG2_TAGGED
BNX2_EMAC_RXMAC_DEBUG3
BNX2_EMAC_RXMAC_DEBUG3
BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CT
BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CT
BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUS
BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUS
BNX2_EMAC_RXMAC_DEBUG4
BNX2_EMAC_RXMAC_DEBUG4
BNX2_EMAC_RXMAC_DEBUG4_ADVANCE
BNX2_EMAC_RXMAC_DEBUG4_ADVANCE
BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT
BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT
BNX2_EMAC_RXMAC_DEBUG4_FALSE_CA
BNX2_EMAC_RXMAC_DEBUG4_FALSE_CA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_FILT_STA
BNX2_EMAC_RXMAC_DEBUG4_LAST_DAT
BNX2_EMAC_RXMAC_DEBUG4_LAST_DAT
BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUN
BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUN
BNX2_EMAC_RXMAC_DEBUG4_SLOT_FIL
BNX2_EMAC_RXMAC_DEBUG4_SLOT_FIL
BNX2_EMAC_RXMAC_DEBUG4_START
BNX2_EMAC_RXMAC_DEBUG4_START
BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIE
BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIE
BNX2_EMAC_RXMAC_DEBUG5
BNX2_EMAC_RXMAC_DEBUG5
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CCODE_BU
BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT
BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT
BNX2_EMAC_RXMAC_DEBUG5_EOF_DETE
BNX2_EMAC_RXMAC_DEBUG5_EOF_DETE
BNX2_EMAC_RXMAC_DEBUG5_FMLEN
BNX2_EMAC_RXMAC_DEBUG5_FMLEN
BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_
BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_
BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_
BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_
BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCO
BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCO
BNX2_EMAC_RXMAC_DEBUG5_LOAD_DAT
BNX2_EMAC_RXMAC_DEBUG5_LOAD_DAT
BNX2_EMAC_RXMAC_DEBUG5_LOAD_STA
BNX2_EMAC_RXMAC_DEBUG5_LOAD_STA
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_
BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_
BNX2_EMAC_RXMAC_SUC_DBG_OVERRUN
BNX2_EMAC_RXMAC_SUC_DBG_OVERRUN
BNX2_EMAC_SERDES_CNTL
BNX2_EMAC_SERDES_CNTL
BNX2_EMAC_SERDES_CNTL_BGMAX
BNX2_EMAC_SERDES_CNTL_BGMAX
BNX2_EMAC_SERDES_CNTL_BGMIN
BNX2_EMAC_SERDES_CNTL_BGMIN
BNX2_EMAC_SERDES_CNTL_CDET_EN
BNX2_EMAC_SERDES_CNTL_CDET_EN
BNX2_EMAC_SERDES_CNTL_PLLTEST
BNX2_EMAC_SERDES_CNTL_PLLTEST
BNX2_EMAC_SERDES_CNTL_REGCTL12
BNX2_EMAC_SERDES_CNTL_REGCTL12
BNX2_EMAC_SERDES_CNTL_REGCTL25
BNX2_EMAC_SERDES_CNTL_REGCTL25
BNX2_EMAC_SERDES_CNTL_REMOTE_LB
BNX2_EMAC_SERDES_CNTL_REMOTE_LB
BNX2_EMAC_SERDES_CNTL_REV_PHASE
BNX2_EMAC_SERDES_CNTL_REV_PHASE
BNX2_EMAC_SERDES_CNTL_RXCKSEL
BNX2_EMAC_SERDES_CNTL_RXCKSEL
BNX2_EMAC_SERDES_CNTL_RXG
BNX2_EMAC_SERDES_CNTL_RXG
BNX2_EMAC_SERDES_CNTL_RXR
BNX2_EMAC_SERDES_CNTL_RXR
BNX2_EMAC_SERDES_CNTL_SERDES_MO
BNX2_EMAC_SERDES_CNTL_SERDES_MO
BNX2_EMAC_SERDES_CNTL_TBI_LBK
BNX2_EMAC_SERDES_CNTL_TBI_LBK
BNX2_EMAC_SERDES_CNTL_TXBIAS
BNX2_EMAC_SERDES_CNTL_TXBIAS
BNX2_EMAC_SERDES_CNTL_TXEDGE
BNX2_EMAC_SERDES_CNTL_TXEDGE
BNX2_EMAC_SERDES_CNTL_TXMODE
BNX2_EMAC_SERDES_CNTL_TXMODE
BNX2_EMAC_SERDES_STATUS
BNX2_EMAC_SERDES_STATUS
BNX2_EMAC_SERDES_STATUS_COMMA_D
BNX2_EMAC_SERDES_STATUS_COMMA_D
BNX2_EMAC_SERDES_STATUS_RX_STAT
BNX2_EMAC_SERDES_STATUS_RX_STAT
BNX2_EMAC_STATUS
BNX2_EMAC_STATUS
BNX2_EMAC_STATUS_AP_ERROR
BNX2_EMAC_STATUS_AP_ERROR
BNX2_EMAC_STATUS_LINK
BNX2_EMAC_STATUS_LINK
BNX2_EMAC_STATUS_LINK_CHANGE
BNX2_EMAC_STATUS_LINK_CHANGE
BNX2_EMAC_STATUS_MI_COMPLETE
BNX2_EMAC_STATUS_MI_COMPLETE
BNX2_EMAC_STATUS_MI_INT
BNX2_EMAC_STATUS_MI_INT
BNX2_EMAC_STATUS_PARITY_ERROR_S
BNX2_EMAC_STATUS_PARITY_ERROR_S
BNX2_EMAC_TX_LENGTHS
BNX2_EMAC_TX_LENGTHS
BNX2_EMAC_TX_LENGTHS_IPG
BNX2_EMAC_TX_LENGTHS_IPG
BNX2_EMAC_TX_LENGTHS_IPG_CRS
BNX2_EMAC_TX_LENGTHS_IPG_CRS
BNX2_EMAC_TX_LENGTHS_SLOT
BNX2_EMAC_TX_LENGTHS_SLOT
BNX2_EMAC_TX_MODE
BNX2_EMAC_TX_MODE
BNX2_EMAC_TX_MODE_BIG_BACKOFF
BNX2_EMAC_TX_MODE_BIG_BACKOFF
BNX2_EMAC_TX_MODE_EXT_PAUSE_EN
BNX2_EMAC_TX_MODE_EXT_PAUSE_EN
BNX2_EMAC_TX_MODE_FLOW_EN
BNX2_EMAC_TX_MODE_FLOW_EN
BNX2_EMAC_TX_MODE_LINK_AWARE
BNX2_EMAC_TX_MODE_LINK_AWARE
BNX2_EMAC_TX_MODE_LONG_PAUSE
BNX2_EMAC_TX_MODE_LONG_PAUSE
BNX2_EMAC_TX_MODE_RESET
BNX2_EMAC_TX_MODE_RESET
BNX2_EMAC_TX_STAT_AC0
BNX2_EMAC_TX_STAT_AC0
BNX2_EMAC_TX_STAT_AC1
BNX2_EMAC_TX_STAT_AC1
BNX2_EMAC_TX_STAT_AC10
BNX2_EMAC_TX_STAT_AC10
BNX2_EMAC_TX_STAT_AC11
BNX2_EMAC_TX_STAT_AC11
BNX2_EMAC_TX_STAT_AC12
BNX2_EMAC_TX_STAT_AC12
BNX2_EMAC_TX_STAT_AC13
BNX2_EMAC_TX_STAT_AC13
BNX2_EMAC_TX_STAT_AC14
BNX2_EMAC_TX_STAT_AC14
BNX2_EMAC_TX_STAT_AC15
BNX2_EMAC_TX_STAT_AC15
BNX2_EMAC_TX_STAT_AC16
BNX2_EMAC_TX_STAT_AC16
BNX2_EMAC_TX_STAT_AC17
BNX2_EMAC_TX_STAT_AC17
BNX2_EMAC_TX_STAT_AC18
BNX2_EMAC_TX_STAT_AC18
BNX2_EMAC_TX_STAT_AC19
BNX2_EMAC_TX_STAT_AC19
BNX2_EMAC_TX_STAT_AC2
BNX2_EMAC_TX_STAT_AC2
BNX2_EMAC_TX_STAT_AC20
BNX2_EMAC_TX_STAT_AC20
BNX2_EMAC_TX_STAT_AC21
BNX2_EMAC_TX_STAT_AC21
BNX2_EMAC_TX_STAT_AC3
BNX2_EMAC_TX_STAT_AC3
BNX2_EMAC_TX_STAT_AC4
BNX2_EMAC_TX_STAT_AC4
BNX2_EMAC_TX_STAT_AC5
BNX2_EMAC_TX_STAT_AC5
BNX2_EMAC_TX_STAT_AC6
BNX2_EMAC_TX_STAT_AC6
BNX2_EMAC_TX_STAT_AC7
BNX2_EMAC_TX_STAT_AC7
BNX2_EMAC_TX_STAT_AC8
BNX2_EMAC_TX_STAT_AC8
BNX2_EMAC_TX_STAT_AC9
BNX2_EMAC_TX_STAT_AC9
BNX2_EMAC_TX_STAT_DOT3STATSDEFE
BNX2_EMAC_TX_STAT_DOT3STATSDEFE
BNX2_EMAC_TX_STAT_DOT3STATSEXCE
BNX2_EMAC_TX_STAT_DOT3STATSEXCE
BNX2_EMAC_TX_STAT_DOT3STATSINTE
BNX2_EMAC_TX_STAT_DOT3STATSINTE
BNX2_EMAC_TX_STAT_DOT3STATSLATE
BNX2_EMAC_TX_STAT_DOT3STATSLATE
BNX2_EMAC_TX_STAT_DOT3STATSMULT
BNX2_EMAC_TX_STAT_DOT3STATSMULT
BNX2_EMAC_TX_STAT_DOT3STATSSING
BNX2_EMAC_TX_STAT_DOT3STATSSING
BNX2_EMAC_TX_STAT_ETHERSTATSCOL
BNX2_EMAC_TX_STAT_ETHERSTATSCOL
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_ETHERSTATSPKT
BNX2_EMAC_TX_STAT_FLOWCONTROLDO
BNX2_EMAC_TX_STAT_FLOWCONTROLDO
BNX2_EMAC_TX_STAT_IFHCOUTBADOCT
BNX2_EMAC_TX_STAT_IFHCOUTBADOCT
BNX2_EMAC_TX_STAT_IFHCOUTBROADC
BNX2_EMAC_TX_STAT_IFHCOUTBROADC
BNX2_EMAC_TX_STAT_IFHCOUTMULTIC
BNX2_EMAC_TX_STAT_IFHCOUTMULTIC
BNX2_EMAC_TX_STAT_IFHCOUTOCTETS
BNX2_EMAC_TX_STAT_IFHCOUTOCTETS
BNX2_EMAC_TX_STAT_IFHCOUTUCASTP
BNX2_EMAC_TX_STAT_IFHCOUTUCASTP
BNX2_EMAC_TX_STAT_OUTXOFFSENT
BNX2_EMAC_TX_STAT_OUTXOFFSENT
BNX2_EMAC_TX_STAT_OUTXONSENT
BNX2_EMAC_TX_STAT_OUTXONSENT
BNX2_EMAC_TX_STATUS
BNX2_EMAC_TX_STATUS
BNX2_EMAC_TX_STATUS_LINK_UP
BNX2_EMAC_TX_STATUS_LINK_UP
BNX2_EMAC_TX_STATUS_UNDERRUN
BNX2_EMAC_TX_STATUS_UNDERRUN
BNX2_EMAC_TX_STATUS_XOFF_SENT
BNX2_EMAC_TX_STATUS_XOFF_SENT
BNX2_EMAC_TX_STATUS_XOFFED
BNX2_EMAC_TX_STATUS_XOFFED
BNX2_EMAC_TX_STATUS_XON_SENT
BNX2_EMAC_TX_STATUS_XON_SENT
BNX2_EMAC_TXMAC_DEBUG0
BNX2_EMAC_TXMAC_DEBUG0
BNX2_EMAC_TXMAC_DEBUG1
BNX2_EMAC_TXMAC_DEBUG1
BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC
BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC
BNX2_EMAC_TXMAC_DEBUG1_CRS_ENAB
BNX2_EMAC_TXMAC_DEBUG1_CRS_ENAB
BNX2_EMAC_TXMAC_DEBUG1_DEFERRED
BNX2_EMAC_TXMAC_DEBUG1_DEFERRED
BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME
BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME
BNX2_EMAC_TXMAC_DEBUG1_LATE_COL
BNX2_EMAC_TXMAC_DEBUG1_LATE_COL
BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFE
BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFE
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ODI_STAT
BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE
BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE
BNX2_EMAC_TXMAC_DEBUG1_SE_COUNT
BNX2_EMAC_TXMAC_DEBUG1_SE_COUNT
BNX2_EMAC_TXMAC_DEBUG1_SEND_PAU
BNX2_EMAC_TXMAC_DEBUG1_SEND_PAU
BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIM
BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIM
BNX2_EMAC_TXMAC_DEBUG2
BNX2_EMAC_TXMAC_DEBUG2
BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF
BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF
BNX2_EMAC_TXMAC_DEBUG2_BYTE_COU
BNX2_EMAC_TXMAC_DEBUG2_BYTE_COU
BNX2_EMAC_TXMAC_DEBUG2_COL_BIT
BNX2_EMAC_TXMAC_DEBUG2_COL_BIT
BNX2_EMAC_TXMAC_DEBUG2_COL_COUN
BNX2_EMAC_TXMAC_DEBUG2_COL_COUN
BNX2_EMAC_TXMAC_DEBUG3
BNX2_EMAC_TXMAC_DEBUG3
BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE
BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_FILT_STA
BNX2_EMAC_TXMAC_DEBUG3_QUANTA_C
BNX2_EMAC_TXMAC_DEBUG3_QUANTA_C
BNX2_EMAC_TXMAC_DEBUG3_SE_COUNT
BNX2_EMAC_TXMAC_DEBUG3_SE_COUNT
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
BNX2_EMAC_TXMAC_DEBUG3_XOFF
BNX2_EMAC_TXMAC_DEBUG3_XOFF
BNX2_EMAC_TXMAC_DEBUG4
BNX2_EMAC_TXMAC_DEBUG4
BNX2_EMAC_TXMAC_DEBUG4_ADVANCE
BNX2_EMAC_TXMAC_DEBUG4_ADVANCE
BNX2_EMAC_TXMAC_DEBUG4_APPEND_C
BNX2_EMAC_TXMAC_DEBUG4_APPEND_C
BNX2_EMAC_TXMAC_DEBUG4_BURSTING
BNX2_EMAC_TXMAC_DEBUG4_BURSTING
BNX2_EMAC_TXMAC_DEBUG4_COL_IN
BNX2_EMAC_TXMAC_DEBUG4_COL_IN
BNX2_EMAC_TXMAC_DEBUG4_COLLIDIN
BNX2_EMAC_TXMAC_DEBUG4_COLLIDIN
BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC
BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC
BNX2_EMAC_TXMAC_DEBUG4_GO
BNX2_EMAC_TXMAC_DEBUG4_GO
BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFE
BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFE
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_CO
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_CO
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST
BNX2_EMAC_TXMAC_DEBUG4_SEND_EXT
BNX2_EMAC_TXMAC_DEBUG4_SEND_EXT
BNX2_EMAC_TXMAC_DEBUG4_SEND_PAD
BNX2_EMAC_TXMAC_DEBUG4_SEND_PAD
BNX2_EMAC_TXMAC_DEBUG4_SLOT_FIL
BNX2_EMAC_TXMAC_DEBUG4_SLOT_FIL
BNX2_EMAC_TXMAC_DEBUG4_STATS0_V
BNX2_EMAC_TXMAC_DEBUG4_STATS0_V
BNX2_EMAC_TXMAC_SUC_DBG_OVERRUN
BNX2_EMAC_TXMAC_SUC_DBG_OVERRUN
bnx2_enable_nvram_access
bnx2_enable_nvram_access
bnx2_fw.h
bnx2_fw.h
BNX2_FW_MB
BNX2_FW_MB
BNX2_FW_MSG_ACK
BNX2_FW_MSG_ACK
BNX2_FW_MSG_STATUS_FAILURE
BNX2_FW_MSG_STATUS_FAILURE
BNX2_FW_MSG_STATUS_MASK
BNX2_FW_MSG_STATUS_MASK
BNX2_FW_MSG_STATUS_OK
BNX2_FW_MSG_STATUS_OK
bnx2_fw_sync
bnx2_fw_sync
BNX2_HC_ATTN_BITS_ENABLE
BNX2_HC_ATTN_BITS_ENABLE
BNX2_HC_CMD_TICKS
BNX2_HC_CMD_TICKS
BNX2_HC_CMD_TICKS_INT
BNX2_HC_CMD_TICKS_INT
BNX2_HC_CMD_TICKS_VALUE
BNX2_HC_CMD_TICKS_VALUE
BNX2_HC_COM_TICKS
BNX2_HC_COM_TICKS
BNX2_HC_COM_TICKS_INT
BNX2_HC_COM_TICKS_INT
BNX2_HC_COM_TICKS_VALUE
BNX2_HC_COM_TICKS_VALUE
BNX2_HC_COMMAND
BNX2_HC_COMMAND
BNX2_HC_COMMAND_CLR_STAT_NOW
BNX2_HC_COMMAND_CLR_STAT_NOW
BNX2_HC_COMMAND_COAL_NOW
BNX2_HC_COMMAND_COAL_NOW
BNX2_HC_COMMAND_COAL_NOW_WO_INT
BNX2_HC_COMMAND_COAL_NOW_WO_INT
BNX2_HC_COMMAND_ENABLE
BNX2_HC_COMMAND_ENABLE
BNX2_HC_COMMAND_FORCE_INT
BNX2_HC_COMMAND_FORCE_INT
BNX2_HC_COMMAND_FORCE_INT_FREE
BNX2_HC_COMMAND_FORCE_INT_FREE
BNX2_HC_COMMAND_FORCE_INT_HIGH
BNX2_HC_COMMAND_FORCE_INT_HIGH
BNX2_HC_COMMAND_FORCE_INT_LOW
BNX2_HC_COMMAND_FORCE_INT_LOW
BNX2_HC_COMMAND_FORCE_INT_NULL
BNX2_HC_COMMAND_FORCE_INT_NULL
BNX2_HC_COMMAND_SKIP_ABORT
BNX2_HC_COMMAND_SKIP_ABORT
BNX2_HC_COMMAND_STATS_NOW
BNX2_HC_COMMAND_STATS_NOW
BNX2_HC_COMP_PROD_TRIP
BNX2_HC_COMP_PROD_TRIP
BNX2_HC_COMP_PROD_TRIP_INT
BNX2_HC_COMP_PROD_TRIP_INT
BNX2_HC_COMP_PROD_TRIP_VALUE
BNX2_HC_COMP_PROD_TRIP_VALUE
BNX2_HC_CONFIG
BNX2_HC_CONFIG
BNX2_HC_CONFIG_CMD_TMR_MODE
BNX2_HC_CONFIG_CMD_TMR_MODE
BNX2_HC_CONFIG_COLLECT_STATS
BNX2_HC_CONFIG_COLLECT_STATS
BNX2_HC_CONFIG_COM_TMR_MODE
BNX2_HC_CONFIG_COM_TMR_MODE
BNX2_HC_CONFIG_RX_TMR_MODE
BNX2_HC_CONFIG_RX_TMR_MODE
BNX2_HC_CONFIG_STAT_MEM_ADDR
BNX2_HC_CONFIG_STAT_MEM_ADDR
BNX2_HC_CONFIG_STATISTIC_PRIORI
BNX2_HC_CONFIG_STATISTIC_PRIORI
BNX2_HC_CONFIG_STATUS_PRIORITY
BNX2_HC_CONFIG_STATUS_PRIORITY
BNX2_HC_CONFIG_TX_TMR_MODE
BNX2_HC_CONFIG_TX_TMR_MODE
BNX2_HC_DEBUG_VECT_PEEK
BNX2_HC_DEBUG_VECT_PEEK
BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_
BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_
BNX2_HC_DEBUG_VECT_PEEK_1_SEL
BNX2_HC_DEBUG_VECT_PEEK_1_SEL
BNX2_HC_DEBUG_VECT_PEEK_1_VALUE
BNX2_HC_DEBUG_VECT_PEEK_1_VALUE
BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_
BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_
BNX2_HC_DEBUG_VECT_PEEK_2_SEL
BNX2_HC_DEBUG_VECT_PEEK_2_SEL
BNX2_HC_DEBUG_VECT_PEEK_2_VALUE
BNX2_HC_DEBUG_VECT_PEEK_2_VALUE
BNX2_HC_PERIODIC_TICKS
BNX2_HC_PERIODIC_TICKS
BNX2_HC_PERIODIC_TICKS_HC_PERIO
BNX2_HC_PERIODIC_TICKS_HC_PERIO
BNX2_HC_RX_QUICK_CONS_TRIP
BNX2_HC_RX_QUICK_CONS_TRIP
BNX2_HC_RX_QUICK_CONS_TRIP_INT
BNX2_HC_RX_QUICK_CONS_TRIP_INT
BNX2_HC_RX_QUICK_CONS_TRIP_VALU
BNX2_HC_RX_QUICK_CONS_TRIP_VALU
BNX2_HC_RX_TICKS
BNX2_HC_RX_TICKS
BNX2_HC_RX_TICKS_INT
BNX2_HC_RX_TICKS_INT
BNX2_HC_RX_TICKS_VALUE
BNX2_HC_RX_TICKS_VALUE
BNX2_HC_STAT_COLLECT_TICKS
BNX2_HC_STAT_COLLECT_TICKS
BNX2_HC_STAT_COLLECT_TICKS_HC_S
BNX2_HC_STAT_COLLECT_TICKS_HC_S
BNX2_HC_STAT_GEN_SEL_0
BNX2_HC_STAT_GEN_SEL_0
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_1
BNX2_HC_STAT_GEN_SEL_1
BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_2
BNX2_HC_STAT_GEN_SEL_2
BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_3
BNX2_HC_STAT_GEN_SEL_3
BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_
BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_
BNX2_HC_STAT_GEN_STAT_AC0
BNX2_HC_STAT_GEN_STAT_AC0
BNX2_HC_STAT_GEN_STAT_AC1
BNX2_HC_STAT_GEN_STAT_AC1
BNX2_HC_STAT_GEN_STAT_AC10
BNX2_HC_STAT_GEN_STAT_AC10
BNX2_HC_STAT_GEN_STAT_AC11
BNX2_HC_STAT_GEN_STAT_AC11
BNX2_HC_STAT_GEN_STAT_AC12
BNX2_HC_STAT_GEN_STAT_AC12
BNX2_HC_STAT_GEN_STAT_AC13
BNX2_HC_STAT_GEN_STAT_AC13
BNX2_HC_STAT_GEN_STAT_AC14
BNX2_HC_STAT_GEN_STAT_AC14
BNX2_HC_STAT_GEN_STAT_AC15
BNX2_HC_STAT_GEN_STAT_AC15
BNX2_HC_STAT_GEN_STAT_AC2
BNX2_HC_STAT_GEN_STAT_AC2
BNX2_HC_STAT_GEN_STAT_AC3
BNX2_HC_STAT_GEN_STAT_AC3
BNX2_HC_STAT_GEN_STAT_AC4
BNX2_HC_STAT_GEN_STAT_AC4
BNX2_HC_STAT_GEN_STAT_AC5
BNX2_HC_STAT_GEN_STAT_AC5
BNX2_HC_STAT_GEN_STAT_AC6
BNX2_HC_STAT_GEN_STAT_AC6
BNX2_HC_STAT_GEN_STAT_AC7
BNX2_HC_STAT_GEN_STAT_AC7
BNX2_HC_STAT_GEN_STAT_AC8
BNX2_HC_STAT_GEN_STAT_AC8
BNX2_HC_STAT_GEN_STAT_AC9
BNX2_HC_STAT_GEN_STAT_AC9
BNX2_HC_STAT_GEN_STAT0
BNX2_HC_STAT_GEN_STAT0
BNX2_HC_STAT_GEN_STAT1
BNX2_HC_STAT_GEN_STAT1
BNX2_HC_STAT_GEN_STAT10
BNX2_HC_STAT_GEN_STAT10
BNX2_HC_STAT_GEN_STAT11
BNX2_HC_STAT_GEN_STAT11
BNX2_HC_STAT_GEN_STAT12
BNX2_HC_STAT_GEN_STAT12
BNX2_HC_STAT_GEN_STAT13
BNX2_HC_STAT_GEN_STAT13
BNX2_HC_STAT_GEN_STAT14
BNX2_HC_STAT_GEN_STAT14
BNX2_HC_STAT_GEN_STAT15
BNX2_HC_STAT_GEN_STAT15
BNX2_HC_STAT_GEN_STAT2
BNX2_HC_STAT_GEN_STAT2
BNX2_HC_STAT_GEN_STAT3
BNX2_HC_STAT_GEN_STAT3
BNX2_HC_STAT_GEN_STAT4
BNX2_HC_STAT_GEN_STAT4
BNX2_HC_STAT_GEN_STAT5
BNX2_HC_STAT_GEN_STAT5
BNX2_HC_STAT_GEN_STAT6
BNX2_HC_STAT_GEN_STAT6
BNX2_HC_STAT_GEN_STAT7
BNX2_HC_STAT_GEN_STAT7
BNX2_HC_STAT_GEN_STAT8
BNX2_HC_STAT_GEN_STAT8
BNX2_HC_STAT_GEN_STAT9
BNX2_HC_STAT_GEN_STAT9
BNX2_HC_STAT_MEM_DATA
BNX2_HC_STAT_MEM_DATA
BNX2_HC_STATISTICS_ADDR_H
BNX2_HC_STATISTICS_ADDR_H
BNX2_HC_STATISTICS_ADDR_L
BNX2_HC_STATISTICS_ADDR_L
BNX2_HC_STATS_TICKS
BNX2_HC_STATS_TICKS
BNX2_HC_STATS_TICKS_HC_STAT_TIC
BNX2_HC_STATS_TICKS_HC_STAT_TIC
BNX2_HC_STATUS
BNX2_HC_STATUS
BNX2_HC_STATUS_ADDR_H
BNX2_HC_STATUS_ADDR_H
BNX2_HC_STATUS_ADDR_L
BNX2_HC_STATUS_ADDR_L
BNX2_HC_STATUS_CORE_CLK_CNT_STA
BNX2_HC_STATUS_CORE_CLK_CNT_STA
BNX2_HC_STATUS_CORE_CLKS_DURING
BNX2_HC_STATUS_CORE_CLKS_DURING
BNX2_HC_STATUS_CORE_CLKS_TO_HW_
BNX2_HC_STATUS_CORE_CLKS_TO_HW_
BNX2_HC_STATUS_CORE_CLKS_TO_SW_
BNX2_HC_STATUS_CORE_CLKS_TO_SW_
BNX2_HC_STATUS_MASTER_ABORT
BNX2_HC_STATUS_MASTER_ABORT
BNX2_HC_STATUS_NUM_INT_GEN_STAT
BNX2_HC_STATUS_NUM_INT_GEN_STAT
BNX2_HC_STATUS_NUM_INT_MBOX_WR_
BNX2_HC_STATUS_NUM_INT_MBOX_WR_
BNX2_HC_STATUS_NUM_STATUS_BLOCK
BNX2_HC_STATUS_NUM_STATUS_BLOCK
BNX2_HC_STATUS_PARITY_ERROR_STA
BNX2_HC_STATUS_PARITY_ERROR_STA
BNX2_HC_STATUS_PCI_CLK_CNT_STAT
BNX2_HC_STATUS_PCI_CLK_CNT_STAT
BNX2_HC_TX_QUICK_CONS_TRIP
BNX2_HC_TX_QUICK_CONS_TRIP
BNX2_HC_TX_QUICK_CONS_TRIP_INT
BNX2_HC_TX_QUICK_CONS_TRIP_INT
BNX2_HC_TX_QUICK_CONS_TRIP_VALU
BNX2_HC_TX_QUICK_CONS_TRIP_VALU
BNX2_HC_TX_TICKS
BNX2_HC_TX_TICKS
BNX2_HC_TX_TICKS_INT
BNX2_HC_TX_TICKS_INT
BNX2_HC_TX_TICKS_VALUE
BNX2_HC_TX_TICKS_VALUE
BNX2_HC_VIS
BNX2_HC_VIS
BNX2_HC_VIS_1
BNX2_HC_VIS_1
BNX2_HC_VIS_1_DURING_SW_INTACK_
BNX2_HC_VIS_1_DURING_SW_INTACK_
BNX2_HC_VIS_1_DURING_SW_INTACK_
BNX2_HC_VIS_1_DURING_SW_INTACK_
BNX2_HC_VIS_1_DURING_SW_INTACK_
BNX2_HC_VIS_1_DURING_SW_INTACK_
BNX2_HC_VIS_1_HW_INTACK_STATE
BNX2_HC_VIS_1_HW_INTACK_STATE
BNX2_HC_VIS_1_HW_INTACK_STATE_C
BNX2_HC_VIS_1_HW_INTACK_STATE_C
BNX2_HC_VIS_1_HW_INTACK_STATE_I
BNX2_HC_VIS_1_HW_INTACK_STATE_I
BNX2_HC_VIS_1_INT_B
BNX2_HC_VIS_1_INT_B
BNX2_HC_VIS_1_INT_GEN_STATE
BNX2_HC_VIS_1_INT_GEN_STATE
BNX2_HC_VIS_1_INT_GEN_STATE_DLE
BNX2_HC_VIS_1_INT_GEN_STATE_DLE
BNX2_HC_VIS_1_INT_GEN_STATE_NTE
BNX2_HC_VIS_1_INT_GEN_STATE_NTE
BNX2_HC_VIS_1_MAILBOX_COUNT_STA
BNX2_HC_VIS_1_MAILBOX_COUNT_STA
BNX2_HC_VIS_1_MAILBOX_COUNT_STA
BNX2_HC_VIS_1_MAILBOX_COUNT_STA
BNX2_HC_VIS_1_MAILBOX_COUNT_STA
BNX2_HC_VIS_1_MAILBOX_COUNT_STA
BNX2_HC_VIS_1_RAM_RD_ARB_STATE
BNX2_HC_VIS_1_RAM_RD_ARB_STATE
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_RD_ARB_STATE_
BNX2_HC_VIS_1_RAM_WR_ARB_STATE
BNX2_HC_VIS_1_RAM_WR_ARB_STATE
BNX2_HC_VIS_1_RAM_WR_ARB_STATE_
BNX2_HC_VIS_1_RAM_WR_ARB_STATE_
BNX2_HC_VIS_1_RAM_WR_ARB_STATE_
BNX2_HC_VIS_1_RAM_WR_ARB_STATE_
BNX2_HC_VIS_1_STAT_CHAN_ID
BNX2_HC_VIS_1_STAT_CHAN_ID
BNX2_HC_VIS_1_SW_INTACK_STATE
BNX2_HC_VIS_1_SW_INTACK_STATE
BNX2_HC_VIS_1_SW_INTACK_STATE_C
BNX2_HC_VIS_1_SW_INTACK_STATE_C
BNX2_HC_VIS_1_SW_INTACK_STATE_I
BNX2_HC_VIS_1_SW_INTACK_STATE_I
BNX2_HC_VIS_DMA_MSI_STATE
BNX2_HC_VIS_DMA_MSI_STATE
BNX2_HC_VIS_DMA_STAT_STATE
BNX2_HC_VIS_DMA_STAT_STATE
BNX2_HC_VIS_DMA_STAT_STATE_ABOR
BNX2_HC_VIS_DMA_STAT_STATE_ABOR
BNX2_HC_VIS_DMA_STAT_STATE_COMP
BNX2_HC_VIS_DMA_STAT_STATE_COMP
BNX2_HC_VIS_DMA_STAT_STATE_IDLE
BNX2_HC_VIS_DMA_STAT_STATE_IDLE
BNX2_HC_VIS_DMA_STAT_STATE_STAT
BNX2_HC_VIS_DMA_STAT_STATE_STAT
BNX2_HC_VIS_DMA_STAT_STATE_STAT
BNX2_HC_VIS_DMA_STAT_STATE_STAT
BNX2_HC_VIS_DMA_STAT_STATE_STAT
BNX2_HC_VIS_DMA_STAT_STATE_STAT
BNX2_HC_VIS_DMA_STAT_STATE_STAT
BNX2_HC_VIS_DMA_STAT_STATE_STAT
BNX2_HC_VIS_DMA_STAT_STATE_WAIT
BNX2_HC_VIS_DMA_STAT_STATE_WAIT
BNX2_HC_VIS_DMA_STAT_STATE_WRIT
BNX2_HC_VIS_DMA_STAT_STATE_WRIT
BNX2_HC_VIS_DMA_STAT_STATE_WRIT
BNX2_HC_VIS_DMA_STAT_STATE_WRIT
BNX2_HC_VIS_DMA_STAT_STATE_WRIT
BNX2_HC_VIS_DMA_STAT_STATE_WRIT
BNX2_HC_VIS_STAT_BUILD_STATE
BNX2_HC_VIS_STAT_BUILD_STATE
BNX2_HC_VIS_STAT_BUILD_STATE_DM
BNX2_HC_VIS_STAT_BUILD_STATE_DM
BNX2_HC_VIS_STAT_BUILD_STATE_ID
BNX2_HC_VIS_STAT_BUILD_STATE_ID
BNX2_HC_VIS_STAT_BUILD_STATE_MS
BNX2_HC_VIS_STAT_BUILD_STATE_MS
BNX2_HC_VIS_STAT_BUILD_STATE_MS
BNX2_HC_VIS_STAT_BUILD_STATE_MS
BNX2_HC_VIS_STAT_BUILD_STATE_MS
BNX2_HC_VIS_STAT_BUILD_STATE_MS
BNX2_HC_VIS_STAT_BUILD_STATE_MS
BNX2_HC_VIS_STAT_BUILD_STATE_MS
BNX2_HC_VIS_STAT_BUILD_STATE_RE
BNX2_HC_VIS_STAT_BUILD_STATE_RE
BNX2_HC_VIS_STAT_BUILD_STATE_ST
BNX2_HC_VIS_STAT_BUILD_STATE_ST
BNX2_HC_VIS_STAT_BUILD_STATE_UP
BNX2_HC_VIS_STAT_BUILD_STATE_UP
BNX2_HC_VIS_STAT_BUILD_STATE_UP
BNX2_HC_VIS_STAT_BUILD_STATE_UP
BNX2_HC_VIS_STAT_BUILD_STATE_UP
BNX2_HC_VIS_STAT_BUILD_STATE_UP
BNX2_HC_VIS_STATISTIC_DMA_EN_ST
BNX2_HC_VIS_STATISTIC_DMA_EN_ST
BNX2_HC_VIS_STATISTIC_DMA_EN_ST
BNX2_HC_VIS_STATISTIC_DMA_EN_ST
BNX2_HC_VIS_STATISTIC_DMA_EN_ST
BNX2_HC_VIS_STATISTIC_DMA_EN_ST
BNX2_HC_VIS_STATISTIC_DMA_EN_ST
BNX2_HC_VIS_STATISTIC_DMA_EN_ST
bnx2_init_5706s_phy
bnx2_init_5706s_phy
bnx2_init_5708s_phy
bnx2_init_5708s_phy
bnx2_init_board
bnx2_init_board
bnx2_init_chip
bnx2_init_chip
bnx2_init_context
bnx2_init_context
bnx2_init_copper_phy
bnx2_init_copper_phy
bnx2_init_cpus
bnx2_init_cpus
bnx2_init_nic
bnx2_init_nic
bnx2_init_nvram
bnx2_init_nvram
bnx2_init_phy
bnx2_init_phy
bnx2_init_rx_ring
bnx2_init_rx_ring
bnx2_init_tx_ring
bnx2_init_tx_ring
bnx2_irq
bnx2_irq
BNX2_L2CTX_BD_PRE_READ
BNX2_L2CTX_BD_PRE_READ
BNX2_L2CTX_CMD_TYPE
BNX2_L2CTX_CMD_TYPE
BNX2_L2CTX_CMD_TYPE_TYPE
BNX2_L2CTX_CMD_TYPE_TYPE
BNX2_L2CTX_CMD_TYPE_TYPE_L2
BNX2_L2CTX_CMD_TYPE_TYPE_L2
BNX2_L2CTX_CMD_TYPE_TYPE_TCP
BNX2_L2CTX_CMD_TYPE_TYPE_TCP
BNX2_L2CTX_CTX_SIZE
BNX2_L2CTX_CTX_SIZE
BNX2_L2CTX_CTX_TYPE
BNX2_L2CTX_CTX_TYPE
BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_
BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_
BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_
BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_
BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_
BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_
BNX2_L2CTX_CTX_TYPE_SIZE_L2
BNX2_L2CTX_CTX_TYPE_SIZE_L2
BNX2_L2CTX_EST_NBD
BNX2_L2CTX_EST_NBD
BNX2_L2CTX_HOST_BDIDX
BNX2_L2CTX_HOST_BDIDX
BNX2_L2CTX_HOST_BSEQ
BNX2_L2CTX_HOST_BSEQ
BNX2_L2CTX_NX_BDHADDR_HI
BNX2_L2CTX_NX_BDHADDR_HI
BNX2_L2CTX_NX_BDHADDR_LO
BNX2_L2CTX_NX_BDHADDR_LO
BNX2_L2CTX_NX_BDIDX
BNX2_L2CTX_NX_BDIDX
BNX2_L2CTX_NX_BSEQ
BNX2_L2CTX_NX_BSEQ
BNX2_L2CTX_TBDR_BHADDR_HI
BNX2_L2CTX_TBDR_BHADDR_HI
BNX2_L2CTX_TBDR_BHADDR_LO
BNX2_L2CTX_TBDR_BHADDR_LO
BNX2_L2CTX_TBDR_BIDX
BNX2_L2CTX_TBDR_BIDX
BNX2_L2CTX_TBDR_BOFF
BNX2_L2CTX_TBDR_BOFF
BNX2_L2CTX_TBDR_BSEQ
BNX2_L2CTX_TBDR_BSEQ
BNX2_L2CTX_TSCH_BSEQ
BNX2_L2CTX_TSCH_BSEQ
BNX2_L2CTX_TX_HOST_BIDX
BNX2_L2CTX_TX_HOST_BIDX
BNX2_L2CTX_TX_HOST_BSEQ
BNX2_L2CTX_TX_HOST_BSEQ
BNX2_L2CTX_TXP_BIDX
BNX2_L2CTX_TXP_BIDX
BNX2_L2CTX_TXP_BOFF
BNX2_L2CTX_TXP_BOFF
BNX2_L2CTX_TXP_BSEQ
BNX2_L2CTX_TXP_BSEQ
BNX2_L2CTX_TYPE
BNX2_L2CTX_TYPE
BNX2_L2CTX_TYPE_SIZE_L2
BNX2_L2CTX_TYPE_SIZE_L2
BNX2_L2CTX_TYPE_TYPE
BNX2_L2CTX_TYPE_TYPE
BNX2_L2CTX_TYPE_TYPE_EMPTY
BNX2_L2CTX_TYPE_TYPE_EMPTY
BNX2_L2CTX_TYPE_TYPE_L2
BNX2_L2CTX_TYPE_TYPE_L2
BNX2_LINK_STATUS
BNX2_LINK_STATUS
BNX2_LINK_STATUS_1000FULL
BNX2_LINK_STATUS_1000FULL
BNX2_LINK_STATUS_1000HALF
BNX2_LINK_STATUS_1000HALF
BNX2_LINK_STATUS_100BASE_T4
BNX2_LINK_STATUS_100BASE_T4
BNX2_LINK_STATUS_100FULL
BNX2_LINK_STATUS_100FULL
BNX2_LINK_STATUS_100HALF
BNX2_LINK_STATUS_100HALF
BNX2_LINK_STATUS_10FULL
BNX2_LINK_STATUS_10FULL
BNX2_LINK_STATUS_10HALF
BNX2_LINK_STATUS_10HALF
BNX2_LINK_STATUS_2500FULL
BNX2_LINK_STATUS_2500FULL
BNX2_LINK_STATUS_2500HALF
BNX2_LINK_STATUS_2500HALF
BNX2_LINK_STATUS_AN_COMPLETE
BNX2_LINK_STATUS_AN_COMPLETE
BNX2_LINK_STATUS_AN_ENABLED
BNX2_LINK_STATUS_AN_ENABLED
BNX2_LINK_STATUS_AN_INCOMPLETE
BNX2_LINK_STATUS_AN_INCOMPLETE
BNX2_LINK_STATUS_INIT_VALUE
BNX2_LINK_STATUS_INIT_VALUE
BNX2_LINK_STATUS_LINK_DOWN
BNX2_LINK_STATUS_LINK_DOWN
BNX2_LINK_STATUS_LINK_UP
BNX2_LINK_STATUS_LINK_UP
BNX2_LINK_STATUS_PARALLEL_DET
BNX2_LINK_STATUS_PARALLEL_DET
BNX2_LINK_STATUS_PARTNER_AD_100
BNX2_LINK_STATUS_PARTNER_AD_100
BNX2_LINK_STATUS_PARTNER_AD_100
BNX2_LINK_STATUS_PARTNER_AD_100
BNX2_LINK_STATUS_PARTNER_AD_100
BNX2_LINK_STATUS_PARTNER_AD_100
BNX2_LINK_STATUS_PARTNER_AD_100
BNX2_LINK_STATUS_PARTNER_AD_100
BNX2_LINK_STATUS_PARTNER_AD_100
BNX2_LINK_STATUS_PARTNER_AD_100
BNX2_LINK_STATUS_PARTNER_AD_10F
BNX2_LINK_STATUS_PARTNER_AD_10F
BNX2_LINK_STATUS_PARTNER_AD_10H
BNX2_LINK_STATUS_PARTNER_AD_10H
BNX2_LINK_STATUS_PARTNER_AD_250
BNX2_LINK_STATUS_PARTNER_AD_250
BNX2_LINK_STATUS_PARTNER_AD_250
BNX2_LINK_STATUS_PARTNER_AD_250
BNX2_LINK_STATUS_PARTNER_ASYM_P
BNX2_LINK_STATUS_PARTNER_ASYM_P
BNX2_LINK_STATUS_PARTNER_SYM_PA
BNX2_LINK_STATUS_PARTNER_SYM_PA
BNX2_LINK_STATUS_RESERVED
BNX2_LINK_STATUS_RESERVED
BNX2_LINK_STATUS_RX_FC_ENABLED
BNX2_LINK_STATUS_RX_FC_ENABLED
BNX2_LINK_STATUS_SERDES_LINK
BNX2_LINK_STATUS_SERDES_LINK
BNX2_LINK_STATUS_SPEED_MASK
BNX2_LINK_STATUS_SPEED_MASK
BNX2_LINK_STATUS_TX_FC_ENABLED
BNX2_LINK_STATUS_TX_FC_ENABLED
BNX2_MCP_CPU_DATA_ACCESS
BNX2_MCP_CPU_DATA_ACCESS
BNX2_MCP_CPU_DEBUG_VECT_PEEK
BNX2_MCP_CPU_DEBUG_VECT_PEEK
BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_
BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_
BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_
BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_
BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_
BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_
BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_
BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_
BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_
BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_
BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_
BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_
BNX2_MCP_CPU_EVENT_MASK
BNX2_MCP_CPU_EVENT_MASK
BNX2_MCP_CPU_EVENT_MASK_ALIGN_H
BNX2_MCP_CPU_EVENT_MASK_ALIGN_H
BNX2_MCP_CPU_EVENT_MASK_BAD_DAT
BNX2_MCP_CPU_EVENT_MASK_BAD_DAT
BNX2_MCP_CPU_EVENT_MASK_BAD_INS
BNX2_MCP_CPU_EVENT_MASK_BAD_INS
BNX2_MCP_CPU_EVENT_MASK_BAD_PC_
BNX2_MCP_CPU_EVENT_MASK_BAD_PC_
BNX2_MCP_CPU_EVENT_MASK_BREAKPO
BNX2_MCP_CPU_EVENT_MASK_BREAKPO
BNX2_MCP_CPU_EVENT_MASK_FIO_ABO
BNX2_MCP_CPU_EVENT_MASK_FIO_ABO
BNX2_MCP_CPU_EVENT_MASK_INTERRU
BNX2_MCP_CPU_EVENT_MASK_INTERRU
BNX2_MCP_CPU_EVENT_MASK_PAGE_0_
BNX2_MCP_CPU_EVENT_MASK_PAGE_0_
BNX2_MCP_CPU_EVENT_MASK_PAGE_0_
BNX2_MCP_CPU_EVENT_MASK_PAGE_0_
BNX2_MCP_CPU_EVENT_MASK_SOFT_HA
BNX2_MCP_CPU_EVENT_MASK_SOFT_HA
BNX2_MCP_CPU_EVENT_MASK_SPAD_UN
BNX2_MCP_CPU_EVENT_MASK_SPAD_UN
BNX2_MCP_CPU_HW_BREAKPOINT
BNX2_MCP_CPU_HW_BREAKPOINT
BNX2_MCP_CPU_HW_BREAKPOINT_ADDR
BNX2_MCP_CPU_HW_BREAKPOINT_ADDR
BNX2_MCP_CPU_HW_BREAKPOINT_DISA
BNX2_MCP_CPU_HW_BREAKPOINT_DISA
BNX2_MCP_CPU_INSTRUCTION
BNX2_MCP_CPU_INSTRUCTION
BNX2_MCP_CPU_INTERRUPT_ENABLE
BNX2_MCP_CPU_INTERRUPT_ENABLE
BNX2_MCP_CPU_INTERRUPT_SAVED_PC
BNX2_MCP_CPU_INTERRUPT_SAVED_PC
BNX2_MCP_CPU_INTERRUPT_VECTOR
BNX2_MCP_CPU_INTERRUPT_VECTOR
BNX2_MCP_CPU_LAST_BRANCH_ADDR
BNX2_MCP_CPU_LAST_BRANCH_ADDR
BNX2_MCP_CPU_LAST_BRANCH_ADDR_L
BNX2_MCP_CPU_LAST_BRANCH_ADDR_L
BNX2_MCP_CPU_LAST_BRANCH_ADDR_T
BNX2_MCP_CPU_LAST_BRANCH_ADDR_T
BNX2_MCP_CPU_LAST_BRANCH_ADDR_T
BNX2_MCP_CPU_LAST_BRANCH_ADDR_T
BNX2_MCP_CPU_LAST_BRANCH_ADDR_T
BNX2_MCP_CPU_LAST_BRANCH_ADDR_T
BNX2_MCP_CPU_MODE
BNX2_MCP_CPU_MODE
BNX2_MCP_CPU_MODE_BAD_DATA_HALT
BNX2_MCP_CPU_MODE_BAD_DATA_HALT
BNX2_MCP_CPU_MODE_BAD_INST_HALT
BNX2_MCP_CPU_MODE_BAD_INST_HALT
BNX2_MCP_CPU_MODE_FIO_ABORT_HAL
BNX2_MCP_CPU_MODE_FIO_ABORT_HAL
BNX2_MCP_CPU_MODE_INTERRUPT_ENA
BNX2_MCP_CPU_MODE_INTERRUPT_ENA
BNX2_MCP_CPU_MODE_LOCAL_RST
BNX2_MCP_CPU_MODE_LOCAL_RST
BNX2_MCP_CPU_MODE_MSG_BIT1
BNX2_MCP_CPU_MODE_MSG_BIT1
BNX2_MCP_CPU_MODE_PAGE_0_DATA_E
BNX2_MCP_CPU_MODE_PAGE_0_DATA_E
BNX2_MCP_CPU_MODE_PAGE_0_INST_E
BNX2_MCP_CPU_MODE_PAGE_0_INST_E
BNX2_MCP_CPU_MODE_SOFT_HALT
BNX2_MCP_CPU_MODE_SOFT_HALT
BNX2_MCP_CPU_MODE_SPAD_UNDERFLO
BNX2_MCP_CPU_MODE_SPAD_UNDERFLO
BNX2_MCP_CPU_MODE_STEP_ENA
BNX2_MCP_CPU_MODE_STEP_ENA
BNX2_MCP_CPU_PROGRAM_COUNTER
BNX2_MCP_CPU_PROGRAM_COUNTER
BNX2_MCP_CPU_REG_FILE
BNX2_MCP_CPU_REG_FILE
BNX2_MCP_CPU_STATE
BNX2_MCP_CPU_STATE
BNX2_MCP_CPU_STATE_ALIGN_HALTED
BNX2_MCP_CPU_STATE_ALIGN_HALTED
BNX2_MCP_CPU_STATE_BAD_DATA_ADD
BNX2_MCP_CPU_STATE_BAD_DATA_ADD
BNX2_MCP_CPU_STATE_BAD_INST_HAL
BNX2_MCP_CPU_STATE_BAD_INST_HAL
BNX2_MCP_CPU_STATE_BAD_pc_HALTE
BNX2_MCP_CPU_STATE_BAD_pc_HALTE
BNX2_MCP_CPU_STATE_BLOCKED_READ
BNX2_MCP_CPU_STATE_BLOCKED_READ
BNX2_MCP_CPU_STATE_BREAKPOINT
BNX2_MCP_CPU_STATE_BREAKPOINT
BNX2_MCP_CPU_STATE_DATA_ACCESS_
BNX2_MCP_CPU_STATE_DATA_ACCESS_
BNX2_MCP_CPU_STATE_FIO_ABORT_HA
BNX2_MCP_CPU_STATE_FIO_ABORT_HA
BNX2_MCP_CPU_STATE_INST_FETCH_S
BNX2_MCP_CPU_STATE_INST_FETCH_S
BNX2_MCP_CPU_STATE_INTERRRUPT
BNX2_MCP_CPU_STATE_INTERRRUPT
BNX2_MCP_CPU_STATE_PAGE_0_DATA_
BNX2_MCP_CPU_STATE_PAGE_0_DATA_
BNX2_MCP_CPU_STATE_PAGE_0_INST_
BNX2_MCP_CPU_STATE_PAGE_0_INST_
BNX2_MCP_CPU_STATE_SOFT_HALTED
BNX2_MCP_CPU_STATE_SOFT_HALTED
BNX2_MCP_CPU_STATE_SPAD_UNDERFL
BNX2_MCP_CPU_STATE_SPAD_UNDERFL
BNX2_MCP_MCPQ_FTQ_CMD
BNX2_MCP_MCPQ_FTQ_CMD
BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA
BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA
BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTER
BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTER
BNX2_MCP_MCPQ_FTQ_CMD_BUSY
BNX2_MCP_MCPQ_FTQ_CMD_BUSY
BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE
BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE
BNX2_MCP_MCPQ_FTQ_CMD_OFFSET
BNX2_MCP_MCPQ_FTQ_CMD_OFFSET
BNX2_MCP_MCPQ_FTQ_CMD_POP
BNX2_MCP_MCPQ_FTQ_CMD_POP
BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA
BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA
BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET
BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET
BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP
BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP
BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0
BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0
BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1
BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1
BNX2_MCP_MCPQ_FTQ_CTL
BNX2_MCP_MCPQ_FTQ_CTL
BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH
BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH
BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INT
BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INT
BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE
BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE
BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH
BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH
BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW
BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW
BNX2_MCP_MCPQ_FTQ_DATA
BNX2_MCP_MCPQ_FTQ_DATA
BNX2_MCP_ROM
BNX2_MCP_ROM
BNX2_MCP_SCRATCH
BNX2_MCP_SCRATCH
BNX2_MISC_ARB_FREE0
BNX2_MISC_ARB_FREE0
BNX2_MISC_ARB_FREE1
BNX2_MISC_ARB_FREE1
BNX2_MISC_ARB_FREE2
BNX2_MISC_ARB_FREE2
BNX2_MISC_ARB_FREE3
BNX2_MISC_ARB_FREE3
BNX2_MISC_ARB_FREE4
BNX2_MISC_ARB_FREE4
BNX2_MISC_ARB_GNT0
BNX2_MISC_ARB_GNT0
BNX2_MISC_ARB_GNT0_0
BNX2_MISC_ARB_GNT0_0
BNX2_MISC_ARB_GNT0_1
BNX2_MISC_ARB_GNT0_1
BNX2_MISC_ARB_GNT0_2
BNX2_MISC_ARB_GNT0_2
BNX2_MISC_ARB_GNT0_3
BNX2_MISC_ARB_GNT0_3
BNX2_MISC_ARB_GNT0_4
BNX2_MISC_ARB_GNT0_4
BNX2_MISC_ARB_GNT0_5
BNX2_MISC_ARB_GNT0_5
BNX2_MISC_ARB_GNT0_6
BNX2_MISC_ARB_GNT0_6
BNX2_MISC_ARB_GNT0_7
BNX2_MISC_ARB_GNT0_7
BNX2_MISC_ARB_GNT1
BNX2_MISC_ARB_GNT1
BNX2_MISC_ARB_GNT1_10
BNX2_MISC_ARB_GNT1_10
BNX2_MISC_ARB_GNT1_11
BNX2_MISC_ARB_GNT1_11
BNX2_MISC_ARB_GNT1_12
BNX2_MISC_ARB_GNT1_12
BNX2_MISC_ARB_GNT1_13
BNX2_MISC_ARB_GNT1_13
BNX2_MISC_ARB_GNT1_14
BNX2_MISC_ARB_GNT1_14
BNX2_MISC_ARB_GNT1_15
BNX2_MISC_ARB_GNT1_15
BNX2_MISC_ARB_GNT1_8
BNX2_MISC_ARB_GNT1_8
BNX2_MISC_ARB_GNT1_9
BNX2_MISC_ARB_GNT1_9
BNX2_MISC_ARB_GNT2
BNX2_MISC_ARB_GNT2
BNX2_MISC_ARB_GNT2_16
BNX2_MISC_ARB_GNT2_16
BNX2_MISC_ARB_GNT2_17
BNX2_MISC_ARB_GNT2_17
BNX2_MISC_ARB_GNT2_18
BNX2_MISC_ARB_GNT2_18
BNX2_MISC_ARB_GNT2_19
BNX2_MISC_ARB_GNT2_19
BNX2_MISC_ARB_GNT2_20
BNX2_MISC_ARB_GNT2_20
BNX2_MISC_ARB_GNT2_21
BNX2_MISC_ARB_GNT2_21
BNX2_MISC_ARB_GNT2_22
BNX2_MISC_ARB_GNT2_22
BNX2_MISC_ARB_GNT2_23
BNX2_MISC_ARB_GNT2_23
BNX2_MISC_ARB_GNT3
BNX2_MISC_ARB_GNT3
BNX2_MISC_ARB_GNT3_24
BNX2_MISC_ARB_GNT3_24
BNX2_MISC_ARB_GNT3_25
BNX2_MISC_ARB_GNT3_25
BNX2_MISC_ARB_GNT3_26
BNX2_MISC_ARB_GNT3_26
BNX2_MISC_ARB_GNT3_27
BNX2_MISC_ARB_GNT3_27
BNX2_MISC_ARB_GNT3_28
BNX2_MISC_ARB_GNT3_28
BNX2_MISC_ARB_GNT3_29
BNX2_MISC_ARB_GNT3_29
BNX2_MISC_ARB_GNT3_30
BNX2_MISC_ARB_GNT3_30
BNX2_MISC_ARB_GNT3_31
BNX2_MISC_ARB_GNT3_31
BNX2_MISC_ARB_REQ_STATUS0
BNX2_MISC_ARB_REQ_STATUS0
BNX2_MISC_ARB_REQ_STATUS1
BNX2_MISC_ARB_REQ_STATUS1
BNX2_MISC_ARB_REQ_STATUS2
BNX2_MISC_ARB_REQ_STATUS2
BNX2_MISC_ARB_REQ_STATUS3
BNX2_MISC_ARB_REQ_STATUS3
BNX2_MISC_ARB_REQ_STATUS4
BNX2_MISC_ARB_REQ_STATUS4
BNX2_MISC_ARB_REQ0
BNX2_MISC_ARB_REQ0
BNX2_MISC_ARB_REQ1
BNX2_MISC_ARB_REQ1
BNX2_MISC_ARB_REQ2
BNX2_MISC_ARB_REQ2
BNX2_MISC_ARB_REQ3
BNX2_MISC_ARB_REQ3
BNX2_MISC_ARB_REQ4
BNX2_MISC_ARB_REQ4
BNX2_MISC_CFG
BNX2_MISC_CFG
BNX2_MISC_CFG_BIST_EN
BNX2_MISC_CFG_BIST_EN
BNX2_MISC_CFG_BYPASS_BSCAN
BNX2_MISC_CFG_BYPASS_BSCAN
BNX2_MISC_CFG_BYPASS_EJTAG
BNX2_MISC_CFG_BYPASS_EJTAG
BNX2_MISC_CFG_CK25_OUT_ALT_SRC
BNX2_MISC_CFG_CK25_OUT_ALT_SRC
BNX2_MISC_CFG_CLK_CTL_OVERRIDE
BNX2_MISC_CFG_CLK_CTL_OVERRIDE
BNX2_MISC_CFG_LEDMODE
BNX2_MISC_CFG_LEDMODE
BNX2_MISC_CFG_LEDMODE_GPHY1
BNX2_MISC_CFG_LEDMODE_GPHY1
BNX2_MISC_CFG_LEDMODE_GPHY2
BNX2_MISC_CFG_LEDMODE_GPHY2
BNX2_MISC_CFG_LEDMODE_MAC
BNX2_MISC_CFG_LEDMODE_MAC
BNX2_MISC_CFG_NVM_WR_EN
BNX2_MISC_CFG_NVM_WR_EN
BNX2_MISC_CFG_NVM_WR_EN_ALLOW
BNX2_MISC_CFG_NVM_WR_EN_ALLOW
BNX2_MISC_CFG_NVM_WR_EN_ALLOW2
BNX2_MISC_CFG_NVM_WR_EN_ALLOW2
BNX2_MISC_CFG_NVM_WR_EN_PCI
BNX2_MISC_CFG_NVM_WR_EN_PCI
BNX2_MISC_CFG_NVM_WR_EN_PROTECT
BNX2_MISC_CFG_NVM_WR_EN_PROTECT
BNX2_MISC_CFG_PCI_GRC_TMOUT
BNX2_MISC_CFG_PCI_GRC_TMOUT
BNX2_MISC_CLOCK_CONTROL_BITS
BNX2_MISC_CLOCK_CONTROL_BITS
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_CO
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PC
BNX2_MISC_CLOCK_CONTROL_BITS_PL
BNX2_MISC_CLOCK_CONTROL_BITS_PL
BNX2_MISC_CLOCK_CONTROL_BITS_RE
BNX2_MISC_CLOCK_CONTROL_BITS_RE
BNX2_MISC_CLOCK_CONTROL_BITS_RE
BNX2_MISC_CLOCK_CONTROL_BITS_RE
BNX2_MISC_CLOCK_CONTROL_BITS_US
BNX2_MISC_CLOCK_CONTROL_BITS_US
BNX2_MISC_COMMAND
BNX2_MISC_COMMAND
BNX2_MISC_COMMAND_CORE_RESET
BNX2_MISC_COMMAND_CORE_RESET
BNX2_MISC_COMMAND_DISABLE_ALL
BNX2_MISC_COMMAND_DISABLE_ALL
BNX2_MISC_COMMAND_ENABLE_ALL
BNX2_MISC_COMMAND_ENABLE_ALL
BNX2_MISC_COMMAND_HARD_RESET
BNX2_MISC_COMMAND_HARD_RESET
BNX2_MISC_COMMAND_PAR_ERR_RAM
BNX2_MISC_COMMAND_PAR_ERR_RAM
BNX2_MISC_COMMAND_PAR_ERROR
BNX2_MISC_COMMAND_PAR_ERROR
BNX2_MISC_CONFIG_LFSR
BNX2_MISC_CONFIG_LFSR
BNX2_MISC_CONFIG_LFSR_DIV
BNX2_MISC_CONFIG_LFSR_DIV
BNX2_MISC_DEBUG_VECTOR_SEL
BNX2_MISC_DEBUG_VECTOR_SEL
BNX2_MISC_DEBUG_VECTOR_SEL_0
BNX2_MISC_DEBUG_VECTOR_SEL_0
BNX2_MISC_DEBUG_VECTOR_SEL_1
BNX2_MISC_DEBUG_VECTOR_SEL_1
BNX2_MISC_ENABLE_CLR_BITS
BNX2_MISC_ENABLE_CLR_BITS
BNX2_MISC_ENABLE_CLR_BITS_CMD_P
BNX2_MISC_ENABLE_CLR_BITS_CMD_P
BNX2_MISC_ENABLE_CLR_BITS_CMD_S
BNX2_MISC_ENABLE_CLR_BITS_CMD_S
BNX2_MISC_ENABLE_CLR_BITS_COMPL
BNX2_MISC_ENABLE_CLR_BITS_COMPL
BNX2_MISC_ENABLE_CLR_BITS_CONTE
BNX2_MISC_ENABLE_CLR_BITS_CONTE
BNX2_MISC_ENABLE_CLR_BITS_DMA_E
BNX2_MISC_ENABLE_CLR_BITS_DMA_E
BNX2_MISC_ENABLE_CLR_BITS_EMAC_
BNX2_MISC_ENABLE_CLR_BITS_EMAC_
BNX2_MISC_ENABLE_CLR_BITS_HOST_
BNX2_MISC_ENABLE_CLR_BITS_HOST_
BNX2_MISC_ENABLE_CLR_BITS_MAILB
BNX2_MISC_ENABLE_CLR_BITS_MAILB
BNX2_MISC_ENABLE_CLR_BITS_MGMT_
BNX2_MISC_ENABLE_CLR_BITS_MGMT_
BNX2_MISC_ENABLE_CLR_BITS_RX_BD
BNX2_MISC_ENABLE_CLR_BITS_RX_BD
BNX2_MISC_ENABLE_CLR_BITS_RX_DM
BNX2_MISC_ENABLE_CLR_BITS_RX_DM
BNX2_MISC_ENABLE_CLR_BITS_RX_LO
BNX2_MISC_ENABLE_CLR_BITS_RX_LO
BNX2_MISC_ENABLE_CLR_BITS_RX_MB
BNX2_MISC_ENABLE_CLR_BITS_RX_MB
BNX2_MISC_ENABLE_CLR_BITS_RX_PA
BNX2_MISC_ENABLE_CLR_BITS_RX_PA
BNX2_MISC_ENABLE_CLR_BITS_RX_PA
BNX2_MISC_ENABLE_CLR_BITS_RX_PA
BNX2_MISC_ENABLE_CLR_BITS_RX_PR
BNX2_MISC_ENABLE_CLR_BITS_RX_PR
BNX2_MISC_ENABLE_CLR_BITS_RX_V2
BNX2_MISC_ENABLE_CLR_BITS_RX_V2
BNX2_MISC_ENABLE_CLR_BITS_TIMER
BNX2_MISC_ENABLE_CLR_BITS_TIMER
BNX2_MISC_ENABLE_CLR_BITS_TX_AS
BNX2_MISC_ENABLE_CLR_BITS_TX_AS
BNX2_MISC_ENABLE_CLR_BITS_TX_BD
BNX2_MISC_ENABLE_CLR_BITS_TX_BD
BNX2_MISC_ENABLE_CLR_BITS_TX_BD
BNX2_MISC_ENABLE_CLR_BITS_TX_BD
BNX2_MISC_ENABLE_CLR_BITS_TX_DM
BNX2_MISC_ENABLE_CLR_BITS_TX_DM
BNX2_MISC_ENABLE_CLR_BITS_TX_HE
BNX2_MISC_ENABLE_CLR_BITS_TX_HE
BNX2_MISC_ENABLE_CLR_BITS_TX_PA
BNX2_MISC_ENABLE_CLR_BITS_TX_PA
BNX2_MISC_ENABLE_CLR_BITS_TX_PA
BNX2_MISC_ENABLE_CLR_BITS_TX_PA
BNX2_MISC_ENABLE_CLR_BITS_TX_PR
BNX2_MISC_ENABLE_CLR_BITS_TX_PR
BNX2_MISC_ENABLE_CLR_BITS_TX_SC
BNX2_MISC_ENABLE_CLR_BITS_TX_SC
BNX2_MISC_ENABLE_CLR_BITS_UMP_E
BNX2_MISC_ENABLE_CLR_BITS_UMP_E
BNX2_MISC_ENABLE_SET_BITS
BNX2_MISC_ENABLE_SET_BITS
BNX2_MISC_ENABLE_SET_BITS_CMD_P
BNX2_MISC_ENABLE_SET_BITS_CMD_P
BNX2_MISC_ENABLE_SET_BITS_CMD_S
BNX2_MISC_ENABLE_SET_BITS_CMD_S
BNX2_MISC_ENABLE_SET_BITS_COMPL
BNX2_MISC_ENABLE_SET_BITS_COMPL
BNX2_MISC_ENABLE_SET_BITS_CONTE
BNX2_MISC_ENABLE_SET_BITS_CONTE
BNX2_MISC_ENABLE_SET_BITS_DMA_E
BNX2_MISC_ENABLE_SET_BITS_DMA_E
BNX2_MISC_ENABLE_SET_BITS_EMAC_
BNX2_MISC_ENABLE_SET_BITS_EMAC_
BNX2_MISC_ENABLE_SET_BITS_HOST_
BNX2_MISC_ENABLE_SET_BITS_HOST_
BNX2_MISC_ENABLE_SET_BITS_MAILB
BNX2_MISC_ENABLE_SET_BITS_MAILB
BNX2_MISC_ENABLE_SET_BITS_MGMT_
BNX2_MISC_ENABLE_SET_BITS_MGMT_
BNX2_MISC_ENABLE_SET_BITS_RX_BD
BNX2_MISC_ENABLE_SET_BITS_RX_BD
BNX2_MISC_ENABLE_SET_BITS_RX_DM
BNX2_MISC_ENABLE_SET_BITS_RX_DM
BNX2_MISC_ENABLE_SET_BITS_RX_LO
BNX2_MISC_ENABLE_SET_BITS_RX_LO
BNX2_MISC_ENABLE_SET_BITS_RX_MB
BNX2_MISC_ENABLE_SET_BITS_RX_MB
BNX2_MISC_ENABLE_SET_BITS_RX_PA
BNX2_MISC_ENABLE_SET_BITS_RX_PA
BNX2_MISC_ENABLE_SET_BITS_RX_PA
BNX2_MISC_ENABLE_SET_BITS_RX_PA
BNX2_MISC_ENABLE_SET_BITS_RX_PR
BNX2_MISC_ENABLE_SET_BITS_RX_PR
BNX2_MISC_ENABLE_SET_BITS_RX_V2
BNX2_MISC_ENABLE_SET_BITS_RX_V2
BNX2_MISC_ENABLE_SET_BITS_TIMER
BNX2_MISC_ENABLE_SET_BITS_TIMER
BNX2_MISC_ENABLE_SET_BITS_TX_AS
BNX2_MISC_ENABLE_SET_BITS_TX_AS
BNX2_MISC_ENABLE_SET_BITS_TX_BD
BNX2_MISC_ENABLE_SET_BITS_TX_BD
BNX2_MISC_ENABLE_SET_BITS_TX_BD
BNX2_MISC_ENABLE_SET_BITS_TX_BD
BNX2_MISC_ENABLE_SET_BITS_TX_DM
BNX2_MISC_ENABLE_SET_BITS_TX_DM
BNX2_MISC_ENABLE_SET_BITS_TX_HE
BNX2_MISC_ENABLE_SET_BITS_TX_HE
BNX2_MISC_ENABLE_SET_BITS_TX_PA
BNX2_MISC_ENABLE_SET_BITS_TX_PA
BNX2_MISC_ENABLE_SET_BITS_TX_PA
BNX2_MISC_ENABLE_SET_BITS_TX_PA
BNX2_MISC_ENABLE_SET_BITS_TX_PR
BNX2_MISC_ENABLE_SET_BITS_TX_PR
BNX2_MISC_ENABLE_SET_BITS_TX_SC
BNX2_MISC_ENABLE_SET_BITS_TX_SC
BNX2_MISC_ENABLE_SET_BITS_UMP_E
BNX2_MISC_ENABLE_SET_BITS_UMP_E
BNX2_MISC_ENABLE_STATUS_BITS
BNX2_MISC_ENABLE_STATUS_BITS
BNX2_MISC_ENABLE_STATUS_BITS_CM
BNX2_MISC_ENABLE_STATUS_BITS_CM
BNX2_MISC_ENABLE_STATUS_BITS_CM
BNX2_MISC_ENABLE_STATUS_BITS_CM
BNX2_MISC_ENABLE_STATUS_BITS_CO
BNX2_MISC_ENABLE_STATUS_BITS_CO
BNX2_MISC_ENABLE_STATUS_BITS_CO
BNX2_MISC_ENABLE_STATUS_BITS_CO
BNX2_MISC_ENABLE_STATUS_BITS_DM
BNX2_MISC_ENABLE_STATUS_BITS_DM
BNX2_MISC_ENABLE_STATUS_BITS_EM
BNX2_MISC_ENABLE_STATUS_BITS_EM
BNX2_MISC_ENABLE_STATUS_BITS_HO
BNX2_MISC_ENABLE_STATUS_BITS_HO
BNX2_MISC_ENABLE_STATUS_BITS_MA
BNX2_MISC_ENABLE_STATUS_BITS_MA
BNX2_MISC_ENABLE_STATUS_BITS_MG
BNX2_MISC_ENABLE_STATUS_BITS_MG
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_RX
BNX2_MISC_ENABLE_STATUS_BITS_TI
BNX2_MISC_ENABLE_STATUS_BITS_TI
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_TX
BNX2_MISC_ENABLE_STATUS_BITS_UM
BNX2_MISC_ENABLE_STATUS_BITS_UM
BNX2_MISC_FINAL_CLK_CTL_VAL
BNX2_MISC_FINAL_CLK_CTL_VAL
BNX2_MISC_FINAL_CLK_CTL_VAL_MIS
BNX2_MISC_FINAL_CLK_CTL_VAL_MIS
BNX2_MISC_GPIO
BNX2_MISC_GPIO
BNX2_MISC_GPIO_CLR
BNX2_MISC_GPIO_CLR
BNX2_MISC_GPIO_FLOAT
BNX2_MISC_GPIO_FLOAT
BNX2_MISC_GPIO_INT
BNX2_MISC_GPIO_INT
BNX2_MISC_GPIO_INT_INT_STATE
BNX2_MISC_GPIO_INT_INT_STATE
BNX2_MISC_GPIO_INT_OLD_CLR
BNX2_MISC_GPIO_INT_OLD_CLR
BNX2_MISC_GPIO_INT_OLD_SET
BNX2_MISC_GPIO_INT_OLD_SET
BNX2_MISC_GPIO_INT_OLD_VALUE
BNX2_MISC_GPIO_INT_OLD_VALUE
BNX2_MISC_GPIO_SET
BNX2_MISC_GPIO_SET
BNX2_MISC_GPIO_VALUE
BNX2_MISC_GPIO_VALUE
BNX2_MISC_ID
BNX2_MISC_ID
BNX2_MISC_ID_BOND_ID
BNX2_MISC_ID_BOND_ID
BNX2_MISC_ID_CHIP_METAL
BNX2_MISC_ID_CHIP_METAL
BNX2_MISC_ID_CHIP_NUM
BNX2_MISC_ID_CHIP_NUM
BNX2_MISC_ID_CHIP_REV
BNX2_MISC_ID_CHIP_REV
BNX2_MISC_LFSR_MASK_BITS
BNX2_MISC_LFSR_MASK_BITS
BNX2_MISC_LFSR_MASK_BITS_CMD_PR
BNX2_MISC_LFSR_MASK_BITS_CMD_PR
BNX2_MISC_LFSR_MASK_BITS_CMD_SC
BNX2_MISC_LFSR_MASK_BITS_CMD_SC
BNX2_MISC_LFSR_MASK_BITS_COMPLE
BNX2_MISC_LFSR_MASK_BITS_COMPLE
BNX2_MISC_LFSR_MASK_BITS_CONTEX
BNX2_MISC_LFSR_MASK_BITS_CONTEX
BNX2_MISC_LFSR_MASK_BITS_DMA_EN
BNX2_MISC_LFSR_MASK_BITS_DMA_EN
BNX2_MISC_LFSR_MASK_BITS_EMAC_E
BNX2_MISC_LFSR_MASK_BITS_EMAC_E
BNX2_MISC_LFSR_MASK_BITS_HOST_C
BNX2_MISC_LFSR_MASK_BITS_HOST_C
BNX2_MISC_LFSR_MASK_BITS_MAILBO
BNX2_MISC_LFSR_MASK_BITS_MAILBO
BNX2_MISC_LFSR_MASK_BITS_MGMT_P
BNX2_MISC_LFSR_MASK_BITS_MGMT_P
BNX2_MISC_LFSR_MASK_BITS_RX_BD_
BNX2_MISC_LFSR_MASK_BITS_RX_BD_
BNX2_MISC_LFSR_MASK_BITS_RX_DMA
BNX2_MISC_LFSR_MASK_BITS_RX_DMA
BNX2_MISC_LFSR_MASK_BITS_RX_LOO
BNX2_MISC_LFSR_MASK_BITS_RX_LOO
BNX2_MISC_LFSR_MASK_BITS_RX_MBU
BNX2_MISC_LFSR_MASK_BITS_RX_MBU
BNX2_MISC_LFSR_MASK_BITS_RX_PAR
BNX2_MISC_LFSR_MASK_BITS_RX_PAR
BNX2_MISC_LFSR_MASK_BITS_RX_PAR
BNX2_MISC_LFSR_MASK_BITS_RX_PAR
BNX2_MISC_LFSR_MASK_BITS_RX_PRO
BNX2_MISC_LFSR_MASK_BITS_RX_PRO
BNX2_MISC_LFSR_MASK_BITS_RX_V2P
BNX2_MISC_LFSR_MASK_BITS_RX_V2P
BNX2_MISC_LFSR_MASK_BITS_TIMER_
BNX2_MISC_LFSR_MASK_BITS_TIMER_
BNX2_MISC_LFSR_MASK_BITS_TX_ASS
BNX2_MISC_LFSR_MASK_BITS_TX_ASS
BNX2_MISC_LFSR_MASK_BITS_TX_BD_
BNX2_MISC_LFSR_MASK_BITS_TX_BD_
BNX2_MISC_LFSR_MASK_BITS_TX_BD_
BNX2_MISC_LFSR_MASK_BITS_TX_BD_
BNX2_MISC_LFSR_MASK_BITS_TX_DMA
BNX2_MISC_LFSR_MASK_BITS_TX_DMA
BNX2_MISC_LFSR_MASK_BITS_TX_HEA
BNX2_MISC_LFSR_MASK_BITS_TX_HEA
BNX2_MISC_LFSR_MASK_BITS_TX_PAT
BNX2_MISC_LFSR_MASK_BITS_TX_PAT
BNX2_MISC_LFSR_MASK_BITS_TX_PAY
BNX2_MISC_LFSR_MASK_BITS_TX_PAY
BNX2_MISC_LFSR_MASK_BITS_TX_PRO
BNX2_MISC_LFSR_MASK_BITS_TX_PRO
BNX2_MISC_LFSR_MASK_BITS_TX_SCH
BNX2_MISC_LFSR_MASK_BITS_TX_SCH
BNX2_MISC_LFSR_MASK_BITS_UMP_EN
BNX2_MISC_LFSR_MASK_BITS_UMP_EN
BNX2_MISC_PERR_ENA0
BNX2_MISC_PERR_ENA0
BNX2_MISC_PERR_ENA0_COM_MISC_CT
BNX2_MISC_PERR_ENA0_COM_MISC_CT
BNX2_MISC_PERR_ENA0_COM_MISC_RE
BNX2_MISC_PERR_ENA0_COM_MISC_RE
BNX2_MISC_PERR_ENA0_COM_MISC_SC
BNX2_MISC_PERR_ENA0_COM_MISC_SC
BNX2_MISC_PERR_ENA0_CP_MISC_CTX
BNX2_MISC_PERR_ENA0_CP_MISC_CTX
BNX2_MISC_PERR_ENA0_CP_MISC_REG
BNX2_MISC_PERR_ENA0_CP_MISC_REG
BNX2_MISC_PERR_ENA0_CP_MISC_SCP
BNX2_MISC_PERR_ENA0_CP_MISC_SCP
BNX2_MISC_PERR_ENA0_CS_MISC_TME
BNX2_MISC_PERR_ENA0_CS_MISC_TME
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_AC
BNX2_MISC_PERR_ENA0_CTX_MISC_PG
BNX2_MISC_PERR_ENA0_CTX_MISC_PG
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_DMAE_MISC_D
BNX2_MISC_PERR_ENA0_HC_MISC_DMA
BNX2_MISC_PERR_ENA0_HC_MISC_DMA
BNX2_MISC_PERR_ENA0_MCP_MISC_RE
BNX2_MISC_PERR_ENA0_MCP_MISC_RE
BNX2_MISC_PERR_ENA0_MCP_MISC_SC
BNX2_MISC_PERR_ENA0_MCP_MISC_SC
BNX2_MISC_PERR_ENA0_MQ_MISC_CTX
BNX2_MISC_PERR_ENA0_MQ_MISC_CTX
BNX2_MISC_PERR_ENA0_RBDC_MISC
BNX2_MISC_PERR_ENA0_RBDC_MISC
BNX2_MISC_PERR_ENA0_RBUF_MISC_M
BNX2_MISC_PERR_ENA0_RBUF_MISC_M
BNX2_MISC_PERR_ENA0_RBUF_MISC_P
BNX2_MISC_PERR_ENA0_RBUF_MISC_P
BNX2_MISC_PERR_ENA0_RDE_MISC_RP
BNX2_MISC_PERR_ENA0_RDE_MISC_RP
BNX2_MISC_PERR_ENA0_RDE_MISC_RP
BNX2_MISC_PERR_ENA0_RDE_MISC_RP
BNX2_MISC_PERR_ENA0_RV2P_MISC_C
BNX2_MISC_PERR_ENA0_RV2P_MISC_C
BNX2_MISC_PERR_ENA1
BNX2_MISC_PERR_ENA1
BNX2_MISC_PERR_ENA1_CPQ_MISC
BNX2_MISC_PERR_ENA1_CPQ_MISC
BNX2_MISC_PERR_ENA1_CSQ_MISC
BNX2_MISC_PERR_ENA1_CSQ_MISC
BNX2_MISC_PERR_ENA1_MCPQ_MISC
BNX2_MISC_PERR_ENA1_MCPQ_MISC
BNX2_MISC_PERR_ENA1_RDMAQ_MISC
BNX2_MISC_PERR_ENA1_RDMAQ_MISC
BNX2_MISC_PERR_ENA1_RLUPQ_MISC
BNX2_MISC_PERR_ENA1_RLUPQ_MISC
BNX2_MISC_PERR_ENA1_RV2P_MISC_C
BNX2_MISC_PERR_ENA1_RV2P_MISC_C
BNX2_MISC_PERR_ENA1_RV2P_MISC_P
BNX2_MISC_PERR_ENA1_RV2P_MISC_P
BNX2_MISC_PERR_ENA1_RV2P_MISC_P
BNX2_MISC_PERR_ENA1_RV2P_MISC_P
BNX2_MISC_PERR_ENA1_RV2PMQ_MISC
BNX2_MISC_PERR_ENA1_RV2PMQ_MISC
BNX2_MISC_PERR_ENA1_RV2PPQ_MISC
BNX2_MISC_PERR_ENA1_RV2PPQ_MISC
BNX2_MISC_PERR_ENA1_RV2PTQ_MISC
BNX2_MISC_PERR_ENA1_RV2PTQ_MISC
BNX2_MISC_PERR_ENA1_RXP_MISC_CT
BNX2_MISC_PERR_ENA1_RXP_MISC_CT
BNX2_MISC_PERR_ENA1_RXP_MISC_RB
BNX2_MISC_PERR_ENA1_RXP_MISC_RB
BNX2_MISC_PERR_ENA1_RXP_MISC_RE
BNX2_MISC_PERR_ENA1_RXP_MISC_RE
BNX2_MISC_PERR_ENA1_RXP_MISC_SC
BNX2_MISC_PERR_ENA1_RXP_MISC_SC
BNX2_MISC_PERR_ENA1_RXPCQ_MISC
BNX2_MISC_PERR_ENA1_RXPCQ_MISC
BNX2_MISC_PERR_ENA1_RXPQ_MISC
BNX2_MISC_PERR_ENA1_RXPQ_MISC
BNX2_MISC_PERR_ENA1_TBDC_MISC
BNX2_MISC_PERR_ENA1_TBDC_MISC
BNX2_MISC_PERR_ENA1_TDMA_MISC
BNX2_MISC_PERR_ENA1_TDMA_MISC
BNX2_MISC_PERR_ENA1_THBUF_MISC_
BNX2_MISC_PERR_ENA1_THBUF_MISC_
BNX2_MISC_PERR_ENA1_THBUF_MISC_
BNX2_MISC_PERR_ENA1_THBUF_MISC_
BNX2_MISC_PERR_ENA1_TPAT_MISC_R
BNX2_MISC_PERR_ENA1_TPAT_MISC_R
BNX2_MISC_PERR_ENA1_TPAT_MISC_S
BNX2_MISC_PERR_ENA1_TPAT_MISC_S
BNX2_MISC_PERR_ENA1_TPBUF_MISC_
BNX2_MISC_PERR_ENA1_TPBUF_MISC_
BNX2_MISC_PERR_ENA1_TSCH_MISC_L
BNX2_MISC_PERR_ENA1_TSCH_MISC_L
BNX2_MISC_PERR_ENA1_TXP_MISC_CT
BNX2_MISC_PERR_ENA1_TXP_MISC_CT
BNX2_MISC_PERR_ENA1_TXP_MISC_RE
BNX2_MISC_PERR_ENA1_TXP_MISC_RE
BNX2_MISC_PERR_ENA1_TXP_MISC_SC
BNX2_MISC_PERR_ENA1_TXP_MISC_SC
BNX2_MISC_PERR_ENA1_UMP_MISC_FI
BNX2_MISC_PERR_ENA1_UMP_MISC_FI
BNX2_MISC_PERR_ENA1_UMP_MISC_FI
BNX2_MISC_PERR_ENA1_UMP_MISC_FI
BNX2_MISC_PERR_ENA1_UMP_MISC_RX
BNX2_MISC_PERR_ENA1_UMP_MISC_RX
BNX2_MISC_PERR_ENA1_UMP_MISC_TX
BNX2_MISC_PERR_ENA1_UMP_MISC_TX
BNX2_MISC_PERR_ENA2
BNX2_MISC_PERR_ENA2
BNX2_MISC_PERR_ENA2_COMQ_MISC
BNX2_MISC_PERR_ENA2_COMQ_MISC
BNX2_MISC_PERR_ENA2_COMTQ_MISC
BNX2_MISC_PERR_ENA2_COMTQ_MISC
BNX2_MISC_PERR_ENA2_COMXQ_MISC
BNX2_MISC_PERR_ENA2_COMXQ_MISC
BNX2_MISC_PERR_ENA2_TASQ_MISC
BNX2_MISC_PERR_ENA2_TASQ_MISC
BNX2_MISC_PERR_ENA2_TBDRQ_MISC
BNX2_MISC_PERR_ENA2_TBDRQ_MISC
BNX2_MISC_PERR_ENA2_TDMAQ_MISC
BNX2_MISC_PERR_ENA2_TDMAQ_MISC
BNX2_MISC_PERR_ENA2_TPATQ_MISC
BNX2_MISC_PERR_ENA2_TPATQ_MISC
BNX2_MISC_PERR_ENA2_TSCHQ_MISC
BNX2_MISC_PERR_ENA2_TSCHQ_MISC
BNX2_MISC_PERR_ENA2_TXPQ_MISC
BNX2_MISC_PERR_ENA2_TXPQ_MISC
BNX2_MISC_PRBS_CONTROL
BNX2_MISC_PRBS_CONTROL
BNX2_MISC_PRBS_CONTROL_EN
BNX2_MISC_PRBS_CONTROL_EN
BNX2_MISC_PRBS_CONTROL_ERR_CLR
BNX2_MISC_PRBS_CONTROL_ERR_CLR
BNX2_MISC_PRBS_CONTROL_INV
BNX2_MISC_PRBS_CONTROL_INV
BNX2_MISC_PRBS_CONTROL_ORDER
BNX2_MISC_PRBS_CONTROL_ORDER
BNX2_MISC_PRBS_CONTROL_ORDER_15
BNX2_MISC_PRBS_CONTROL_ORDER_15
BNX2_MISC_PRBS_CONTROL_ORDER_23
BNX2_MISC_PRBS_CONTROL_ORDER_23
BNX2_MISC_PRBS_CONTROL_ORDER_31
BNX2_MISC_PRBS_CONTROL_ORDER_31
BNX2_MISC_PRBS_CONTROL_ORDER_7T
BNX2_MISC_PRBS_CONTROL_ORDER_7T
BNX2_MISC_PRBS_CONTROL_RSTB
BNX2_MISC_PRBS_CONTROL_RSTB
BNX2_MISC_PRBS_STATUS
BNX2_MISC_PRBS_STATUS
BNX2_MISC_PRBS_STATUS_ERRORS
BNX2_MISC_PRBS_STATUS_ERRORS
BNX2_MISC_PRBS_STATUS_LOCK
BNX2_MISC_PRBS_STATUS_LOCK
BNX2_MISC_PRBS_STATUS_STATE
BNX2_MISC_PRBS_STATUS_STATE
BNX2_MISC_PRBS_STATUS_STKY
BNX2_MISC_PRBS_STATUS_STKY
BNX2_MISC_SM_ASF_CONTROL
BNX2_MISC_SM_ASF_CONTROL
BNX2_MISC_SM_ASF_CONTROL_ASF_RS
BNX2_MISC_SM_ASF_CONTROL_ASF_RS
BNX2_MISC_SM_ASF_CONTROL_EN_NIC
BNX2_MISC_SM_ASF_CONTROL_EN_NIC
BNX2_MISC_SM_ASF_CONTROL_HB_TO
BNX2_MISC_SM_ASF_CONTROL_HB_TO
BNX2_MISC_SM_ASF_CONTROL_NIC_SM
BNX2_MISC_SM_ASF_CONTROL_NIC_SM
BNX2_MISC_SM_ASF_CONTROL_NIC_SM
BNX2_MISC_SM_ASF_CONTROL_NIC_SM
BNX2_MISC_SM_ASF_CONTROL_PA_TO
BNX2_MISC_SM_ASF_CONTROL_PA_TO
BNX2_MISC_SM_ASF_CONTROL_PL_TO
BNX2_MISC_SM_ASF_CONTROL_PL_TO
BNX2_MISC_SM_ASF_CONTROL_RES
BNX2_MISC_SM_ASF_CONTROL_RES
BNX2_MISC_SM_ASF_CONTROL_RT_TO
BNX2_MISC_SM_ASF_CONTROL_RT_TO
BNX2_MISC_SM_ASF_CONTROL_SMB_AU
BNX2_MISC_SM_ASF_CONTROL_SMB_AU
BNX2_MISC_SM_ASF_CONTROL_SMB_BB
BNX2_MISC_SM_ASF_CONTROL_SMB_BB
BNX2_MISC_SM_ASF_CONTROL_SMB_EA
BNX2_MISC_SM_ASF_CONTROL_SMB_EA
BNX2_MISC_SM_ASF_CONTROL_SMB_EN
BNX2_MISC_SM_ASF_CONTROL_SMB_EN
BNX2_MISC_SM_ASF_CONTROL_SMB_EV
BNX2_MISC_SM_ASF_CONTROL_SMB_EV
BNX2_MISC_SM_ASF_CONTROL_SMB_NO
BNX2_MISC_SM_ASF_CONTROL_SMB_NO
BNX2_MISC_SM_ASF_CONTROL_TSC_EN
BNX2_MISC_SM_ASF_CONTROL_TSC_EN
BNX2_MISC_SM_ASF_CONTROL_WG_TO
BNX2_MISC_SM_ASF_CONTROL_WG_TO
BNX2_MISC_SMB_HEARTBEAT
BNX2_MISC_SMB_HEARTBEAT
BNX2_MISC_SMB_HEARTBEAT_HEARTBE
BNX2_MISC_SMB_HEARTBEAT_HEARTBE
BNX2_MISC_SMB_IN
BNX2_MISC_SMB_IN
BNX2_MISC_SMB_IN_DAT_IN
BNX2_MISC_SMB_IN_DAT_IN
BNX2_MISC_SMB_IN_DONE
BNX2_MISC_SMB_IN_DONE
BNX2_MISC_SMB_IN_FIRSTBYTE
BNX2_MISC_SMB_IN_FIRSTBYTE
BNX2_MISC_SMB_IN_RDY
BNX2_MISC_SMB_IN_RDY
BNX2_MISC_SMB_IN_STATUS
BNX2_MISC_SMB_IN_STATUS
BNX2_MISC_SMB_IN_STATUS_OFLOW
BNX2_MISC_SMB_IN_STATUS_OFLOW
BNX2_MISC_SMB_IN_STATUS_OK
BNX2_MISC_SMB_IN_STATUS_OK
BNX2_MISC_SMB_IN_STATUS_PEC
BNX2_MISC_SMB_IN_STATUS_PEC
BNX2_MISC_SMB_IN_STATUS_STOP
BNX2_MISC_SMB_IN_STATUS_STOP
BNX2_MISC_SMB_IN_STATUS_TIMEOUT
BNX2_MISC_SMB_IN_STATUS_TIMEOUT
BNX2_MISC_SMB_OUT
BNX2_MISC_SMB_OUT
BNX2_MISC_SMB_OUT_ACC_TYPE
BNX2_MISC_SMB_OUT_ACC_TYPE
BNX2_MISC_SMB_OUT_DAT_OUT
BNX2_MISC_SMB_OUT_DAT_OUT
BNX2_MISC_SMB_OUT_ENB_PEC
BNX2_MISC_SMB_OUT_ENB_PEC
BNX2_MISC_SMB_OUT_GET_RX_LEN
BNX2_MISC_SMB_OUT_GET_RX_LEN
BNX2_MISC_SMB_OUT_LAST
BNX2_MISC_SMB_OUT_LAST
BNX2_MISC_SMB_OUT_RDY
BNX2_MISC_SMB_OUT_RDY
BNX2_MISC_SMB_OUT_SMB_OUT_CLK_E
BNX2_MISC_SMB_OUT_SMB_OUT_CLK_E
BNX2_MISC_SMB_OUT_SMB_OUT_CLK_I
BNX2_MISC_SMB_OUT_SMB_OUT_CLK_I
BNX2_MISC_SMB_OUT_SMB_OUT_DAT_E
BNX2_MISC_SMB_OUT_SMB_OUT_DAT_E
BNX2_MISC_SMB_OUT_SMB_OUT_DAT_I
BNX2_MISC_SMB_OUT_SMB_OUT_DAT_I
BNX2_MISC_SMB_OUT_SMB_OUT_SLAVE
BNX2_MISC_SMB_OUT_SMB_OUT_SLAVE
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_OUT_STATU
BNX2_MISC_SMB_OUT_SMB_READ_LEN
BNX2_MISC_SMB_OUT_SMB_READ_LEN
BNX2_MISC_SMB_OUT_START
BNX2_MISC_SMB_OUT_START
BNX2_MISC_SMB_POLL_ASF
BNX2_MISC_SMB_POLL_ASF
BNX2_MISC_SMB_POLL_ASF_POLL_ASF
BNX2_MISC_SMB_POLL_ASF_POLL_ASF
BNX2_MISC_SMB_POLL_LEGACY
BNX2_MISC_SMB_POLL_LEGACY
BNX2_MISC_SMB_POLL_LEGACY_POLL_
BNX2_MISC_SMB_POLL_LEGACY_POLL_
BNX2_MISC_SMB_RETRAN
BNX2_MISC_SMB_RETRAN
BNX2_MISC_SMB_RETRAN_RETRAN
BNX2_MISC_SMB_RETRAN_RETRAN
BNX2_MISC_SMB_TIMESTAMP
BNX2_MISC_SMB_TIMESTAMP
BNX2_MISC_SMB_TIMESTAMP_TIMESTA
BNX2_MISC_SMB_TIMESTAMP_TIMESTA
BNX2_MISC_SMB_WATCHDOG
BNX2_MISC_SMB_WATCHDOG
BNX2_MISC_SMB_WATCHDOG_WATCHDOG
BNX2_MISC_SMB_WATCHDOG_WATCHDOG
BNX2_MISC_UNUSED0
BNX2_MISC_UNUSED0
BNX2_MISC_VREG_CONTROL
BNX2_MISC_VREG_CONTROL
BNX2_MISC_VREG_CONTROL_1_2
BNX2_MISC_VREG_CONTROL_1_2
BNX2_MISC_VREG_CONTROL_2_5
BNX2_MISC_VREG_CONTROL_2_5
BNX2_MQ_BAD_RD_ADDR
BNX2_MQ_BAD_RD_ADDR
BNX2_MQ_BAD_WR_ADDR
BNX2_MQ_BAD_WR_ADDR
BNX2_MQ_COMMAND
BNX2_MQ_COMMAND
BNX2_MQ_COMMAND_ENABLED
BNX2_MQ_COMMAND_ENABLED
BNX2_MQ_COMMAND_OVERFLOW
BNX2_MQ_COMMAND_OVERFLOW
BNX2_MQ_COMMAND_RD_ERROR
BNX2_MQ_COMMAND_RD_ERROR
BNX2_MQ_COMMAND_WR_ERROR
BNX2_MQ_COMMAND_WR_ERROR
BNX2_MQ_CONFIG
BNX2_MQ_CONFIG
BNX2_MQ_CONFIG_CUR_DEPTH
BNX2_MQ_CONFIG_CUR_DEPTH
BNX2_MQ_CONFIG_HALT_DIS
BNX2_MQ_CONFIG_HALT_DIS
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
BNX2_MQ_CONFIG_MAX_DEPTH
BNX2_MQ_CONFIG_MAX_DEPTH
BNX2_MQ_CONFIG_TX_HIGH_PRI
BNX2_MQ_CONFIG_TX_HIGH_PRI
BNX2_MQ_ENQUEUE1
BNX2_MQ_ENQUEUE1
BNX2_MQ_ENQUEUE1_BYTE_MASK
BNX2_MQ_ENQUEUE1_BYTE_MASK
BNX2_MQ_ENQUEUE1_CID
BNX2_MQ_ENQUEUE1_CID
BNX2_MQ_ENQUEUE1_KNL_MODE
BNX2_MQ_ENQUEUE1_KNL_MODE
BNX2_MQ_ENQUEUE1_OFFSET
BNX2_MQ_ENQUEUE1_OFFSET
BNX2_MQ_ENQUEUE2
BNX2_MQ_ENQUEUE2
BNX2_MQ_KNL_BYP_CMD_MASK1
BNX2_MQ_KNL_BYP_CMD_MASK1
BNX2_MQ_KNL_BYP_CMD_MASK2
BNX2_MQ_KNL_BYP_CMD_MASK2
BNX2_MQ_KNL_BYP_COND_ENQUEUE_MA
BNX2_MQ_KNL_BYP_COND_ENQUEUE_MA
BNX2_MQ_KNL_BYP_COND_ENQUEUE_MA
BNX2_MQ_KNL_BYP_COND_ENQUEUE_MA
BNX2_MQ_KNL_BYP_RX_V2P_MASK1
BNX2_MQ_KNL_BYP_RX_V2P_MASK1
BNX2_MQ_KNL_BYP_RX_V2P_MASK2
BNX2_MQ_KNL_BYP_RX_V2P_MASK2
BNX2_MQ_KNL_BYP_TX_MASK1
BNX2_MQ_KNL_BYP_TX_MASK1
BNX2_MQ_KNL_BYP_TX_MASK2
BNX2_MQ_KNL_BYP_TX_MASK2
BNX2_MQ_KNL_BYP_WIND_START
BNX2_MQ_KNL_BYP_WIND_START
BNX2_MQ_KNL_BYP_WIND_START_VALU
BNX2_MQ_KNL_BYP_WIND_START_VALU
BNX2_MQ_KNL_BYP_WRITE_MASK1
BNX2_MQ_KNL_BYP_WRITE_MASK1
BNX2_MQ_KNL_BYP_WRITE_MASK2
BNX2_MQ_KNL_BYP_WRITE_MASK2
BNX2_MQ_KNL_CMD_MASK1
BNX2_MQ_KNL_CMD_MASK1
BNX2_MQ_KNL_CMD_MASK2
BNX2_MQ_KNL_CMD_MASK2
BNX2_MQ_KNL_COND_ENQUEUE_MASK1
BNX2_MQ_KNL_COND_ENQUEUE_MASK1
BNX2_MQ_KNL_COND_ENQUEUE_MASK2
BNX2_MQ_KNL_COND_ENQUEUE_MASK2
BNX2_MQ_KNL_RX_V2P_MASK1
BNX2_MQ_KNL_RX_V2P_MASK1
BNX2_MQ_KNL_RX_V2P_MASK2
BNX2_MQ_KNL_RX_V2P_MASK2
BNX2_MQ_KNL_TX_MASK1
BNX2_MQ_KNL_TX_MASK1
BNX2_MQ_KNL_TX_MASK2
BNX2_MQ_KNL_TX_MASK2
BNX2_MQ_KNL_WIND_END
BNX2_MQ_KNL_WIND_END
BNX2_MQ_KNL_WIND_END_VALUE
BNX2_MQ_KNL_WIND_END_VALUE
BNX2_MQ_KNL_WRITE_MASK1
BNX2_MQ_KNL_WRITE_MASK1
BNX2_MQ_KNL_WRITE_MASK2
BNX2_MQ_KNL_WRITE_MASK2
BNX2_MQ_MEM_RD_ADDR
BNX2_MQ_MEM_RD_ADDR
BNX2_MQ_MEM_RD_ADDR_VALUE
BNX2_MQ_MEM_RD_ADDR_VALUE
BNX2_MQ_MEM_RD_DATA0
BNX2_MQ_MEM_RD_DATA0
BNX2_MQ_MEM_RD_DATA0_VALUE
BNX2_MQ_MEM_RD_DATA0_VALUE
BNX2_MQ_MEM_RD_DATA1
BNX2_MQ_MEM_RD_DATA1
BNX2_MQ_MEM_RD_DATA1_VALUE
BNX2_MQ_MEM_RD_DATA1_VALUE
BNX2_MQ_MEM_RD_DATA2
BNX2_MQ_MEM_RD_DATA2
BNX2_MQ_MEM_RD_DATA2_VALUE
BNX2_MQ_MEM_RD_DATA2_VALUE
BNX2_MQ_MEM_WR_ADDR
BNX2_MQ_MEM_WR_ADDR
BNX2_MQ_MEM_WR_ADDR_VALUE
BNX2_MQ_MEM_WR_ADDR_VALUE
BNX2_MQ_MEM_WR_DATA0
BNX2_MQ_MEM_WR_DATA0
BNX2_MQ_MEM_WR_DATA0_VALUE
BNX2_MQ_MEM_WR_DATA0_VALUE
BNX2_MQ_MEM_WR_DATA1
BNX2_MQ_MEM_WR_DATA1
BNX2_MQ_MEM_WR_DATA1_VALUE
BNX2_MQ_MEM_WR_DATA1_VALUE
BNX2_MQ_MEM_WR_DATA2
BNX2_MQ_MEM_WR_DATA2
BNX2_MQ_MEM_WR_DATA2_VALUE
BNX2_MQ_MEM_WR_DATA2_VALUE
BNX2_MQ_STATUS
BNX2_MQ_STATUS
BNX2_MQ_STATUS_CTX_ACCESS_STAT
BNX2_MQ_STATUS_CTX_ACCESS_STAT
BNX2_MQ_STATUS_CTX_ACCESS64_STA
BNX2_MQ_STATUS_CTX_ACCESS64_STA
BNX2_MQ_STATUS_PCI_STALL_STAT
BNX2_MQ_STATUS_PCI_STALL_STAT
BNX2_NVM_ACCESS_ENABLE
BNX2_NVM_ACCESS_ENABLE
BNX2_NVM_ACCESS_ENABLE_EN
BNX2_NVM_ACCESS_ENABLE_EN
BNX2_NVM_ACCESS_ENABLE_WR_EN
BNX2_NVM_ACCESS_ENABLE_WR_EN
BNX2_NVM_ADDR
BNX2_NVM_ADDR
BNX2_NVM_ADDR_NVM_ADDR_VALUE
BNX2_NVM_ADDR_NVM_ADDR_VALUE
BNX2_NVM_ADDR_NVM_ADDR_VALUE_BI
BNX2_NVM_ADDR_NVM_ADDR_VALUE_BI
BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS
BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS
BNX2_NVM_ADDR_NVM_ADDR_VALUE_EE
BNX2_NVM_ADDR_NVM_ADDR_VALUE_EE
BNX2_NVM_ADDR_NVM_ADDR_VALUE_EE
BNX2_NVM_ADDR_NVM_ADDR_VALUE_EE
BNX2_NVM_ADDR_NVM_ADDR_VALUE_SC
BNX2_NVM_ADDR_NVM_ADDR_VALUE_SC
BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI
BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI
BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO
BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO
BNX2_NVM_CFG1
BNX2_NVM_CFG1
BNX2_NVM_CFG1_BITBANG_MODE
BNX2_NVM_CFG1_BITBANG_MODE
BNX2_NVM_CFG1_BUFFER_MODE
BNX2_NVM_CFG1_BUFFER_MODE
BNX2_NVM_CFG1_COMPAT_BYPASSS
BNX2_NVM_CFG1_COMPAT_BYPASSS
BNX2_NVM_CFG1_FLASH_MODE
BNX2_NVM_CFG1_FLASH_MODE
BNX2_NVM_CFG1_FLASH_SIZE
BNX2_NVM_CFG1_FLASH_SIZE
BNX2_NVM_CFG1_PASS_MODE
BNX2_NVM_CFG1_PASS_MODE
BNX2_NVM_CFG1_PROTECT_MODE
BNX2_NVM_CFG1_PROTECT_MODE
BNX2_NVM_CFG1_SEE_CLK_DIV
BNX2_NVM_CFG1_SEE_CLK_DIV
BNX2_NVM_CFG1_SPI_CLK_DIV
BNX2_NVM_CFG1_SPI_CLK_DIV
BNX2_NVM_CFG1_STATUS_BIT
BNX2_NVM_CFG1_STATUS_BIT
BNX2_NVM_CFG1_STATUS_BIT_BUFFER
BNX2_NVM_CFG1_STATUS_BIT_BUFFER
BNX2_NVM_CFG1_STATUS_BIT_FLASH_
BNX2_NVM_CFG1_STATUS_BIT_FLASH_
BNX2_NVM_CFG2
BNX2_NVM_CFG2
BNX2_NVM_CFG2_DUMMY
BNX2_NVM_CFG2_DUMMY
BNX2_NVM_CFG2_ERASE_CMD
BNX2_NVM_CFG2_ERASE_CMD
BNX2_NVM_CFG2_STATUS_CMD
BNX2_NVM_CFG2_STATUS_CMD
BNX2_NVM_CFG3
BNX2_NVM_CFG3
BNX2_NVM_CFG3_BUFFER_RD_CMD
BNX2_NVM_CFG3_BUFFER_RD_CMD
BNX2_NVM_CFG3_BUFFER_WRITE_CMD
BNX2_NVM_CFG3_BUFFER_WRITE_CMD
BNX2_NVM_CFG3_READ_CMD
BNX2_NVM_CFG3_READ_CMD
BNX2_NVM_CFG3_WRITE_CMD
BNX2_NVM_CFG3_WRITE_CMD
BNX2_NVM_COMMAND
BNX2_NVM_COMMAND
BNX2_NVM_COMMAND_DOIT
BNX2_NVM_COMMAND_DOIT
BNX2_NVM_COMMAND_DONE
BNX2_NVM_COMMAND_DONE
BNX2_NVM_COMMAND_ERASE
BNX2_NVM_COMMAND_ERASE
BNX2_NVM_COMMAND_EWSR
BNX2_NVM_COMMAND_EWSR
BNX2_NVM_COMMAND_FIRST
BNX2_NVM_COMMAND_FIRST
BNX2_NVM_COMMAND_LAST
BNX2_NVM_COMMAND_LAST
BNX2_NVM_COMMAND_RST
BNX2_NVM_COMMAND_RST
BNX2_NVM_COMMAND_WR
BNX2_NVM_COMMAND_WR
BNX2_NVM_COMMAND_WRDI
BNX2_NVM_COMMAND_WRDI
BNX2_NVM_COMMAND_WREN
BNX2_NVM_COMMAND_WREN
BNX2_NVM_COMMAND_WRSR
BNX2_NVM_COMMAND_WRSR
BNX2_NVM_READ
BNX2_NVM_READ
BNX2_NVM_READ_NVM_READ_VALUE
BNX2_NVM_READ_NVM_READ_VALUE
BNX2_NVM_READ_NVM_READ_VALUE_BI
BNX2_NVM_READ_NVM_READ_VALUE_BI
BNX2_NVM_READ_NVM_READ_VALUE_CS
BNX2_NVM_READ_NVM_READ_VALUE_CS
BNX2_NVM_READ_NVM_READ_VALUE_EE
BNX2_NVM_READ_NVM_READ_VALUE_EE
BNX2_NVM_READ_NVM_READ_VALUE_EE
BNX2_NVM_READ_NVM_READ_VALUE_EE
BNX2_NVM_READ_NVM_READ_VALUE_SC
BNX2_NVM_READ_NVM_READ_VALUE_SC
BNX2_NVM_READ_NVM_READ_VALUE_SI
BNX2_NVM_READ_NVM_READ_VALUE_SI
BNX2_NVM_READ_NVM_READ_VALUE_SO
BNX2_NVM_READ_NVM_READ_VALUE_SO
BNX2_NVM_STATUS
BNX2_NVM_STATUS
BNX2_NVM_STATUS_EE_FSM_STATE
BNX2_NVM_STATUS_EE_FSM_STATE
BNX2_NVM_STATUS_EQ_FSM_STATE
BNX2_NVM_STATUS_EQ_FSM_STATE
BNX2_NVM_STATUS_PI_FSM_STATE
BNX2_NVM_STATUS_PI_FSM_STATE
BNX2_NVM_SW_ARB
BNX2_NVM_SW_ARB
BNX2_NVM_SW_ARB_ARB_ARB0
BNX2_NVM_SW_ARB_ARB_ARB0
BNX2_NVM_SW_ARB_ARB_ARB1
BNX2_NVM_SW_ARB_ARB_ARB1
BNX2_NVM_SW_ARB_ARB_ARB2
BNX2_NVM_SW_ARB_ARB_ARB2
BNX2_NVM_SW_ARB_ARB_ARB3
BNX2_NVM_SW_ARB_ARB_ARB3
BNX2_NVM_SW_ARB_ARB_REQ_CLR0
BNX2_NVM_SW_ARB_ARB_REQ_CLR0
BNX2_NVM_SW_ARB_ARB_REQ_CLR1
BNX2_NVM_SW_ARB_ARB_REQ_CLR1
BNX2_NVM_SW_ARB_ARB_REQ_CLR2
BNX2_NVM_SW_ARB_ARB_REQ_CLR2
BNX2_NVM_SW_ARB_ARB_REQ_CLR3
BNX2_NVM_SW_ARB_ARB_REQ_CLR3
BNX2_NVM_SW_ARB_ARB_REQ_SET0
BNX2_NVM_SW_ARB_ARB_REQ_SET0
BNX2_NVM_SW_ARB_ARB_REQ_SET1
BNX2_NVM_SW_ARB_ARB_REQ_SET1
BNX2_NVM_SW_ARB_ARB_REQ_SET2
BNX2_NVM_SW_ARB_ARB_REQ_SET2
BNX2_NVM_SW_ARB_ARB_REQ_SET3
BNX2_NVM_SW_ARB_ARB_REQ_SET3
BNX2_NVM_SW_ARB_REQ0
BNX2_NVM_SW_ARB_REQ0
BNX2_NVM_SW_ARB_REQ1
BNX2_NVM_SW_ARB_REQ1
BNX2_NVM_SW_ARB_REQ2
BNX2_NVM_SW_ARB_REQ2
BNX2_NVM_SW_ARB_REQ3
BNX2_NVM_SW_ARB_REQ3
BNX2_NVM_WRITE
BNX2_NVM_WRITE
BNX2_NVM_WRITE_NVM_WRITE_VALUE
BNX2_NVM_WRITE_NVM_WRITE_VALUE
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE_NVM_WRITE_VALUE_
BNX2_NVM_WRITE1
BNX2_NVM_WRITE1
BNX2_NVM_WRITE1_SR_DATA
BNX2_NVM_WRITE1_SR_DATA
BNX2_NVM_WRITE1_WRDI_CMD
BNX2_NVM_WRITE1_WRDI_CMD
BNX2_NVM_WRITE1_WREN_CMD
BNX2_NVM_WRITE1_WREN_CMD
BNX2_PCI_CONFIG_1
BNX2_PCI_CONFIG_1
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_READ_BOUNDARY
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_1_WRITE_BOUNDAR
BNX2_PCI_CONFIG_2
BNX2_PCI_CONFIG_2
BNX2_PCI_CONFIG_2_BAR1_64ENA
BNX2_PCI_CONFIG_2_BAR1_64ENA
BNX2_PCI_CONFIG_2_BAR1_SIZE
BNX2_PCI_CONFIG_2_BAR1_SIZE
BNX2_PCI_CONFIG_2_BAR1_SIZE_128
BNX2_PCI_CONFIG_2_BAR1_SIZE_128
BNX2_PCI_CONFIG_2_BAR1_SIZE_128
BNX2_PCI_CONFIG_2_BAR1_SIZE_128
BNX2_PCI_CONFIG_2_BAR1_SIZE_16M
BNX2_PCI_CONFIG_2_BAR1_SIZE_16M
BNX2_PCI_CONFIG_2_BAR1_SIZE_1G
BNX2_PCI_CONFIG_2_BAR1_SIZE_1G
BNX2_PCI_CONFIG_2_BAR1_SIZE_1M
BNX2_PCI_CONFIG_2_BAR1_SIZE_1M
BNX2_PCI_CONFIG_2_BAR1_SIZE_256
BNX2_PCI_CONFIG_2_BAR1_SIZE_256
BNX2_PCI_CONFIG_2_BAR1_SIZE_256
BNX2_PCI_CONFIG_2_BAR1_SIZE_256
BNX2_PCI_CONFIG_2_BAR1_SIZE_2M
BNX2_PCI_CONFIG_2_BAR1_SIZE_2M
BNX2_PCI_CONFIG_2_BAR1_SIZE_32M
BNX2_PCI_CONFIG_2_BAR1_SIZE_32M
BNX2_PCI_CONFIG_2_BAR1_SIZE_4M
BNX2_PCI_CONFIG_2_BAR1_SIZE_4M
BNX2_PCI_CONFIG_2_BAR1_SIZE_512
BNX2_PCI_CONFIG_2_BAR1_SIZE_512
BNX2_PCI_CONFIG_2_BAR1_SIZE_512
BNX2_PCI_CONFIG_2_BAR1_SIZE_512
BNX2_PCI_CONFIG_2_BAR1_SIZE_64K
BNX2_PCI_CONFIG_2_BAR1_SIZE_64K
BNX2_PCI_CONFIG_2_BAR1_SIZE_64M
BNX2_PCI_CONFIG_2_BAR1_SIZE_64M
BNX2_PCI_CONFIG_2_BAR1_SIZE_8M
BNX2_PCI_CONFIG_2_BAR1_SIZE_8M
BNX2_PCI_CONFIG_2_BAR1_SIZE_DIS
BNX2_PCI_CONFIG_2_BAR1_SIZE_DIS
BNX2_PCI_CONFIG_2_CFG_CYCLE_RET
BNX2_PCI_CONFIG_2_CFG_CYCLE_RET
BNX2_PCI_CONFIG_2_EXP_ROM_RETRY
BNX2_PCI_CONFIG_2_EXP_ROM_RETRY
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_
BNX2_PCI_CONFIG_2_FIRST_CFG_DON
BNX2_PCI_CONFIG_2_FIRST_CFG_DON
BNX2_PCI_CONFIG_2_FORCE_32_BIT_
BNX2_PCI_CONFIG_2_FORCE_32_BIT_
BNX2_PCI_CONFIG_2_FORCE_32_BIT_
BNX2_PCI_CONFIG_2_FORCE_32_BIT_
BNX2_PCI_CONFIG_2_KEEP_REQ_ASSE
BNX2_PCI_CONFIG_2_KEEP_REQ_ASSE
BNX2_PCI_CONFIG_2_MAX_READ_LIMI
BNX2_PCI_CONFIG_2_MAX_READ_LIMI
BNX2_PCI_CONFIG_2_MAX_READ_LIMI
BNX2_PCI_CONFIG_2_MAX_READ_LIMI
BNX2_PCI_CONFIG_2_MAX_READ_LIMI
BNX2_PCI_CONFIG_2_MAX_READ_LIMI
BNX2_PCI_CONFIG_2_MAX_READ_LIMI
BNX2_PCI_CONFIG_2_MAX_READ_LIMI
BNX2_PCI_CONFIG_2_MAX_READ_LIMI
BNX2_PCI_CONFIG_2_MAX_READ_LIMI
BNX2_PCI_CONFIG_2_MAX_SPLIT_LIM
BNX2_PCI_CONFIG_2_MAX_SPLIT_LIM
BNX2_PCI_CONFIG_3
BNX2_PCI_CONFIG_3
BNX2_PCI_CONFIG_3_FORCE_PME
BNX2_PCI_CONFIG_3_FORCE_PME
BNX2_PCI_CONFIG_3_PCI_POWER
BNX2_PCI_CONFIG_3_PCI_POWER
BNX2_PCI_CONFIG_3_PM_STATE
BNX2_PCI_CONFIG_3_PM_STATE
BNX2_PCI_CONFIG_3_PME_ENABLE
BNX2_PCI_CONFIG_3_PME_ENABLE
BNX2_PCI_CONFIG_3_PME_STATUS
BNX2_PCI_CONFIG_3_PME_STATUS
BNX2_PCI_CONFIG_3_STICKY_BYTE
BNX2_PCI_CONFIG_3_STICKY_BYTE
BNX2_PCI_CONFIG_3_VAUX_PRESET
BNX2_PCI_CONFIG_3_VAUX_PRESET
BNX2_PCI_EXP_ROM_ADDR
BNX2_PCI_EXP_ROM_ADDR
BNX2_PCI_EXP_ROM_ADDR_ADDRESS
BNX2_PCI_EXP_ROM_ADDR_ADDRESS
BNX2_PCI_EXP_ROM_ADDR_REQ
BNX2_PCI_EXP_ROM_ADDR_REQ
BNX2_PCI_EXP_ROM_DATA
BNX2_PCI_EXP_ROM_DATA
BNX2_PCI_GRC_WINDOW_ADDR
BNX2_PCI_GRC_WINDOW_ADDR
BNX2_PCI_GRC_WINDOW_ADDR_PCI_GR
BNX2_PCI_GRC_WINDOW_ADDR_PCI_GR
BNX2_PCI_ID_VAL1
BNX2_PCI_ID_VAL1
BNX2_PCI_ID_VAL1_DEVICE_ID
BNX2_PCI_ID_VAL1_DEVICE_ID
BNX2_PCI_ID_VAL1_VENDOR_ID
BNX2_PCI_ID_VAL1_VENDOR_ID
BNX2_PCI_ID_VAL2
BNX2_PCI_ID_VAL2
BNX2_PCI_ID_VAL2_SUBSYSTEM_ID
BNX2_PCI_ID_VAL2_SUBSYSTEM_ID
BNX2_PCI_ID_VAL2_SUBSYSTEM_VEND
BNX2_PCI_ID_VAL2_SUBSYSTEM_VEND
BNX2_PCI_ID_VAL3
BNX2_PCI_ID_VAL3
BNX2_PCI_ID_VAL3_CLASS_CODE
BNX2_PCI_ID_VAL3_CLASS_CODE
BNX2_PCI_ID_VAL3_REVISION_ID
BNX2_PCI_ID_VAL3_REVISION_ID
BNX2_PCI_ID_VAL4
BNX2_PCI_ID_VAL4
BNX2_PCI_ID_VAL4_CAP_ENA
BNX2_PCI_ID_VAL4_CAP_ENA
BNX2_PCI_ID_VAL4_CAP_ENA_0
BNX2_PCI_ID_VAL4_CAP_ENA_0
BNX2_PCI_ID_VAL4_CAP_ENA_1
BNX2_PCI_ID_VAL4_CAP_ENA_1
BNX2_PCI_ID_VAL4_CAP_ENA_10
BNX2_PCI_ID_VAL4_CAP_ENA_10
BNX2_PCI_ID_VAL4_CAP_ENA_11
BNX2_PCI_ID_VAL4_CAP_ENA_11
BNX2_PCI_ID_VAL4_CAP_ENA_12
BNX2_PCI_ID_VAL4_CAP_ENA_12
BNX2_PCI_ID_VAL4_CAP_ENA_13
BNX2_PCI_ID_VAL4_CAP_ENA_13
BNX2_PCI_ID_VAL4_CAP_ENA_14
BNX2_PCI_ID_VAL4_CAP_ENA_14
BNX2_PCI_ID_VAL4_CAP_ENA_15
BNX2_PCI_ID_VAL4_CAP_ENA_15
BNX2_PCI_ID_VAL4_CAP_ENA_2
BNX2_PCI_ID_VAL4_CAP_ENA_2
BNX2_PCI_ID_VAL4_CAP_ENA_3
BNX2_PCI_ID_VAL4_CAP_ENA_3
BNX2_PCI_ID_VAL4_CAP_ENA_4
BNX2_PCI_ID_VAL4_CAP_ENA_4
BNX2_PCI_ID_VAL4_CAP_ENA_5
BNX2_PCI_ID_VAL4_CAP_ENA_5
BNX2_PCI_ID_VAL4_CAP_ENA_6
BNX2_PCI_ID_VAL4_CAP_ENA_6
BNX2_PCI_ID_VAL4_CAP_ENA_7
BNX2_PCI_ID_VAL4_CAP_ENA_7
BNX2_PCI_ID_VAL4_CAP_ENA_8
BNX2_PCI_ID_VAL4_CAP_ENA_8
BNX2_PCI_ID_VAL4_CAP_ENA_9
BNX2_PCI_ID_VAL4_CAP_ENA_9
BNX2_PCI_ID_VAL4_MAX_133_ADVERT
BNX2_PCI_ID_VAL4_MAX_133_ADVERT
BNX2_PCI_ID_VAL4_MAX_64_ADVERTI
BNX2_PCI_ID_VAL4_MAX_64_ADVERTI
BNX2_PCI_ID_VAL4_MAX_CUMULATIVE
BNX2_PCI_ID_VAL4_MAX_CUMULATIVE
BNX2_PCI_ID_VAL4_MAX_MEM_READ_S
BNX2_PCI_ID_VAL4_MAX_MEM_READ_S
BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE
BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE
BNX2_PCI_ID_VAL4_MSI_ADVERTIZE
BNX2_PCI_ID_VAL4_MSI_ADVERTIZE
BNX2_PCI_ID_VAL4_MSI_ENABLE
BNX2_PCI_ID_VAL4_MSI_ENABLE
BNX2_PCI_ID_VAL4_MSI_LIMIT
BNX2_PCI_ID_VAL4_MSI_LIMIT
BNX2_PCI_ID_VAL4_PM_SCALE_PRG
BNX2_PCI_ID_VAL4_PM_SCALE_PRG
BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0
BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0
BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1
BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1
BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2
BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2
BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3
BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3
BNX2_PCI_ID_VAL5
BNX2_PCI_ID_VAL5
BNX2_PCI_ID_VAL5_D1_SUPPORT
BNX2_PCI_ID_VAL5_D1_SUPPORT
BNX2_PCI_ID_VAL5_D2_SUPPORT
BNX2_PCI_ID_VAL5_D2_SUPPORT
BNX2_PCI_ID_VAL5_PME_IN_D0
BNX2_PCI_ID_VAL5_PME_IN_D0
BNX2_PCI_ID_VAL5_PME_IN_D1
BNX2_PCI_ID_VAL5_PME_IN_D1
BNX2_PCI_ID_VAL5_PME_IN_D2
BNX2_PCI_ID_VAL5_PME_IN_D2
BNX2_PCI_ID_VAL5_PME_IN_D3_HOT
BNX2_PCI_ID_VAL5_PME_IN_D3_HOT
BNX2_PCI_ID_VAL6
BNX2_PCI_ID_VAL6
BNX2_PCI_ID_VAL6_BIST
BNX2_PCI_ID_VAL6_BIST
BNX2_PCI_ID_VAL6_MAX_LAT
BNX2_PCI_ID_VAL6_MAX_LAT
BNX2_PCI_ID_VAL6_MIN_GNT
BNX2_PCI_ID_VAL6_MIN_GNT
BNX2_PCI_MSI_ADDR_H
BNX2_PCI_MSI_ADDR_H
BNX2_PCI_MSI_ADDR_L
BNX2_PCI_MSI_ADDR_L
BNX2_PCI_MSI_DATA
BNX2_PCI_MSI_DATA
BNX2_PCI_MSI_DATA_PCI_MSI_DATA
BNX2_PCI_MSI_DATA_PCI_MSI_DATA
BNX2_PCI_PCIX_EXTENDED_STATUS
BNX2_PCI_PCIX_EXTENDED_STATUS
BNX2_PCI_PCIX_EXTENDED_STATUS_L
BNX2_PCI_PCIX_EXTENDED_STATUS_L
BNX2_PCI_PCIX_EXTENDED_STATUS_N
BNX2_PCI_PCIX_EXTENDED_STATUS_N
BNX2_PCI_PCIX_EXTENDED_STATUS_S
BNX2_PCI_PCIX_EXTENDED_STATUS_S
BNX2_PCI_PCIX_EXTENDED_STATUS_S
BNX2_PCI_PCIX_EXTENDED_STATUS_S
BNX2_PCI_PM_DATA_A
BNX2_PCI_PM_DATA_A
BNX2_PCI_PM_DATA_A_PM_DATA_0_PR
BNX2_PCI_PM_DATA_A_PM_DATA_0_PR
BNX2_PCI_PM_DATA_A_PM_DATA_1_PR
BNX2_PCI_PM_DATA_A_PM_DATA_1_PR
BNX2_PCI_PM_DATA_A_PM_DATA_2_PR
BNX2_PCI_PM_DATA_A_PM_DATA_2_PR
BNX2_PCI_PM_DATA_A_PM_DATA_3_PR
BNX2_PCI_PM_DATA_A_PM_DATA_3_PR
BNX2_PCI_PM_DATA_B
BNX2_PCI_PM_DATA_B
BNX2_PCI_PM_DATA_B_PM_DATA_4_PR
BNX2_PCI_PM_DATA_B_PM_DATA_4_PR
BNX2_PCI_PM_DATA_B_PM_DATA_5_PR
BNX2_PCI_PM_DATA_B_PM_DATA_5_PR
BNX2_PCI_PM_DATA_B_PM_DATA_6_PR
BNX2_PCI_PM_DATA_B_PM_DATA_6_PR
BNX2_PCI_PM_DATA_B_PM_DATA_7_PR
BNX2_PCI_PM_DATA_B_PM_DATA_7_PR
BNX2_PCI_SWAP_DIAG0
BNX2_PCI_SWAP_DIAG0
BNX2_PCI_SWAP_DIAG1
BNX2_PCI_SWAP_DIAG1
BNX2_PCI_VPD_ADDR_FLAG
BNX2_PCI_VPD_ADDR_FLAG
BNX2_PCI_VPD_ADDR_FLAG_ADDRESS
BNX2_PCI_VPD_ADDR_FLAG_ADDRESS
BNX2_PCI_VPD_ADDR_FLAG_WR
BNX2_PCI_VPD_ADDR_FLAG_WR
BNX2_PCI_VPD_DATA
BNX2_PCI_VPD_DATA
BNX2_PCI_VPD_INTF
BNX2_PCI_VPD_INTF
BNX2_PCI_VPD_INTF_INTF_REQ
BNX2_PCI_VPD_INTF_INTF_REQ
BNX2_PCICFG_INT_ACK_CMD
BNX2_PCICFG_INT_ACK_CMD
BNX2_PCICFG_INT_ACK_CMD_INDEX
BNX2_PCICFG_INT_ACK_CMD_INDEX
BNX2_PCICFG_INT_ACK_CMD_INDEX_V
BNX2_PCICFG_INT_ACK_CMD_INDEX_V
BNX2_PCICFG_INT_ACK_CMD_MASK_IN
BNX2_PCICFG_INT_ACK_CMD_MASK_IN
BNX2_PCICFG_INT_ACK_CMD_USE_INT
BNX2_PCICFG_INT_ACK_CMD_USE_INT
BNX2_PCICFG_MAILBOX_QUEUE_ADDR
BNX2_PCICFG_MAILBOX_QUEUE_ADDR
BNX2_PCICFG_MAILBOX_QUEUE_DATA
BNX2_PCICFG_MAILBOX_QUEUE_DATA
BNX2_PCICFG_MISC_CONFIG
BNX2_PCICFG_MISC_CONFIG
BNX2_PCICFG_MISC_CONFIG_ASIC_BA
BNX2_PCICFG_MISC_CONFIG_ASIC_BA
BNX2_PCICFG_MISC_CONFIG_ASIC_ID
BNX2_PCICFG_MISC_CONFIG_ASIC_ID
BNX2_PCICFG_MISC_CONFIG_ASIC_ME
BNX2_PCICFG_MISC_CONFIG_ASIC_ME
BNX2_PCICFG_MISC_CONFIG_CLOCK_C
BNX2_PCICFG_MISC_CONFIG_CLOCK_C
BNX2_PCICFG_MISC_CONFIG_CORE_RS
BNX2_PCICFG_MISC_CONFIG_CORE_RS
BNX2_PCICFG_MISC_CONFIG_CORE_RS
BNX2_PCICFG_MISC_CONFIG_CORE_RS
BNX2_PCICFG_MISC_CONFIG_REG_WIN
BNX2_PCICFG_MISC_CONFIG_REG_WIN
BNX2_PCICFG_MISC_CONFIG_TARGET_
BNX2_PCICFG_MISC_CONFIG_TARGET_
BNX2_PCICFG_MISC_CONFIG_TARGET_
BNX2_PCICFG_MISC_CONFIG_TARGET_
BNX2_PCICFG_MISC_CONFIG_TARGET_
BNX2_PCICFG_MISC_CONFIG_TARGET_
BNX2_PCICFG_MISC_STATUS
BNX2_PCICFG_MISC_STATUS
BNX2_PCICFG_MISC_STATUS_32BIT_D
BNX2_PCICFG_MISC_STATUS_32BIT_D
BNX2_PCICFG_MISC_STATUS_INTA_VA
BNX2_PCICFG_MISC_STATUS_INTA_VA
BNX2_PCICFG_MISC_STATUS_M66EN
BNX2_PCICFG_MISC_STATUS_M66EN
BNX2_PCICFG_MISC_STATUS_PCIX_DE
BNX2_PCICFG_MISC_STATUS_PCIX_DE
BNX2_PCICFG_MISC_STATUS_PCIX_SP
BNX2_PCICFG_MISC_STATUS_PCIX_SP
BNX2_PCICFG_MISC_STATUS_PCIX_SP
BNX2_PCICFG_MISC_STATUS_PCIX_SP
BNX2_PCICFG_MISC_STATUS_PCIX_SP
BNX2_PCICFG_MISC_STATUS_PCIX_SP
BNX2_PCICFG_MISC_STATUS_PCIX_SP
BNX2_PCICFG_MISC_STATUS_PCIX_SP
BNX2_PCICFG_MISC_STATUS_PCIX_SP
BNX2_PCICFG_MISC_STATUS_PCIX_SP
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_PCI_CLOCK_CONTROL_B
BNX2_PCICFG_REG_WINDOW
BNX2_PCICFG_REG_WINDOW
BNX2_PCICFG_REG_WINDOW_ADDRESS
BNX2_PCICFG_REG_WINDOW_ADDRESS
BNX2_PCICFG_STATUS_BIT_CLEAR_CM
BNX2_PCICFG_STATUS_BIT_CLEAR_CM
BNX2_PCICFG_STATUS_BIT_SET_CMD
BNX2_PCICFG_STATUS_BIT_SET_CMD
bnx2_phy_get_pause_adv
bnx2_phy_get_pause_adv
bnx2_poll
bnx2_poll
bnx2_poll_link
bnx2_poll_link
BNX2_PORT_FEATURE
BNX2_PORT_FEATURE
BNX2_PORT_FEATURE_ASF_ENABLED
BNX2_PORT_FEATURE_ASF_ENABLED
BNX2_PORT_FEATURE_BAR1_SIZE_128
BNX2_PORT_FEATURE_BAR1_SIZE_128
BNX2_PORT_FEATURE_BAR1_SIZE_128
BNX2_PORT_FEATURE_BAR1_SIZE_128
BNX2_PORT_FEATURE_BAR1_SIZE_16M
BNX2_PORT_FEATURE_BAR1_SIZE_16M
BNX2_PORT_FEATURE_BAR1_SIZE_1G
BNX2_PORT_FEATURE_BAR1_SIZE_1G
BNX2_PORT_FEATURE_BAR1_SIZE_1M
BNX2_PORT_FEATURE_BAR1_SIZE_1M
BNX2_PORT_FEATURE_BAR1_SIZE_256
BNX2_PORT_FEATURE_BAR1_SIZE_256
BNX2_PORT_FEATURE_BAR1_SIZE_256
BNX2_PORT_FEATURE_BAR1_SIZE_256
BNX2_PORT_FEATURE_BAR1_SIZE_2M
BNX2_PORT_FEATURE_BAR1_SIZE_2M
BNX2_PORT_FEATURE_BAR1_SIZE_32M
BNX2_PORT_FEATURE_BAR1_SIZE_32M
BNX2_PORT_FEATURE_BAR1_SIZE_4M
BNX2_PORT_FEATURE_BAR1_SIZE_4M
BNX2_PORT_FEATURE_BAR1_SIZE_512
BNX2_PORT_FEATURE_BAR1_SIZE_512
BNX2_PORT_FEATURE_BAR1_SIZE_512
BNX2_PORT_FEATURE_BAR1_SIZE_512
BNX2_PORT_FEATURE_BAR1_SIZE_64K
BNX2_PORT_FEATURE_BAR1_SIZE_64K
BNX2_PORT_FEATURE_BAR1_SIZE_64M
BNX2_PORT_FEATURE_BAR1_SIZE_64M
BNX2_PORT_FEATURE_BAR1_SIZE_8M
BNX2_PORT_FEATURE_BAR1_SIZE_8M
BNX2_PORT_FEATURE_BAR1_SIZE_DIS
BNX2_PORT_FEATURE_BAR1_SIZE_DIS
BNX2_PORT_FEATURE_BAR1_SIZE_MAS
BNX2_PORT_FEATURE_BAR1_SIZE_MAS
BNX2_PORT_FEATURE_IMD
BNX2_PORT_FEATURE_IMD
BNX2_PORT_FEATURE_IMD_ENABLED
BNX2_PORT_FEATURE_IMD_ENABLED
BNX2_PORT_FEATURE_IMD_LINK_OVER
BNX2_PORT_FEATURE_IMD_LINK_OVER
BNX2_PORT_FEATURE_IMD_LINK_OVER
BNX2_PORT_FEATURE_IMD_LINK_OVER
BNX2_PORT_FEATURE_MBA
BNX2_PORT_FEATURE_MBA
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BIOS_BOOT
BNX2_PORT_FEATURE_MBA_BOOT_AGEN
BNX2_PORT_FEATURE_MBA_BOOT_AGEN
BNX2_PORT_FEATURE_MBA_BOOT_AGEN
BNX2_PORT_FEATURE_MBA_BOOT_AGEN
BNX2_PORT_FEATURE_MBA_BOOT_AGEN
BNX2_PORT_FEATURE_MBA_BOOT_AGEN
BNX2_PORT_FEATURE_MBA_BOOT_AGEN
BNX2_PORT_FEATURE_MBA_BOOT_AGEN
BNX2_PORT_FEATURE_MBA_BOOT_AGEN
BNX2_PORT_FEATURE_MBA_BOOT_AGEN
BNX2_PORT_FEATURE_MBA_ENABLED
BNX2_PORT_FEATURE_MBA_ENABLED
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_EXP_ROM_S
BNX2_PORT_FEATURE_MBA_HOTKEY_CT
BNX2_PORT_FEATURE_MBA_HOTKEY_CT
BNX2_PORT_FEATURE_MBA_HOTKEY_CT
BNX2_PORT_FEATURE_MBA_HOTKEY_CT
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_LINK_SPEE
BNX2_PORT_FEATURE_MBA_MSG_TIMEO
BNX2_PORT_FEATURE_MBA_MSG_TIMEO
BNX2_PORT_FEATURE_MBA_MSG_TIMEO
BNX2_PORT_FEATURE_MBA_MSG_TIMEO
BNX2_PORT_FEATURE_MBA_SETUP_PRO
BNX2_PORT_FEATURE_MBA_SETUP_PRO
BNX2_PORT_FEATURE_MBA_VLAN_ENAB
BNX2_PORT_FEATURE_MBA_VLAN_ENAB
BNX2_PORT_FEATURE_MBA_VLAN_TAG_
BNX2_PORT_FEATURE_MBA_VLAN_TAG_
BNX2_PORT_FEATURE_VLAN
BNX2_PORT_FEATURE_VLAN
BNX2_PORT_FEATURE_WOL
BNX2_PORT_FEATURE_WOL
BNX2_PORT_FEATURE_WOL_AUTONEG_A
BNX2_PORT_FEATURE_WOL_AUTONEG_A
BNX2_PORT_FEATURE_WOL_DEFAULT_A
BNX2_PORT_FEATURE_WOL_DEFAULT_A
BNX2_PORT_FEATURE_WOL_DEFAULT_D
BNX2_PORT_FEATURE_WOL_DEFAULT_D
BNX2_PORT_FEATURE_WOL_DEFAULT_M
BNX2_PORT_FEATURE_WOL_DEFAULT_M
BNX2_PORT_FEATURE_WOL_DEFAULT_M
BNX2_PORT_FEATURE_WOL_DEFAULT_M
BNX2_PORT_FEATURE_WOL_DEFAULT_M
BNX2_PORT_FEATURE_WOL_DEFAULT_M
BNX2_PORT_FEATURE_WOL_DEFAULT_S
BNX2_PORT_FEATURE_WOL_DEFAULT_S
BNX2_PORT_FEATURE_WOL_ENABLED
BNX2_PORT_FEATURE_WOL_ENABLED
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_LINK_SPEE
BNX2_PORT_FEATURE_WOL_RESERVED_
BNX2_PORT_FEATURE_WOL_RESERVED_
BNX2_PORT_FEATURE_WOL_RESERVED_
BNX2_PORT_FEATURE_WOL_RESERVED_
BNX2_PORT_HW_CFG_CFG_DFLT_LINK_
BNX2_PORT_HW_CFG_CFG_DFLT_LINK_
BNX2_PORT_HW_CFG_CFG_DFLT_LINK_
BNX2_PORT_HW_CFG_CFG_DFLT_LINK_
BNX2_PORT_HW_CFG_CFG_DFLT_LINK_
BNX2_PORT_HW_CFG_CFG_DFLT_LINK_
BNX2_PORT_HW_CFG_CFG_DFLT_LINK_
BNX2_PORT_HW_CFG_CFG_DFLT_LINK_
BNX2_PORT_HW_CFG_CFG_TXCTL3_MAS
BNX2_PORT_HW_CFG_CFG_TXCTL3_MAS
BNX2_PORT_HW_CFG_CONFIG
BNX2_PORT_HW_CFG_CONFIG
BNX2_PORT_HW_CFG_IMD_MAC_A_LOWE
BNX2_PORT_HW_CFG_IMD_MAC_A_LOWE
BNX2_PORT_HW_CFG_IMD_MAC_A_UPPE
BNX2_PORT_HW_CFG_IMD_MAC_A_UPPE
BNX2_PORT_HW_CFG_IMD_MAC_B_LOWE
BNX2_PORT_HW_CFG_IMD_MAC_B_LOWE
BNX2_PORT_HW_CFG_IMD_MAC_B_UPPE
BNX2_PORT_HW_CFG_IMD_MAC_B_UPPE
BNX2_PORT_HW_CFG_ISCSI_MAC_LOWE
BNX2_PORT_HW_CFG_ISCSI_MAC_LOWE
BNX2_PORT_HW_CFG_ISCSI_MAC_UPPE
BNX2_PORT_HW_CFG_ISCSI_MAC_UPPE
BNX2_PORT_HW_CFG_MAC_LOWER
BNX2_PORT_HW_CFG_MAC_LOWER
BNX2_PORT_HW_CFG_MAC_UPPER
BNX2_PORT_HW_CFG_MAC_UPPER
BNX2_PORT_HW_CFG_UPPERMAC_MASK
BNX2_PORT_HW_CFG_UPPERMAC_MASK
BNX2_PORT2_FEATURE
BNX2_PORT2_FEATURE
BNX2_PORT2_FEATURE_IMD
BNX2_PORT2_FEATURE_IMD
BNX2_PORT2_FEATURE_MBA
BNX2_PORT2_FEATURE_MBA
BNX2_PORT2_FEATURE_VLAN
BNX2_PORT2_FEATURE_VLAN
BNX2_PORT2_FEATURE_WOL
BNX2_PORT2_FEATURE_WOL
bnx2_probe
bnx2_probe
BNX2_RBUF_BUF_DATA
BNX2_RBUF_BUF_DATA
BNX2_RBUF_CLIST_DATA
BNX2_RBUF_CLIST_DATA
BNX2_RBUF_COMMAND
BNX2_RBUF_COMMAND
BNX2_RBUF_COMMAND_ALLOC_REQ
BNX2_RBUF_COMMAND_ALLOC_REQ
BNX2_RBUF_COMMAND_ENABLED
BNX2_RBUF_COMMAND_ENABLED
BNX2_RBUF_COMMAND_FREE_INIT
BNX2_RBUF_COMMAND_FREE_INIT
BNX2_RBUF_COMMAND_OVER_FREE
BNX2_RBUF_COMMAND_OVER_FREE
BNX2_RBUF_COMMAND_RAM_INIT
BNX2_RBUF_COMMAND_RAM_INIT
BNX2_RBUF_CONFIG
BNX2_RBUF_CONFIG
BNX2_RBUF_CONFIG_XOFF_TRIP
BNX2_RBUF_CONFIG_XOFF_TRIP
BNX2_RBUF_CONFIG_XON_TRIP
BNX2_RBUF_CONFIG_XON_TRIP
BNX2_RBUF_CONFIG2
BNX2_RBUF_CONFIG2
BNX2_RBUF_CONFIG2_MAC_DROP_TRIP
BNX2_RBUF_CONFIG2_MAC_DROP_TRIP
BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP
BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP
BNX2_RBUF_CONFIG3
BNX2_RBUF_CONFIG3
BNX2_RBUF_CONFIG3_CU_DROP_TRIP
BNX2_RBUF_CONFIG3_CU_DROP_TRIP
BNX2_RBUF_CONFIG3_CU_KEEP_TRIP
BNX2_RBUF_CONFIG3_CU_KEEP_TRIP
BNX2_RBUF_FW_BUF_ALLOC
BNX2_RBUF_FW_BUF_ALLOC
BNX2_RBUF_FW_BUF_ALLOC_VALUE
BNX2_RBUF_FW_BUF_ALLOC_VALUE
BNX2_RBUF_FW_BUF_FREE
BNX2_RBUF_FW_BUF_FREE
BNX2_RBUF_FW_BUF_FREE_COUNT
BNX2_RBUF_FW_BUF_FREE_COUNT
BNX2_RBUF_FW_BUF_FREE_HEAD
BNX2_RBUF_FW_BUF_FREE_HEAD
BNX2_RBUF_FW_BUF_FREE_TAIL
BNX2_RBUF_FW_BUF_FREE_TAIL
BNX2_RBUF_FW_BUF_SEL
BNX2_RBUF_FW_BUF_SEL
BNX2_RBUF_FW_BUF_SEL_COUNT
BNX2_RBUF_FW_BUF_SEL_COUNT
BNX2_RBUF_FW_BUF_SEL_HEAD
BNX2_RBUF_FW_BUF_SEL_HEAD
BNX2_RBUF_FW_BUF_SEL_TAIL
BNX2_RBUF_FW_BUF_SEL_TAIL
BNX2_RBUF_PKT_DATA
BNX2_RBUF_PKT_DATA
BNX2_RBUF_STATUS1
BNX2_RBUF_STATUS1
BNX2_RBUF_STATUS1_FREE_COUNT
BNX2_RBUF_STATUS1_FREE_COUNT
BNX2_RBUF_STATUS2
BNX2_RBUF_STATUS2
BNX2_RBUF_STATUS2_FREE_HEAD
BNX2_RBUF_STATUS2_FREE_HEAD
BNX2_RBUF_STATUS2_FREE_TAIL
BNX2_RBUF_STATUS2_FREE_TAIL
bnx2_read_phy
bnx2_read_phy
bnx2_reg_rd_ind
bnx2_reg_rd_ind
bnx2_reg_wr_ind
bnx2_reg_wr_ind
bnx2_report_fw_link
bnx2_report_fw_link
bnx2_report_link
bnx2_report_link
bnx2_reset_chip
bnx2_reset_chip
bnx2_reset_nic
bnx2_reset_nic
bnx2_reset_phy
bnx2_reset_phy
bnx2_resolve_flow_ctrl
bnx2_resolve_flow_ctrl
BNX2_RPM_ACPI_DBG_BUF_W00
BNX2_RPM_ACPI_DBG_BUF_W00
BNX2_RPM_ACPI_DBG_BUF_W01
BNX2_RPM_ACPI_DBG_BUF_W01
BNX2_RPM_ACPI_DBG_BUF_W02
BNX2_RPM_ACPI_DBG_BUF_W02
BNX2_RPM_ACPI_DBG_BUF_W03
BNX2_RPM_ACPI_DBG_BUF_W03
BNX2_RPM_ACPI_DBG_BUF_W10
BNX2_RPM_ACPI_DBG_BUF_W10
BNX2_RPM_ACPI_DBG_BUF_W11
BNX2_RPM_ACPI_DBG_BUF_W11
BNX2_RPM_ACPI_DBG_BUF_W12
BNX2_RPM_ACPI_DBG_BUF_W12
BNX2_RPM_ACPI_DBG_BUF_W13
BNX2_RPM_ACPI_DBG_BUF_W13
BNX2_RPM_ACPI_DBG_BUF_W20
BNX2_RPM_ACPI_DBG_BUF_W20
BNX2_RPM_ACPI_DBG_BUF_W21
BNX2_RPM_ACPI_DBG_BUF_W21
BNX2_RPM_ACPI_DBG_BUF_W22
BNX2_RPM_ACPI_DBG_BUF_W22
BNX2_RPM_ACPI_DBG_BUF_W23
BNX2_RPM_ACPI_DBG_BUF_W23
BNX2_RPM_ACPI_DBG_BUF_W30
BNX2_RPM_ACPI_DBG_BUF_W30
BNX2_RPM_ACPI_DBG_BUF_W31
BNX2_RPM_ACPI_DBG_BUF_W31
BNX2_RPM_ACPI_DBG_BUF_W32
BNX2_RPM_ACPI_DBG_BUF_W32
BNX2_RPM_ACPI_DBG_BUF_W33
BNX2_RPM_ACPI_DBG_BUF_W33
BNX2_RPM_COMMAND
BNX2_RPM_COMMAND
BNX2_RPM_COMMAND_ENABLED
BNX2_RPM_COMMAND_ENABLED
BNX2_RPM_COMMAND_OVERRUN_ABORT
BNX2_RPM_COMMAND_OVERRUN_ABORT
BNX2_RPM_CONFIG
BNX2_RPM_CONFIG
BNX2_RPM_CONFIG_ACPI_ENA
BNX2_RPM_CONFIG_ACPI_ENA
BNX2_RPM_CONFIG_ACPI_KEEP
BNX2_RPM_CONFIG_ACPI_KEEP
BNX2_RPM_CONFIG_IGNORE_VLAN
BNX2_RPM_CONFIG_IGNORE_VLAN
BNX2_RPM_CONFIG_MP_KEEP
BNX2_RPM_CONFIG_MP_KEEP
BNX2_RPM_CONFIG_NO_PSD_HDR_CKSU
BNX2_RPM_CONFIG_NO_PSD_HDR_CKSU
BNX2_RPM_CONFIG_SORT_VECT_VAL
BNX2_RPM_CONFIG_SORT_VECT_VAL
BNX2_RPM_DEBUG0
BNX2_RPM_DEBUG0
BNX2_RPM_DEBUG0_DONE
BNX2_RPM_DEBUG0_DONE
BNX2_RPM_DEBUG0_FM_BCNT
BNX2_RPM_DEBUG0_FM_BCNT
BNX2_RPM_DEBUG0_FM_STARTED
BNX2_RPM_DEBUG0_FM_STARTED
BNX2_RPM_DEBUG0_IGNORE_VLAN
BNX2_RPM_DEBUG0_IGNORE_VLAN
BNX2_RPM_DEBUG0_IP_MORE_FRGMT
BNX2_RPM_DEBUG0_IP_MORE_FRGMT
BNX2_RPM_DEBUG0_LLC_SNAP
BNX2_RPM_DEBUG0_LLC_SNAP
BNX2_RPM_DEBUG0_RP_ENA_ACTIVE
BNX2_RPM_DEBUG0_RP_ENA_ACTIVE
BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_C
BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_C
BNX2_RPM_DEBUG0_T_DATA_OFST_VLD
BNX2_RPM_DEBUG0_T_DATA_OFST_VLD
BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP
BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP
BNX2_RPM_DEBUG0_T_IP_OFST_VLD
BNX2_RPM_DEBUG0_T_IP_OFST_VLD
BNX2_RPM_DEBUG0_T_TCP_OFST_VLD
BNX2_RPM_DEBUG0_T_TCP_OFST_VLD
BNX2_RPM_DEBUG0_T_UDP_OFST_VLD
BNX2_RPM_DEBUG0_T_UDP_OFST_VLD
BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM
BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM
BNX2_RPM_DEBUG0_WAIT_4_DONE
BNX2_RPM_DEBUG0_WAIT_4_DONE
BNX2_RPM_DEBUG1
BNX2_RPM_DEBUG1
BNX2_RPM_DEBUG1_EOF_0XTRA_WD
BNX2_RPM_DEBUG1_EOF_0XTRA_WD
BNX2_RPM_DEBUG1_FSM_CUR_ST
BNX2_RPM_DEBUG1_FSM_CUR_ST
BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_
BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_
BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_
BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_
BNX2_RPM_DEBUG1_FSM_CUR_ST_AH
BNX2_RPM_DEBUG1_FSM_CUR_ST_AH
BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA
BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA
BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP
BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP
BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_
BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_
BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP
BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP
BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP
BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP
BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP
BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP
BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP
BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP
BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE
BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE
BNX2_RPM_DEBUG1_FSM_CUR_ST_IP
BNX2_RPM_DEBUG1_FSM_CUR_ST_IP
BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_S
BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_S
BNX2_RPM_DEBUG1_FSM_CUR_ST_LATC
BNX2_RPM_DEBUG1_FSM_CUR_ST_LATC
BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP
BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP
BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP
BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP
BNX2_RPM_DEBUG1_HDR_BCNT
BNX2_RPM_DEBUG1_HDR_BCNT
BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D
BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D
BNX2_RPM_DEBUG1_VLAN_REMOVED_D1
BNX2_RPM_DEBUG1_VLAN_REMOVED_D1
BNX2_RPM_DEBUG1_VLAN_REMOVED_D2
BNX2_RPM_DEBUG1_VLAN_REMOVED_D2
BNX2_RPM_DEBUG2
BNX2_RPM_DEBUG2
BNX2_RPM_DEBUG2_CMD_HIT_VEC
BNX2_RPM_DEBUG2_CMD_HIT_VEC
BNX2_RPM_DEBUG2_FM_DISCARD
BNX2_RPM_DEBUG2_FM_DISCARD
BNX2_RPM_DEBUG2_IP_BCNT
BNX2_RPM_DEBUG2_IP_BCNT
BNX2_RPM_DEBUG2_IPIPE_EMPTY
BNX2_RPM_DEBUG2_IPIPE_EMPTY
BNX2_RPM_DEBUG2_LAST_RULE_IN_FM
BNX2_RPM_DEBUG2_LAST_RULE_IN_FM
BNX2_RPM_DEBUG2_LAST_RULE_IN_FM
BNX2_RPM_DEBUG2_LAST_RULE_IN_FM
BNX2_RPM_DEBUG2_THIS_CMD_M1
BNX2_RPM_DEBUG2_THIS_CMD_M1
BNX2_RPM_DEBUG2_THIS_CMD_M2
BNX2_RPM_DEBUG2_THIS_CMD_M2
BNX2_RPM_DEBUG2_THIS_CMD_M3
BNX2_RPM_DEBUG2_THIS_CMD_M3
BNX2_RPM_DEBUG2_THIS_CMD_M4
BNX2_RPM_DEBUG2_THIS_CMD_M4
BNX2_RPM_DEBUG3
BNX2_RPM_DEBUG3
BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR
BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR
BNX2_RPM_DEBUG3_CCODE_EOF_ERROR
BNX2_RPM_DEBUG3_CCODE_EOF_ERROR
BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY
BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY
BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAV
BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAV
BNX2_RPM_DEBUG3_DROP_NXT
BNX2_RPM_DEBUG3_DROP_NXT
BNX2_RPM_DEBUG3_DROP_NXT_VLD
BNX2_RPM_DEBUG3_DROP_NXT_VLD
BNX2_RPM_DEBUG3_FTQ_FSM
BNX2_RPM_DEBUG3_FTQ_FSM
BNX2_RPM_DEBUG3_FTQ_FSM_IDLE
BNX2_RPM_DEBUG3_FTQ_FSM_IDLE
BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_AC
BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_AC
BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FR
BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FR
BNX2_RPM_DEBUG3_MBALLOC_FSM
BNX2_RPM_DEBUG3_MBALLOC_FSM
BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_
BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_
BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE
BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE
BNX2_RPM_DEBUG3_MBFREE_FSM
BNX2_RPM_DEBUG3_MBFREE_FSM
BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE
BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE
BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT
BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT
BNX2_RPM_DEBUG3_MBWRITE_FSM
BNX2_RPM_DEBUG3_MBWRITE_FSM
BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA
BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA
BNX2_RPM_DEBUG3_MBWRITE_FSM_DON
BNX2_RPM_DEBUG3_MBWRITE_FSM_DON
BNX2_RPM_DEBUG3_MBWRITE_FSM_GET
BNX2_RPM_DEBUG3_MBWRITE_FSM_GET
BNX2_RPM_DEBUG3_MBWRITE_FSM_WAI
BNX2_RPM_DEBUG3_MBWRITE_FSM_WAI
BNX2_RPM_DEBUG3_MBWRITE_FSM_WAI
BNX2_RPM_DEBUG3_MBWRITE_FSM_WAI
BNX2_RPM_DEBUG3_MBWRITE_FSM_WAI
BNX2_RPM_DEBUG3_MBWRITE_FSM_WAI
BNX2_RPM_DEBUG3_MBWRITE_FSM_WAI
BNX2_RPM_DEBUG3_MBWRITE_FSM_WAI
BNX2_RPM_DEBUG3_MBWRITE_FSM_WAI
BNX2_RPM_DEBUG3_MBWRITE_FSM_WAI
BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DR
BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DR
BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_
BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_
BNX2_RPM_DEBUG3_RDE_RBUF_FREE_R
BNX2_RPM_DEBUG3_RDE_RBUF_FREE_R
BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAS
BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAS
BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ
BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ
BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_RE
BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_RE
BNX2_RPM_DEBUG3_RDE_SRC_FIFO_AL
BNX2_RPM_DEBUG3_RDE_SRC_FIFO_AL
BNX2_RPM_DEBUG4
BNX2_RPM_DEBUG4
BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE
BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE
BNX2_RPM_DEBUG4_DFIFO_EMPTY
BNX2_RPM_DEBUG4_DFIFO_EMPTY
BNX2_RPM_DEBUG4_DFSM_MBUF_CLUST
BNX2_RPM_DEBUG4_DFSM_MBUF_CLUST
BNX2_RPM_DEBUG4_MBWRITE_FSM
BNX2_RPM_DEBUG4_MBWRITE_FSM
BNX2_RPM_DEBUG5
BNX2_RPM_DEBUG5
BNX2_RPM_DEBUG5_HOLDREG_ACPI_EM
BNX2_RPM_DEBUG5_HOLDREG_ACPI_EM
BNX2_RPM_DEBUG5_HOLDREG_DISCARD
BNX2_RPM_DEBUG5_HOLDREG_DISCARD
BNX2_RPM_DEBUG5_HOLDREG_FC_EMPT
BNX2_RPM_DEBUG5_HOLDREG_FC_EMPT
BNX2_RPM_DEBUG5_HOLDREG_FULL_T
BNX2_RPM_DEBUG5_HOLDREG_FULL_T
BNX2_RPM_DEBUG5_HOLDREG_MBUF_NO
BNX2_RPM_DEBUG5_HOLDREG_MBUF_NO
BNX2_RPM_DEBUG5_HOLDREG_MC_EMPT
BNX2_RPM_DEBUG5_HOLDREG_MC_EMPT
BNX2_RPM_DEBUG5_HOLDREG_RC_EMPT
BNX2_RPM_DEBUG5_HOLDREG_RC_EMPT
BNX2_RPM_DEBUG5_HOLDREG_RD
BNX2_RPM_DEBUG5_HOLDREG_RD
BNX2_RPM_DEBUG5_HOLDREG_WOL_DRO
BNX2_RPM_DEBUG5_HOLDREG_WOL_DRO
BNX2_RPM_DEBUG5_RDROP_ACPI_EMPT
BNX2_RPM_DEBUG5_RDROP_ACPI_EMPT
BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR
BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR
BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_
BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_
BNX2_RPM_DEBUG5_RDROP_MC_EMPTY
BNX2_RPM_DEBUG5_RDROP_MC_EMPTY
BNX2_RPM_DEBUG5_RDROP_MC_RPTR
BNX2_RPM_DEBUG5_RDROP_MC_RPTR
BNX2_RPM_DEBUG5_RDROP_RC_RPTR
BNX2_RPM_DEBUG5_RDROP_RC_RPTR
BNX2_RPM_DEBUG5_RDROP_WPTR
BNX2_RPM_DEBUG5_RDROP_WPTR
BNX2_RPM_DEBUG6
BNX2_RPM_DEBUG6
BNX2_RPM_DEBUG6_ACPI_VEC
BNX2_RPM_DEBUG6_ACPI_VEC
BNX2_RPM_DEBUG6_VEC
BNX2_RPM_DEBUG6_VEC
BNX2_RPM_DEBUG7
BNX2_RPM_DEBUG7
BNX2_RPM_DEBUG7_RPM_DBG7_LAST_C
BNX2_RPM_DEBUG7_RPM_DBG7_LAST_C
BNX2_RPM_DEBUG8
BNX2_RPM_DEBUG8
BNX2_RPM_DEBUG8_ALL_DONE
BNX2_RPM_DEBUG8_ALL_DONE
BNX2_RPM_DEBUG8_BYTE_CTR
BNX2_RPM_DEBUG8_BYTE_CTR
BNX2_RPM_DEBUG8_COMPARE_AT_SOF_
BNX2_RPM_DEBUG8_COMPARE_AT_SOF_
BNX2_RPM_DEBUG8_COMPARE_AT_SOF_
BNX2_RPM_DEBUG8_COMPARE_AT_SOF_
BNX2_RPM_DEBUG8_COMPARE_AT_SOF_
BNX2_RPM_DEBUG8_COMPARE_AT_SOF_
BNX2_RPM_DEBUG8_COMPARE_AT_W0
BNX2_RPM_DEBUG8_COMPARE_AT_W0
BNX2_RPM_DEBUG8_COMPARE_AT_W3_D
BNX2_RPM_DEBUG8_COMPARE_AT_W3_D
BNX2_RPM_DEBUG8_EOF_DET
BNX2_RPM_DEBUG8_EOF_DET
BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLD
BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLD
BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLD
BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLD
BNX2_RPM_DEBUG8_NXT_EOF_W_12_VL
BNX2_RPM_DEBUG8_NXT_EOF_W_12_VL
BNX2_RPM_DEBUG8_PS_ACPI_FSM
BNX2_RPM_DEBUG8_PS_ACPI_FSM
BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDL
BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDL
BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF
BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF
BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF
BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF
BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF
BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF
BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF
BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF
BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_
BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_
BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_
BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_
BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_
BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_
BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_
BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_
BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_
BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_
BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAI
BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAI
BNX2_RPM_DEBUG8_SOF_DET
BNX2_RPM_DEBUG8_SOF_DET
BNX2_RPM_DEBUG8_THBUF_ADDR
BNX2_RPM_DEBUG8_THBUF_ADDR
BNX2_RPM_DEBUG8_WAIT_4_SOF
BNX2_RPM_DEBUG8_WAIT_4_SOF
BNX2_RPM_DEBUG9
BNX2_RPM_DEBUG9
BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN
BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN
BNX2_RPM_DEBUG9_ACPI_MATCH_INT
BNX2_RPM_DEBUG9_ACPI_MATCH_INT
BNX2_RPM_DEBUG9_INFIFO_OVERRUN_
BNX2_RPM_DEBUG9_INFIFO_OVERRUN_
BNX2_RPM_DEBUG9_OUTFIFO_COUNT
BNX2_RPM_DEBUG9_OUTFIFO_COUNT
BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN
BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN
BNX2_RPM_DEBUG9_RDE_ACPI_RDY
BNX2_RPM_DEBUG9_RDE_ACPI_RDY
BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT
BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT
BNX2_RPM_RC_CNTL_0
BNX2_RPM_RC_CNTL_0
BNX2_RPM_RC_CNTL_0_CLASS
BNX2_RPM_RC_CNTL_0_CLASS
BNX2_RPM_RC_CNTL_0_CMDSEL
BNX2_RPM_RC_CNTL_0_CMDSEL
BNX2_RPM_RC_CNTL_0_COMP
BNX2_RPM_RC_CNTL_0_COMP
BNX2_RPM_RC_CNTL_0_COMP_EQUAL
BNX2_RPM_RC_CNTL_0_COMP_EQUAL
BNX2_RPM_RC_CNTL_0_COMP_GREATER
BNX2_RPM_RC_CNTL_0_COMP_GREATER
BNX2_RPM_RC_CNTL_0_COMP_LESS
BNX2_RPM_RC_CNTL_0_COMP_LESS
BNX2_RPM_RC_CNTL_0_COMP_NEQUAL
BNX2_RPM_RC_CNTL_0_COMP_NEQUAL
BNX2_RPM_RC_CNTL_0_DISCARD
BNX2_RPM_RC_CNTL_0_DISCARD
BNX2_RPM_RC_CNTL_0_HDR_TYPE
BNX2_RPM_RC_CNTL_0_HDR_TYPE
BNX2_RPM_RC_CNTL_0_HDR_TYPE_DAT
BNX2_RPM_RC_CNTL_0_HDR_TYPE_DAT
BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP
BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP
BNX2_RPM_RC_CNTL_0_HDR_TYPE_STA
BNX2_RPM_RC_CNTL_0_HDR_TYPE_STA
BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP
BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP
BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP
BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP
BNX2_RPM_RC_CNTL_0_MAP
BNX2_RPM_RC_CNTL_0_MAP
BNX2_RPM_RC_CNTL_0_MASK
BNX2_RPM_RC_CNTL_0_MASK
BNX2_RPM_RC_CNTL_0_NBIT
BNX2_RPM_RC_CNTL_0_NBIT
BNX2_RPM_RC_CNTL_0_OFFSET
BNX2_RPM_RC_CNTL_0_OFFSET
BNX2_RPM_RC_CNTL_0_P1
BNX2_RPM_RC_CNTL_0_P1
BNX2_RPM_RC_CNTL_0_P2
BNX2_RPM_RC_CNTL_0_P2
BNX2_RPM_RC_CNTL_0_P3
BNX2_RPM_RC_CNTL_0_P3
BNX2_RPM_RC_CNTL_0_P4
BNX2_RPM_RC_CNTL_0_P4
BNX2_RPM_RC_CNTL_0_PRIORITY
BNX2_RPM_RC_CNTL_0_PRIORITY
BNX2_RPM_RC_CNTL_0_SBIT
BNX2_RPM_RC_CNTL_0_SBIT
BNX2_RPM_RC_CNTL_1
BNX2_RPM_RC_CNTL_1
BNX2_RPM_RC_CNTL_1_A
BNX2_RPM_RC_CNTL_1_A
BNX2_RPM_RC_CNTL_1_B
BNX2_RPM_RC_CNTL_1_B
BNX2_RPM_RC_CNTL_10
BNX2_RPM_RC_CNTL_10
BNX2_RPM_RC_CNTL_10_A
BNX2_RPM_RC_CNTL_10_A
BNX2_RPM_RC_CNTL_10_B
BNX2_RPM_RC_CNTL_10_B
BNX2_RPM_RC_CNTL_11
BNX2_RPM_RC_CNTL_11
BNX2_RPM_RC_CNTL_11_A
BNX2_RPM_RC_CNTL_11_A
BNX2_RPM_RC_CNTL_11_B
BNX2_RPM_RC_CNTL_11_B
BNX2_RPM_RC_CNTL_12
BNX2_RPM_RC_CNTL_12
BNX2_RPM_RC_CNTL_12_A
BNX2_RPM_RC_CNTL_12_A
BNX2_RPM_RC_CNTL_12_B
BNX2_RPM_RC_CNTL_12_B
BNX2_RPM_RC_CNTL_13
BNX2_RPM_RC_CNTL_13
BNX2_RPM_RC_CNTL_13_A
BNX2_RPM_RC_CNTL_13_A
BNX2_RPM_RC_CNTL_13_B
BNX2_RPM_RC_CNTL_13_B
BNX2_RPM_RC_CNTL_14
BNX2_RPM_RC_CNTL_14
BNX2_RPM_RC_CNTL_14_A
BNX2_RPM_RC_CNTL_14_A
BNX2_RPM_RC_CNTL_14_B
BNX2_RPM_RC_CNTL_14_B
BNX2_RPM_RC_CNTL_15
BNX2_RPM_RC_CNTL_15
BNX2_RPM_RC_CNTL_15_A
BNX2_RPM_RC_CNTL_15_A
BNX2_RPM_RC_CNTL_15_B
BNX2_RPM_RC_CNTL_15_B
BNX2_RPM_RC_CNTL_2
BNX2_RPM_RC_CNTL_2
BNX2_RPM_RC_CNTL_2_A
BNX2_RPM_RC_CNTL_2_A
BNX2_RPM_RC_CNTL_2_B
BNX2_RPM_RC_CNTL_2_B
BNX2_RPM_RC_CNTL_3
BNX2_RPM_RC_CNTL_3
BNX2_RPM_RC_CNTL_3_A
BNX2_RPM_RC_CNTL_3_A
BNX2_RPM_RC_CNTL_3_B
BNX2_RPM_RC_CNTL_3_B
BNX2_RPM_RC_CNTL_4
BNX2_RPM_RC_CNTL_4
BNX2_RPM_RC_CNTL_4_A
BNX2_RPM_RC_CNTL_4_A
BNX2_RPM_RC_CNTL_4_B
BNX2_RPM_RC_CNTL_4_B
BNX2_RPM_RC_CNTL_5
BNX2_RPM_RC_CNTL_5
BNX2_RPM_RC_CNTL_5_A
BNX2_RPM_RC_CNTL_5_A
BNX2_RPM_RC_CNTL_5_B
BNX2_RPM_RC_CNTL_5_B
BNX2_RPM_RC_CNTL_6
BNX2_RPM_RC_CNTL_6
BNX2_RPM_RC_CNTL_6_A
BNX2_RPM_RC_CNTL_6_A
BNX2_RPM_RC_CNTL_6_B
BNX2_RPM_RC_CNTL_6_B
BNX2_RPM_RC_CNTL_7
BNX2_RPM_RC_CNTL_7
BNX2_RPM_RC_CNTL_7_A
BNX2_RPM_RC_CNTL_7_A
BNX2_RPM_RC_CNTL_7_B
BNX2_RPM_RC_CNTL_7_B
BNX2_RPM_RC_CNTL_8
BNX2_RPM_RC_CNTL_8
BNX2_RPM_RC_CNTL_8_A
BNX2_RPM_RC_CNTL_8_A
BNX2_RPM_RC_CNTL_8_B
BNX2_RPM_RC_CNTL_8_B
BNX2_RPM_RC_CNTL_9
BNX2_RPM_RC_CNTL_9
BNX2_RPM_RC_CNTL_9_A
BNX2_RPM_RC_CNTL_9_A
BNX2_RPM_RC_CNTL_9_B
BNX2_RPM_RC_CNTL_9_B
BNX2_RPM_RC_CONFIG
BNX2_RPM_RC_CONFIG
BNX2_RPM_RC_CONFIG_DEF_CLASS
BNX2_RPM_RC_CONFIG_DEF_CLASS
BNX2_RPM_RC_CONFIG_RULE_ENABLE
BNX2_RPM_RC_CONFIG_RULE_ENABLE
BNX2_RPM_RC_VALUE_MASK_0
BNX2_RPM_RC_VALUE_MASK_0
BNX2_RPM_RC_VALUE_MASK_0_MASK
BNX2_RPM_RC_VALUE_MASK_0_MASK
BNX2_RPM_RC_VALUE_MASK_0_VALUE
BNX2_RPM_RC_VALUE_MASK_0_VALUE
BNX2_RPM_RC_VALUE_MASK_1
BNX2_RPM_RC_VALUE_MASK_1
BNX2_RPM_RC_VALUE_MASK_10
BNX2_RPM_RC_VALUE_MASK_10
BNX2_RPM_RC_VALUE_MASK_11
BNX2_RPM_RC_VALUE_MASK_11
BNX2_RPM_RC_VALUE_MASK_12
BNX2_RPM_RC_VALUE_MASK_12
BNX2_RPM_RC_VALUE_MASK_13
BNX2_RPM_RC_VALUE_MASK_13
BNX2_RPM_RC_VALUE_MASK_14
BNX2_RPM_RC_VALUE_MASK_14
BNX2_RPM_RC_VALUE_MASK_15
BNX2_RPM_RC_VALUE_MASK_15
BNX2_RPM_RC_VALUE_MASK_2
BNX2_RPM_RC_VALUE_MASK_2
BNX2_RPM_RC_VALUE_MASK_3
BNX2_RPM_RC_VALUE_MASK_3
BNX2_RPM_RC_VALUE_MASK_4
BNX2_RPM_RC_VALUE_MASK_4
BNX2_RPM_RC_VALUE_MASK_5
BNX2_RPM_RC_VALUE_MASK_5
BNX2_RPM_RC_VALUE_MASK_6
BNX2_RPM_RC_VALUE_MASK_6
BNX2_RPM_RC_VALUE_MASK_7
BNX2_RPM_RC_VALUE_MASK_7
BNX2_RPM_RC_VALUE_MASK_8
BNX2_RPM_RC_VALUE_MASK_8
BNX2_RPM_RC_VALUE_MASK_9
BNX2_RPM_RC_VALUE_MASK_9
BNX2_RPM_SORT_USER0
BNX2_RPM_SORT_USER0
BNX2_RPM_SORT_USER0_BC_EN
BNX2_RPM_SORT_USER0_BC_EN
BNX2_RPM_SORT_USER0_ENA
BNX2_RPM_SORT_USER0_ENA
BNX2_RPM_SORT_USER0_MC_EN
BNX2_RPM_SORT_USER0_MC_EN
BNX2_RPM_SORT_USER0_MC_HSH_EN
BNX2_RPM_SORT_USER0_MC_HSH_EN
BNX2_RPM_SORT_USER0_PM_EN
BNX2_RPM_SORT_USER0_PM_EN
BNX2_RPM_SORT_USER0_PROM_EN
BNX2_RPM_SORT_USER0_PROM_EN
BNX2_RPM_SORT_USER0_PROM_VLAN
BNX2_RPM_SORT_USER0_PROM_VLAN
BNX2_RPM_SORT_USER0_VLAN_EN
BNX2_RPM_SORT_USER0_VLAN_EN
BNX2_RPM_SORT_USER1
BNX2_RPM_SORT_USER1
BNX2_RPM_SORT_USER1_BC_EN
BNX2_RPM_SORT_USER1_BC_EN
BNX2_RPM_SORT_USER1_ENA
BNX2_RPM_SORT_USER1_ENA
BNX2_RPM_SORT_USER1_MC_EN
BNX2_RPM_SORT_USER1_MC_EN
BNX2_RPM_SORT_USER1_MC_HSH_EN
BNX2_RPM_SORT_USER1_MC_HSH_EN
BNX2_RPM_SORT_USER1_PM_EN
BNX2_RPM_SORT_USER1_PM_EN
BNX2_RPM_SORT_USER1_PROM_EN
BNX2_RPM_SORT_USER1_PROM_EN
BNX2_RPM_SORT_USER1_PROM_VLAN
BNX2_RPM_SORT_USER1_PROM_VLAN
BNX2_RPM_SORT_USER1_VLAN_EN
BNX2_RPM_SORT_USER1_VLAN_EN
BNX2_RPM_SORT_USER2
BNX2_RPM_SORT_USER2
BNX2_RPM_SORT_USER2_BC_EN
BNX2_RPM_SORT_USER2_BC_EN
BNX2_RPM_SORT_USER2_ENA
BNX2_RPM_SORT_USER2_ENA
BNX2_RPM_SORT_USER2_MC_EN
BNX2_RPM_SORT_USER2_MC_EN
BNX2_RPM_SORT_USER2_MC_HSH_EN
BNX2_RPM_SORT_USER2_MC_HSH_EN
BNX2_RPM_SORT_USER2_PM_EN
BNX2_RPM_SORT_USER2_PM_EN
BNX2_RPM_SORT_USER2_PROM_EN
BNX2_RPM_SORT_USER2_PROM_EN
BNX2_RPM_SORT_USER2_PROM_VLAN
BNX2_RPM_SORT_USER2_PROM_VLAN
BNX2_RPM_SORT_USER2_VLAN_EN
BNX2_RPM_SORT_USER2_VLAN_EN
BNX2_RPM_SORT_USER3
BNX2_RPM_SORT_USER3
BNX2_RPM_SORT_USER3_BC_EN
BNX2_RPM_SORT_USER3_BC_EN
BNX2_RPM_SORT_USER3_ENA
BNX2_RPM_SORT_USER3_ENA
BNX2_RPM_SORT_USER3_MC_EN
BNX2_RPM_SORT_USER3_MC_EN
BNX2_RPM_SORT_USER3_MC_HSH_EN
BNX2_RPM_SORT_USER3_MC_HSH_EN
BNX2_RPM_SORT_USER3_PM_EN
BNX2_RPM_SORT_USER3_PM_EN
BNX2_RPM_SORT_USER3_PROM_EN
BNX2_RPM_SORT_USER3_PROM_EN
BNX2_RPM_SORT_USER3_PROM_VLAN
BNX2_RPM_SORT_USER3_PROM_VLAN
BNX2_RPM_SORT_USER3_VLAN_EN
BNX2_RPM_SORT_USER3_VLAN_EN
BNX2_RPM_STAT_AC0
BNX2_RPM_STAT_AC0
BNX2_RPM_STAT_AC1
BNX2_RPM_STAT_AC1
BNX2_RPM_STAT_AC2
BNX2_RPM_STAT_AC2
BNX2_RPM_STAT_AC3
BNX2_RPM_STAT_AC3
BNX2_RPM_STAT_AC4
BNX2_RPM_STAT_AC4
BNX2_RPM_STAT_IFINFTQDISCARDS
BNX2_RPM_STAT_IFINFTQDISCARDS
BNX2_RPM_STAT_IFINMBUFDISCARD
BNX2_RPM_STAT_IFINMBUFDISCARD
BNX2_RPM_STAT_L2_FILTER_DISCARD
BNX2_RPM_STAT_L2_FILTER_DISCARD
BNX2_RPM_STAT_RULE_CHECKER_DISC
BNX2_RPM_STAT_RULE_CHECKER_DISC
BNX2_RPM_STAT_RULE_CHECKER_P4_H
BNX2_RPM_STAT_RULE_CHECKER_P4_H
BNX2_RPM_STATUS
BNX2_RPM_STATUS
BNX2_RPM_STATUS_FREE_WAIT
BNX2_RPM_STATUS_FREE_WAIT
BNX2_RPM_STATUS_MBUF_WAIT
BNX2_RPM_STATUS_MBUF_WAIT
BNX2_RPM_VLAN_MATCH0
BNX2_RPM_VLAN_MATCH0
BNX2_RPM_VLAN_MATCH0_RPM_VLAN_M
BNX2_RPM_VLAN_MATCH0_RPM_VLAN_M
BNX2_RPM_VLAN_MATCH1
BNX2_RPM_VLAN_MATCH1
BNX2_RPM_VLAN_MATCH1_RPM_VLAN_M
BNX2_RPM_VLAN_MATCH1_RPM_VLAN_M
BNX2_RPM_VLAN_MATCH2
BNX2_RPM_VLAN_MATCH2
BNX2_RPM_VLAN_MATCH2_RPM_VLAN_M
BNX2_RPM_VLAN_MATCH2_RPM_VLAN_M
BNX2_RPM_VLAN_MATCH3
BNX2_RPM_VLAN_MATCH3
BNX2_RPM_VLAN_MATCH3_RPM_VLAN_M
BNX2_RPM_VLAN_MATCH3_RPM_VLAN_M
BNX2_RV2P_COMMAND
BNX2_RV2P_COMMAND
BNX2_RV2P_COMMAND_ABORT0
BNX2_RV2P_COMMAND_ABORT0
BNX2_RV2P_COMMAND_ABORT1
BNX2_RV2P_COMMAND_ABORT1
BNX2_RV2P_COMMAND_ABORT2
BNX2_RV2P_COMMAND_ABORT2
BNX2_RV2P_COMMAND_ABORT3
BNX2_RV2P_COMMAND_ABORT3
BNX2_RV2P_COMMAND_ABORT4
BNX2_RV2P_COMMAND_ABORT4
BNX2_RV2P_COMMAND_ABORT5
BNX2_RV2P_COMMAND_ABORT5
BNX2_RV2P_COMMAND_CTXIF_RESET
BNX2_RV2P_COMMAND_CTXIF_RESET
BNX2_RV2P_COMMAND_ENABLED
BNX2_RV2P_COMMAND_ENABLED
BNX2_RV2P_COMMAND_PROC1_INTRPT
BNX2_RV2P_COMMAND_PROC1_INTRPT
BNX2_RV2P_COMMAND_PROC1_RESET
BNX2_RV2P_COMMAND_PROC1_RESET
BNX2_RV2P_COMMAND_PROC2_INTRPT
BNX2_RV2P_COMMAND_PROC2_INTRPT
BNX2_RV2P_COMMAND_PROC2_RESET
BNX2_RV2P_COMMAND_PROC2_RESET
BNX2_RV2P_CONFIG
BNX2_RV2P_CONFIG
BNX2_RV2P_CONFIG_PAGE_SIZE
BNX2_RV2P_CONFIG_PAGE_SIZE
BNX2_RV2P_CONFIG_PAGE_SIZE_128K
BNX2_RV2P_CONFIG_PAGE_SIZE_128K
BNX2_RV2P_CONFIG_PAGE_SIZE_16K
BNX2_RV2P_CONFIG_PAGE_SIZE_16K
BNX2_RV2P_CONFIG_PAGE_SIZE_1K
BNX2_RV2P_CONFIG_PAGE_SIZE_1K
BNX2_RV2P_CONFIG_PAGE_SIZE_1M
BNX2_RV2P_CONFIG_PAGE_SIZE_1M
BNX2_RV2P_CONFIG_PAGE_SIZE_256
BNX2_RV2P_CONFIG_PAGE_SIZE_256
BNX2_RV2P_CONFIG_PAGE_SIZE_256K
BNX2_RV2P_CONFIG_PAGE_SIZE_256K
BNX2_RV2P_CONFIG_PAGE_SIZE_2K
BNX2_RV2P_CONFIG_PAGE_SIZE_2K
BNX2_RV2P_CONFIG_PAGE_SIZE_32K
BNX2_RV2P_CONFIG_PAGE_SIZE_32K
BNX2_RV2P_CONFIG_PAGE_SIZE_4K
BNX2_RV2P_CONFIG_PAGE_SIZE_4K
BNX2_RV2P_CONFIG_PAGE_SIZE_512
BNX2_RV2P_CONFIG_PAGE_SIZE_512
BNX2_RV2P_CONFIG_PAGE_SIZE_512K
BNX2_RV2P_CONFIG_PAGE_SIZE_512K
BNX2_RV2P_CONFIG_PAGE_SIZE_64K
BNX2_RV2P_CONFIG_PAGE_SIZE_64K
BNX2_RV2P_CONFIG_PAGE_SIZE_8K
BNX2_RV2P_CONFIG_PAGE_SIZE_8K
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC1_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_PROC2_STALL_ON
BNX2_RV2P_CONFIG_STALL_PROC1
BNX2_RV2P_CONFIG_STALL_PROC1
BNX2_RV2P_CONFIG_STALL_PROC2
BNX2_RV2P_CONFIG_STALL_PROC2
BNX2_RV2P_DEBUG_VECT_PEEK
BNX2_RV2P_DEBUG_VECT_PEEK
BNX2_RV2P_DEBUG_VECT_PEEK_1_PEE
BNX2_RV2P_DEBUG_VECT_PEEK_1_PEE
BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL
BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL
BNX2_RV2P_DEBUG_VECT_PEEK_1_VAL
BNX2_RV2P_DEBUG_VECT_PEEK_1_VAL
BNX2_RV2P_DEBUG_VECT_PEEK_2_PEE
BNX2_RV2P_DEBUG_VECT_PEEK_2_PEE
BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL
BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL
BNX2_RV2P_DEBUG_VECT_PEEK_2_VAL
BNX2_RV2P_DEBUG_VECT_PEEK_2_VAL
BNX2_RV2P_GEN_BFR_ADDR_0
BNX2_RV2P_GEN_BFR_ADDR_0
BNX2_RV2P_GEN_BFR_ADDR_0_VALUE
BNX2_RV2P_GEN_BFR_ADDR_0_VALUE
BNX2_RV2P_GEN_BFR_ADDR_1
BNX2_RV2P_GEN_BFR_ADDR_1
BNX2_RV2P_GEN_BFR_ADDR_1_VALUE
BNX2_RV2P_GEN_BFR_ADDR_1_VALUE
BNX2_RV2P_GEN_BFR_ADDR_2
BNX2_RV2P_GEN_BFR_ADDR_2
BNX2_RV2P_GEN_BFR_ADDR_2_VALUE
BNX2_RV2P_GEN_BFR_ADDR_2_VALUE
BNX2_RV2P_GEN_BFR_ADDR_3
BNX2_RV2P_GEN_BFR_ADDR_3
BNX2_RV2P_GEN_BFR_ADDR_3_VALUE
BNX2_RV2P_GEN_BFR_ADDR_3_VALUE
BNX2_RV2P_GRC_PROC_DEBUG
BNX2_RV2P_GRC_PROC_DEBUG
BNX2_RV2P_INSTR_HIGH
BNX2_RV2P_INSTR_HIGH
BNX2_RV2P_INSTR_HIGH_HIGH
BNX2_RV2P_INSTR_HIGH_HIGH
BNX2_RV2P_INSTR_LOW
BNX2_RV2P_INSTR_LOW
BNX2_RV2P_MFTQ_CMD
BNX2_RV2P_MFTQ_CMD
BNX2_RV2P_MFTQ_CMD_ADD_DATA
BNX2_RV2P_MFTQ_CMD_ADD_DATA
BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN
BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN
BNX2_RV2P_MFTQ_CMD_BUSY
BNX2_RV2P_MFTQ_CMD_BUSY
BNX2_RV2P_MFTQ_CMD_INTERVENE_CL
BNX2_RV2P_MFTQ_CMD_INTERVENE_CL
BNX2_RV2P_MFTQ_CMD_OFFSET
BNX2_RV2P_MFTQ_CMD_OFFSET
BNX2_RV2P_MFTQ_CMD_POP
BNX2_RV2P_MFTQ_CMD_POP
BNX2_RV2P_MFTQ_CMD_RD_DATA
BNX2_RV2P_MFTQ_CMD_RD_DATA
BNX2_RV2P_MFTQ_CMD_SFT_RESET
BNX2_RV2P_MFTQ_CMD_SFT_RESET
BNX2_RV2P_MFTQ_CMD_WR_TOP
BNX2_RV2P_MFTQ_CMD_WR_TOP
BNX2_RV2P_MFTQ_CMD_WR_TOP_0
BNX2_RV2P_MFTQ_CMD_WR_TOP_0
BNX2_RV2P_MFTQ_CMD_WR_TOP_1
BNX2_RV2P_MFTQ_CMD_WR_TOP_1
BNX2_RV2P_MFTQ_CTL
BNX2_RV2P_MFTQ_CTL
BNX2_RV2P_MFTQ_CTL_CUR_DEPTH
BNX2_RV2P_MFTQ_CTL_CUR_DEPTH
BNX2_RV2P_MFTQ_CTL_FORCE_INTERV
BNX2_RV2P_MFTQ_CTL_FORCE_INTERV
BNX2_RV2P_MFTQ_CTL_INTERVENE
BNX2_RV2P_MFTQ_CTL_INTERVENE
BNX2_RV2P_MFTQ_CTL_MAX_DEPTH
BNX2_RV2P_MFTQ_CTL_MAX_DEPTH
BNX2_RV2P_MFTQ_CTL_OVERFLOW
BNX2_RV2P_MFTQ_CTL_OVERFLOW
BNX2_RV2P_MFTQ_DATA
BNX2_RV2P_MFTQ_DATA
BNX2_RV2P_PFTQ_CMD
BNX2_RV2P_PFTQ_CMD
BNX2_RV2P_PFTQ_CMD_ADD_DATA
BNX2_RV2P_PFTQ_CMD_ADD_DATA
BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN
BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN
BNX2_RV2P_PFTQ_CMD_BUSY
BNX2_RV2P_PFTQ_CMD_BUSY
BNX2_RV2P_PFTQ_CMD_INTERVENE_CL
BNX2_RV2P_PFTQ_CMD_INTERVENE_CL
BNX2_RV2P_PFTQ_CMD_OFFSET
BNX2_RV2P_PFTQ_CMD_OFFSET
BNX2_RV2P_PFTQ_CMD_POP
BNX2_RV2P_PFTQ_CMD_POP
BNX2_RV2P_PFTQ_CMD_RD_DATA
BNX2_RV2P_PFTQ_CMD_RD_DATA
BNX2_RV2P_PFTQ_CMD_SFT_RESET
BNX2_RV2P_PFTQ_CMD_SFT_RESET
BNX2_RV2P_PFTQ_CMD_WR_TOP
BNX2_RV2P_PFTQ_CMD_WR_TOP
BNX2_RV2P_PFTQ_CMD_WR_TOP_0
BNX2_RV2P_PFTQ_CMD_WR_TOP_0
BNX2_RV2P_PFTQ_CMD_WR_TOP_1
BNX2_RV2P_PFTQ_CMD_WR_TOP_1
BNX2_RV2P_PFTQ_CTL
BNX2_RV2P_PFTQ_CTL
BNX2_RV2P_PFTQ_CTL_CUR_DEPTH
BNX2_RV2P_PFTQ_CTL_CUR_DEPTH
BNX2_RV2P_PFTQ_CTL_FORCE_INTERV
BNX2_RV2P_PFTQ_CTL_FORCE_INTERV
BNX2_RV2P_PFTQ_CTL_INTERVENE
BNX2_RV2P_PFTQ_CTL_INTERVENE
BNX2_RV2P_PFTQ_CTL_MAX_DEPTH
BNX2_RV2P_PFTQ_CTL_MAX_DEPTH
BNX2_RV2P_PFTQ_CTL_OVERFLOW
BNX2_RV2P_PFTQ_CTL_OVERFLOW
BNX2_RV2P_PFTQ_DATA
BNX2_RV2P_PFTQ_DATA
BNX2_RV2P_PROC1_ADDR_CMD
BNX2_RV2P_PROC1_ADDR_CMD
BNX2_RV2P_PROC1_ADDR_CMD_ADD
BNX2_RV2P_PROC1_ADDR_CMD_ADD
BNX2_RV2P_PROC1_ADDR_CMD_RDWR
BNX2_RV2P_PROC1_ADDR_CMD_RDWR
BNX2_RV2P_PROC1_GRC_DEBUG
BNX2_RV2P_PROC1_GRC_DEBUG
BNX2_RV2P_PROC2_ADDR_CMD
BNX2_RV2P_PROC2_ADDR_CMD
BNX2_RV2P_PROC2_ADDR_CMD_ADD
BNX2_RV2P_PROC2_ADDR_CMD_ADD
BNX2_RV2P_PROC2_ADDR_CMD_RDWR
BNX2_RV2P_PROC2_ADDR_CMD_RDWR
BNX2_RV2P_PROC2_GRC_DEBUG
BNX2_RV2P_PROC2_GRC_DEBUG
BNX2_RV2P_STATUS
BNX2_RV2P_STATUS
BNX2_RV2P_STATUS_ALWAYS_0
BNX2_RV2P_STATUS_ALWAYS_0
BNX2_RV2P_STATUS_RV2P_GEN_STAT0
BNX2_RV2P_STATUS_RV2P_GEN_STAT0
BNX2_RV2P_STATUS_RV2P_GEN_STAT1
BNX2_RV2P_STATUS_RV2P_GEN_STAT1
BNX2_RV2P_STATUS_RV2P_GEN_STAT2
BNX2_RV2P_STATUS_RV2P_GEN_STAT2
BNX2_RV2P_STATUS_RV2P_GEN_STAT3
BNX2_RV2P_STATUS_RV2P_GEN_STAT3
BNX2_RV2P_STATUS_RV2P_GEN_STAT4
BNX2_RV2P_STATUS_RV2P_GEN_STAT4
BNX2_RV2P_STATUS_RV2P_GEN_STAT5
BNX2_RV2P_STATUS_RV2P_GEN_STAT5
BNX2_RV2P_TFTQ_CMD
BNX2_RV2P_TFTQ_CMD
BNX2_RV2P_TFTQ_CMD_ADD_DATA
BNX2_RV2P_TFTQ_CMD_ADD_DATA
BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN
BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN
BNX2_RV2P_TFTQ_CMD_BUSY
BNX2_RV2P_TFTQ_CMD_BUSY
BNX2_RV2P_TFTQ_CMD_INTERVENE_CL
BNX2_RV2P_TFTQ_CMD_INTERVENE_CL
BNX2_RV2P_TFTQ_CMD_OFFSET
BNX2_RV2P_TFTQ_CMD_OFFSET
BNX2_RV2P_TFTQ_CMD_POP
BNX2_RV2P_TFTQ_CMD_POP
BNX2_RV2P_TFTQ_CMD_RD_DATA
BNX2_RV2P_TFTQ_CMD_RD_DATA
BNX2_RV2P_TFTQ_CMD_SFT_RESET
BNX2_RV2P_TFTQ_CMD_SFT_RESET
BNX2_RV2P_TFTQ_CMD_WR_TOP
BNX2_RV2P_TFTQ_CMD_WR_TOP
BNX2_RV2P_TFTQ_CMD_WR_TOP_0
BNX2_RV2P_TFTQ_CMD_WR_TOP_0
BNX2_RV2P_TFTQ_CMD_WR_TOP_1
BNX2_RV2P_TFTQ_CMD_WR_TOP_1
BNX2_RV2P_TFTQ_CTL
BNX2_RV2P_TFTQ_CTL
BNX2_RV2P_TFTQ_CTL_CUR_DEPTH
BNX2_RV2P_TFTQ_CTL_CUR_DEPTH
BNX2_RV2P_TFTQ_CTL_FORCE_INTERV
BNX2_RV2P_TFTQ_CTL_FORCE_INTERV
BNX2_RV2P_TFTQ_CTL_INTERVENE
BNX2_RV2P_TFTQ_CTL_INTERVENE
BNX2_RV2P_TFTQ_CTL_MAX_DEPTH
BNX2_RV2P_TFTQ_CTL_MAX_DEPTH
BNX2_RV2P_TFTQ_CTL_OVERFLOW
BNX2_RV2P_TFTQ_CTL_OVERFLOW
BNX2_RV2P_TFTQ_DATA
BNX2_RV2P_TFTQ_DATA
BNX2_RXP_CFTQ_CMD
BNX2_RXP_CFTQ_CMD
BNX2_RXP_CFTQ_CMD_ADD_DATA
BNX2_RXP_CFTQ_CMD_ADD_DATA
BNX2_RXP_CFTQ_CMD_ADD_INTERVEN
BNX2_RXP_CFTQ_CMD_ADD_INTERVEN
BNX2_RXP_CFTQ_CMD_BUSY
BNX2_RXP_CFTQ_CMD_BUSY
BNX2_RXP_CFTQ_CMD_INTERVENE_CLR
BNX2_RXP_CFTQ_CMD_INTERVENE_CLR
BNX2_RXP_CFTQ_CMD_OFFSET
BNX2_RXP_CFTQ_CMD_OFFSET
BNX2_RXP_CFTQ_CMD_POP
BNX2_RXP_CFTQ_CMD_POP
BNX2_RXP_CFTQ_CMD_RD_DATA
BNX2_RXP_CFTQ_CMD_RD_DATA
BNX2_RXP_CFTQ_CMD_SFT_RESET
BNX2_RXP_CFTQ_CMD_SFT_RESET
BNX2_RXP_CFTQ_CMD_WR_TOP
BNX2_RXP_CFTQ_CMD_WR_TOP
BNX2_RXP_CFTQ_CMD_WR_TOP_0
BNX2_RXP_CFTQ_CMD_WR_TOP_0
BNX2_RXP_CFTQ_CMD_WR_TOP_1
BNX2_RXP_CFTQ_CMD_WR_TOP_1
BNX2_RXP_CFTQ_CTL
BNX2_RXP_CFTQ_CTL
BNX2_RXP_CFTQ_CTL_CUR_DEPTH
BNX2_RXP_CFTQ_CTL_CUR_DEPTH
BNX2_RXP_CFTQ_CTL_FORCE_INTERVE
BNX2_RXP_CFTQ_CTL_FORCE_INTERVE
BNX2_RXP_CFTQ_CTL_INTERVENE
BNX2_RXP_CFTQ_CTL_INTERVENE
BNX2_RXP_CFTQ_CTL_MAX_DEPTH
BNX2_RXP_CFTQ_CTL_MAX_DEPTH
BNX2_RXP_CFTQ_CTL_OVERFLOW
BNX2_RXP_CFTQ_CTL_OVERFLOW
BNX2_RXP_CFTQ_DATA
BNX2_RXP_CFTQ_DATA
BNX2_RXP_CPU_DATA_ACCESS
BNX2_RXP_CPU_DATA_ACCESS
BNX2_RXP_CPU_DEBUG_VECT_PEEK
BNX2_RXP_CPU_DEBUG_VECT_PEEK
BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_RXP_CPU_EVENT_MASK
BNX2_RXP_CPU_EVENT_MASK
BNX2_RXP_CPU_EVENT_MASK_ALIGN_H
BNX2_RXP_CPU_EVENT_MASK_ALIGN_H
BNX2_RXP_CPU_EVENT_MASK_BAD_DAT
BNX2_RXP_CPU_EVENT_MASK_BAD_DAT
BNX2_RXP_CPU_EVENT_MASK_BAD_INS
BNX2_RXP_CPU_EVENT_MASK_BAD_INS
BNX2_RXP_CPU_EVENT_MASK_BAD_PC_
BNX2_RXP_CPU_EVENT_MASK_BAD_PC_
BNX2_RXP_CPU_EVENT_MASK_BREAKPO
BNX2_RXP_CPU_EVENT_MASK_BREAKPO
BNX2_RXP_CPU_EVENT_MASK_FIO_ABO
BNX2_RXP_CPU_EVENT_MASK_FIO_ABO
BNX2_RXP_CPU_EVENT_MASK_INTERRU
BNX2_RXP_CPU_EVENT_MASK_INTERRU
BNX2_RXP_CPU_EVENT_MASK_PAGE_0_
BNX2_RXP_CPU_EVENT_MASK_PAGE_0_
BNX2_RXP_CPU_EVENT_MASK_PAGE_0_
BNX2_RXP_CPU_EVENT_MASK_PAGE_0_
BNX2_RXP_CPU_EVENT_MASK_SOFT_HA
BNX2_RXP_CPU_EVENT_MASK_SOFT_HA
BNX2_RXP_CPU_EVENT_MASK_SPAD_UN
BNX2_RXP_CPU_EVENT_MASK_SPAD_UN
BNX2_RXP_CPU_HW_BREAKPOINT
BNX2_RXP_CPU_HW_BREAKPOINT
BNX2_RXP_CPU_HW_BREAKPOINT_ADDR
BNX2_RXP_CPU_HW_BREAKPOINT_ADDR
BNX2_RXP_CPU_HW_BREAKPOINT_DISA
BNX2_RXP_CPU_HW_BREAKPOINT_DISA
BNX2_RXP_CPU_INSTRUCTION
BNX2_RXP_CPU_INSTRUCTION
BNX2_RXP_CPU_INTERRUPT_ENABLE
BNX2_RXP_CPU_INTERRUPT_ENABLE
BNX2_RXP_CPU_INTERRUPT_SAVED_PC
BNX2_RXP_CPU_INTERRUPT_SAVED_PC
BNX2_RXP_CPU_INTERRUPT_VECTOR
BNX2_RXP_CPU_INTERRUPT_VECTOR
BNX2_RXP_CPU_LAST_BRANCH_ADDR
BNX2_RXP_CPU_LAST_BRANCH_ADDR
BNX2_RXP_CPU_LAST_BRANCH_ADDR_L
BNX2_RXP_CPU_LAST_BRANCH_ADDR_L
BNX2_RXP_CPU_LAST_BRANCH_ADDR_T
BNX2_RXP_CPU_LAST_BRANCH_ADDR_T
BNX2_RXP_CPU_LAST_BRANCH_ADDR_T
BNX2_RXP_CPU_LAST_BRANCH_ADDR_T
BNX2_RXP_CPU_LAST_BRANCH_ADDR_T
BNX2_RXP_CPU_LAST_BRANCH_ADDR_T
BNX2_RXP_CPU_MODE
BNX2_RXP_CPU_MODE
BNX2_RXP_CPU_MODE_BAD_DATA_HALT
BNX2_RXP_CPU_MODE_BAD_DATA_HALT
BNX2_RXP_CPU_MODE_BAD_INST_HALT
BNX2_RXP_CPU_MODE_BAD_INST_HALT
BNX2_RXP_CPU_MODE_FIO_ABORT_HAL
BNX2_RXP_CPU_MODE_FIO_ABORT_HAL
BNX2_RXP_CPU_MODE_INTERRUPT_ENA
BNX2_RXP_CPU_MODE_INTERRUPT_ENA
BNX2_RXP_CPU_MODE_LOCAL_RST
BNX2_RXP_CPU_MODE_LOCAL_RST
BNX2_RXP_CPU_MODE_MSG_BIT1
BNX2_RXP_CPU_MODE_MSG_BIT1
BNX2_RXP_CPU_MODE_PAGE_0_DATA_E
BNX2_RXP_CPU_MODE_PAGE_0_DATA_E
BNX2_RXP_CPU_MODE_PAGE_0_INST_E
BNX2_RXP_CPU_MODE_PAGE_0_INST_E
BNX2_RXP_CPU_MODE_SOFT_HALT
BNX2_RXP_CPU_MODE_SOFT_HALT
BNX2_RXP_CPU_MODE_SPAD_UNDERFLO
BNX2_RXP_CPU_MODE_SPAD_UNDERFLO
BNX2_RXP_CPU_MODE_STEP_ENA
BNX2_RXP_CPU_MODE_STEP_ENA
BNX2_RXP_CPU_PROGRAM_COUNTER
BNX2_RXP_CPU_PROGRAM_COUNTER
BNX2_RXP_CPU_REG_FILE
BNX2_RXP_CPU_REG_FILE
BNX2_RXP_CPU_STATE
BNX2_RXP_CPU_STATE
BNX2_RXP_CPU_STATE_ALIGN_HALTED
BNX2_RXP_CPU_STATE_ALIGN_HALTED
BNX2_RXP_CPU_STATE_BAD_DATA_ADD
BNX2_RXP_CPU_STATE_BAD_DATA_ADD
BNX2_RXP_CPU_STATE_BAD_INST_HAL
BNX2_RXP_CPU_STATE_BAD_INST_HAL
BNX2_RXP_CPU_STATE_BAD_pc_HALTE
BNX2_RXP_CPU_STATE_BAD_pc_HALTE
BNX2_RXP_CPU_STATE_BLOCKED_READ
BNX2_RXP_CPU_STATE_BLOCKED_READ
BNX2_RXP_CPU_STATE_BREAKPOINT
BNX2_RXP_CPU_STATE_BREAKPOINT
BNX2_RXP_CPU_STATE_DATA_ACCESS_
BNX2_RXP_CPU_STATE_DATA_ACCESS_
BNX2_RXP_CPU_STATE_FIO_ABORT_HA
BNX2_RXP_CPU_STATE_FIO_ABORT_HA
BNX2_RXP_CPU_STATE_INST_FETCH_S
BNX2_RXP_CPU_STATE_INST_FETCH_S
BNX2_RXP_CPU_STATE_INTERRRUPT
BNX2_RXP_CPU_STATE_INTERRRUPT
BNX2_RXP_CPU_STATE_PAGE_0_DATA_
BNX2_RXP_CPU_STATE_PAGE_0_DATA_
BNX2_RXP_CPU_STATE_PAGE_0_INST_
BNX2_RXP_CPU_STATE_PAGE_0_INST_
BNX2_RXP_CPU_STATE_SOFT_HALTED
BNX2_RXP_CPU_STATE_SOFT_HALTED
BNX2_RXP_CPU_STATE_SPAD_UNDERFL
BNX2_RXP_CPU_STATE_SPAD_UNDERFL
BNX2_RXP_FTQ_CMD
BNX2_RXP_FTQ_CMD
BNX2_RXP_FTQ_CMD_ADD_DATA
BNX2_RXP_FTQ_CMD_ADD_DATA
BNX2_RXP_FTQ_CMD_ADD_INTERVEN
BNX2_RXP_FTQ_CMD_ADD_INTERVEN
BNX2_RXP_FTQ_CMD_BUSY
BNX2_RXP_FTQ_CMD_BUSY
BNX2_RXP_FTQ_CMD_INTERVENE_CLR
BNX2_RXP_FTQ_CMD_INTERVENE_CLR
BNX2_RXP_FTQ_CMD_OFFSET
BNX2_RXP_FTQ_CMD_OFFSET
BNX2_RXP_FTQ_CMD_POP
BNX2_RXP_FTQ_CMD_POP
BNX2_RXP_FTQ_CMD_RD_DATA
BNX2_RXP_FTQ_CMD_RD_DATA
BNX2_RXP_FTQ_CMD_SFT_RESET
BNX2_RXP_FTQ_CMD_SFT_RESET
BNX2_RXP_FTQ_CMD_WR_TOP
BNX2_RXP_FTQ_CMD_WR_TOP
BNX2_RXP_FTQ_CMD_WR_TOP_0
BNX2_RXP_FTQ_CMD_WR_TOP_0
BNX2_RXP_FTQ_CMD_WR_TOP_1
BNX2_RXP_FTQ_CMD_WR_TOP_1
BNX2_RXP_FTQ_CTL
BNX2_RXP_FTQ_CTL
BNX2_RXP_FTQ_CTL_CUR_DEPTH
BNX2_RXP_FTQ_CTL_CUR_DEPTH
BNX2_RXP_FTQ_CTL_FORCE_INTERVEN
BNX2_RXP_FTQ_CTL_FORCE_INTERVEN
BNX2_RXP_FTQ_CTL_INTERVENE
BNX2_RXP_FTQ_CTL_INTERVENE
BNX2_RXP_FTQ_CTL_MAX_DEPTH
BNX2_RXP_FTQ_CTL_MAX_DEPTH
BNX2_RXP_FTQ_CTL_OVERFLOW
BNX2_RXP_FTQ_CTL_OVERFLOW
BNX2_RXP_FTQ_DATA
BNX2_RXP_FTQ_DATA
BNX2_RXP_SCRATCH
BNX2_RXP_SCRATCH
bnx2_set_link
bnx2_set_link
bnx2_set_mac_addr
bnx2_set_mac_addr
bnx2_set_mac_link
bnx2_set_mac_link
bnx2_set_power_state_0
bnx2_set_power_state_0
bnx2_set_rx_mode
bnx2_set_rx_mode
bnx2_setup_copper_phy
bnx2_setup_copper_phy
bnx2_setup_phy
bnx2_setup_phy
bnx2_setup_serdes_phy
bnx2_setup_serdes_phy
BNX2_SHARED_FEATURE
BNX2_SHARED_FEATURE
BNX2_SHARED_FEATURE_MASK
BNX2_SHARED_FEATURE_MASK
BNX2_SHARED_HW_CFG
BNX2_SHARED_HW_CFG
BNX2_SHARED_HW_CFG_CONFIG
BNX2_SHARED_HW_CFG_CONFIG
BNX2_SHARED_HW_CFG_CONFIG2
BNX2_SHARED_HW_CFG_CONFIG2
BNX2_SHARED_HW_CFG_DESIGN_LOM
BNX2_SHARED_HW_CFG_DESIGN_LOM
BNX2_SHARED_HW_CFG_DESIGN_NIC
BNX2_SHARED_HW_CFG_DESIGN_NIC
BNX2_SHARED_HW_CFG_LED_MODE_GPH
BNX2_SHARED_HW_CFG_LED_MODE_GPH
BNX2_SHARED_HW_CFG_LED_MODE_GPH
BNX2_SHARED_HW_CFG_LED_MODE_GPH
BNX2_SHARED_HW_CFG_LED_MODE_MAC
BNX2_SHARED_HW_CFG_LED_MODE_MAC
BNX2_SHARED_HW_CFG_LED_MODE_MAS
BNX2_SHARED_HW_CFG_LED_MODE_MAS
BNX2_SHARED_HW_CFG_LED_MODE_SHI
BNX2_SHARED_HW_CFG_LED_MODE_SHI
BNX2_SHARED_HW_CFG_PART_NUM
BNX2_SHARED_HW_CFG_PART_NUM
BNX2_SHARED_HW_CFG_PHY_2_5G
BNX2_SHARED_HW_CFG_PHY_2_5G
BNX2_SHARED_HW_CFG_PHY_BACKPLAN
BNX2_SHARED_HW_CFG_PHY_BACKPLAN
BNX2_SHARED_HW_CFG_PHY_COPPER
BNX2_SHARED_HW_CFG_PHY_COPPER
BNX2_SHARED_HW_CFG_PHY_FIBER
BNX2_SHARED_HW_CFG_PHY_FIBER
BNX2_SHARED_HW_CFG_POWER_DISSIP
BNX2_SHARED_HW_CFG_POWER_DISSIP
BNX2_SHARED_HW_CFG_POWER_STATE_
BNX2_SHARED_HW_CFG_POWER_STATE_
BNX2_SHARED_HW_CFG_POWER_STATE_
BNX2_SHARED_HW_CFG_POWER_STATE_
BNX2_SHARED_HW_CFG_POWER_STATE_
BNX2_SHARED_HW_CFG_POWER_STATE_
BNX2_SHARED_HW_CFG_POWER_STATE_
BNX2_SHARED_HW_CFG_POWER_STATE_
BNX2_SHARED_HW_CFG2_NVM_SIZE_MA
BNX2_SHARED_HW_CFG2_NVM_SIZE_MA
BNX2_SHM_HDR_ADDR_0
BNX2_SHM_HDR_ADDR_0
BNX2_SHM_HDR_ADDR_1
BNX2_SHM_HDR_ADDR_1
BNX2_SHM_HDR_SIGNATURE
BNX2_SHM_HDR_SIGNATURE
BNX2_SHM_HDR_SIGNATURE_SIG
BNX2_SHM_HDR_SIGNATURE_SIG
BNX2_SHM_HDR_SIGNATURE_SIG_MASK
BNX2_SHM_HDR_SIGNATURE_SIG_MASK
BNX2_SHM_HDR_SIGNATURE_VER_MASK
BNX2_SHM_HDR_SIGNATURE_VER_MASK
BNX2_SHM_HDR_SIGNATURE_VER_ONE
BNX2_SHM_HDR_SIGNATURE_VER_ONE
BNX2_TBDR_COMMAND
BNX2_TBDR_COMMAND
BNX2_TBDR_COMMAND_ENABLE
BNX2_TBDR_COMMAND_ENABLE
BNX2_TBDR_COMMAND_MSTR_ABORT
BNX2_TBDR_COMMAND_MSTR_ABORT
BNX2_TBDR_COMMAND_SOFT_RST
BNX2_TBDR_COMMAND_SOFT_RST
BNX2_TBDR_CONFIG
BNX2_TBDR_CONFIG
BNX2_TBDR_CONFIG_CACHE_NEXT_PAG
BNX2_TBDR_CONFIG_CACHE_NEXT_PAG
BNX2_TBDR_CONFIG_MAX_BDS
BNX2_TBDR_CONFIG_MAX_BDS
BNX2_TBDR_CONFIG_PAGE_SIZE
BNX2_TBDR_CONFIG_PAGE_SIZE
BNX2_TBDR_CONFIG_PAGE_SIZE_128K
BNX2_TBDR_CONFIG_PAGE_SIZE_128K
BNX2_TBDR_CONFIG_PAGE_SIZE_16K
BNX2_TBDR_CONFIG_PAGE_SIZE_16K
BNX2_TBDR_CONFIG_PAGE_SIZE_1K
BNX2_TBDR_CONFIG_PAGE_SIZE_1K
BNX2_TBDR_CONFIG_PAGE_SIZE_1M
BNX2_TBDR_CONFIG_PAGE_SIZE_1M
BNX2_TBDR_CONFIG_PAGE_SIZE_256
BNX2_TBDR_CONFIG_PAGE_SIZE_256
BNX2_TBDR_CONFIG_PAGE_SIZE_256K
BNX2_TBDR_CONFIG_PAGE_SIZE_256K
BNX2_TBDR_CONFIG_PAGE_SIZE_2K
BNX2_TBDR_CONFIG_PAGE_SIZE_2K
BNX2_TBDR_CONFIG_PAGE_SIZE_32K
BNX2_TBDR_CONFIG_PAGE_SIZE_32K
BNX2_TBDR_CONFIG_PAGE_SIZE_4K
BNX2_TBDR_CONFIG_PAGE_SIZE_4K
BNX2_TBDR_CONFIG_PAGE_SIZE_512
BNX2_TBDR_CONFIG_PAGE_SIZE_512
BNX2_TBDR_CONFIG_PAGE_SIZE_512K
BNX2_TBDR_CONFIG_PAGE_SIZE_512K
BNX2_TBDR_CONFIG_PAGE_SIZE_64K
BNX2_TBDR_CONFIG_PAGE_SIZE_64K
BNX2_TBDR_CONFIG_PAGE_SIZE_8K
BNX2_TBDR_CONFIG_PAGE_SIZE_8K
BNX2_TBDR_CONFIG_PRIORITY
BNX2_TBDR_CONFIG_PRIORITY
BNX2_TBDR_CONFIG_SWAP_MODE
BNX2_TBDR_CONFIG_SWAP_MODE
BNX2_TBDR_DEBUG_VECT_PEEK
BNX2_TBDR_DEBUG_VECT_PEEK
BNX2_TBDR_DEBUG_VECT_PEEK_1_PEE
BNX2_TBDR_DEBUG_VECT_PEEK_1_PEE
BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL
BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL
BNX2_TBDR_DEBUG_VECT_PEEK_1_VAL
BNX2_TBDR_DEBUG_VECT_PEEK_1_VAL
BNX2_TBDR_DEBUG_VECT_PEEK_2_PEE
BNX2_TBDR_DEBUG_VECT_PEEK_2_PEE
BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL
BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL
BNX2_TBDR_DEBUG_VECT_PEEK_2_VAL
BNX2_TBDR_DEBUG_VECT_PEEK_2_VAL
BNX2_TBDR_FTQ_CMD
BNX2_TBDR_FTQ_CMD
BNX2_TBDR_FTQ_CMD_ADD_DATA
BNX2_TBDR_FTQ_CMD_ADD_DATA
BNX2_TBDR_FTQ_CMD_ADD_INTERVEN
BNX2_TBDR_FTQ_CMD_ADD_INTERVEN
BNX2_TBDR_FTQ_CMD_BUSY
BNX2_TBDR_FTQ_CMD_BUSY
BNX2_TBDR_FTQ_CMD_INTERVENE_CLR
BNX2_TBDR_FTQ_CMD_INTERVENE_CLR
BNX2_TBDR_FTQ_CMD_OFFSET
BNX2_TBDR_FTQ_CMD_OFFSET
BNX2_TBDR_FTQ_CMD_POP
BNX2_TBDR_FTQ_CMD_POP
BNX2_TBDR_FTQ_CMD_RD_DATA
BNX2_TBDR_FTQ_CMD_RD_DATA
BNX2_TBDR_FTQ_CMD_SFT_RESET
BNX2_TBDR_FTQ_CMD_SFT_RESET
BNX2_TBDR_FTQ_CMD_WR_TOP
BNX2_TBDR_FTQ_CMD_WR_TOP
BNX2_TBDR_FTQ_CMD_WR_TOP_0
BNX2_TBDR_FTQ_CMD_WR_TOP_0
BNX2_TBDR_FTQ_CMD_WR_TOP_1
BNX2_TBDR_FTQ_CMD_WR_TOP_1
BNX2_TBDR_FTQ_CTL
BNX2_TBDR_FTQ_CTL
BNX2_TBDR_FTQ_CTL_CUR_DEPTH
BNX2_TBDR_FTQ_CTL_CUR_DEPTH
BNX2_TBDR_FTQ_CTL_FORCE_INTERVE
BNX2_TBDR_FTQ_CTL_FORCE_INTERVE
BNX2_TBDR_FTQ_CTL_INTERVENE
BNX2_TBDR_FTQ_CTL_INTERVENE
BNX2_TBDR_FTQ_CTL_MAX_DEPTH
BNX2_TBDR_FTQ_CTL_MAX_DEPTH
BNX2_TBDR_FTQ_CTL_OVERFLOW
BNX2_TBDR_FTQ_CTL_OVERFLOW
BNX2_TBDR_FTQ_DATA
BNX2_TBDR_FTQ_DATA
BNX2_TBDR_STATUS
BNX2_TBDR_STATUS
BNX2_TBDR_STATUS_BURST_CNT
BNX2_TBDR_STATUS_BURST_CNT
BNX2_TBDR_STATUS_DMA_WAIT
BNX2_TBDR_STATUS_DMA_WAIT
BNX2_TBDR_STATUS_FIFO_OVERFLOW
BNX2_TBDR_STATUS_FIFO_OVERFLOW
BNX2_TBDR_STATUS_FIFO_UNDERFLOW
BNX2_TBDR_STATUS_FIFO_UNDERFLOW
BNX2_TBDR_STATUS_FTQ_ENTRY_CNT
BNX2_TBDR_STATUS_FTQ_ENTRY_CNT
BNX2_TBDR_STATUS_FTQ_WAIT
BNX2_TBDR_STATUS_FTQ_WAIT
BNX2_TBDR_STATUS_SEARCHMISS_ERR
BNX2_TBDR_STATUS_SEARCHMISS_ERR
BNX2_TDMA_COMMAND
BNX2_TDMA_COMMAND
BNX2_TDMA_COMMAND_BAD_L2_LENGTH
BNX2_TDMA_COMMAND_BAD_L2_LENGTH
BNX2_TDMA_COMMAND_ENABLED
BNX2_TDMA_COMMAND_ENABLED
BNX2_TDMA_COMMAND_MASTER_ABORT
BNX2_TDMA_COMMAND_MASTER_ABORT
BNX2_TDMA_CONFIG
BNX2_TDMA_CONFIG
BNX2_TDMA_CONFIG_ALIGN_ENA
BNX2_TDMA_CONFIG_ALIGN_ENA
BNX2_TDMA_CONFIG_CHK_L2_BD
BNX2_TDMA_CONFIG_CHK_L2_BD
BNX2_TDMA_CONFIG_FIFO_CMP
BNX2_TDMA_CONFIG_FIFO_CMP
BNX2_TDMA_CONFIG_LIMIT_SZ
BNX2_TDMA_CONFIG_LIMIT_SZ
BNX2_TDMA_CONFIG_LIMIT_SZ_128
BNX2_TDMA_CONFIG_LIMIT_SZ_128
BNX2_TDMA_CONFIG_LIMIT_SZ_256
BNX2_TDMA_CONFIG_LIMIT_SZ_256
BNX2_TDMA_CONFIG_LIMIT_SZ_512
BNX2_TDMA_CONFIG_LIMIT_SZ_512
BNX2_TDMA_CONFIG_LIMIT_SZ_64
BNX2_TDMA_CONFIG_LIMIT_SZ_64
BNX2_TDMA_CONFIG_LINE_SZ
BNX2_TDMA_CONFIG_LINE_SZ
BNX2_TDMA_CONFIG_LINE_SZ_128
BNX2_TDMA_CONFIG_LINE_SZ_128
BNX2_TDMA_CONFIG_LINE_SZ_256
BNX2_TDMA_CONFIG_LINE_SZ_256
BNX2_TDMA_CONFIG_LINE_SZ_512
BNX2_TDMA_CONFIG_LINE_SZ_512
BNX2_TDMA_CONFIG_LINE_SZ_64
BNX2_TDMA_CONFIG_LINE_SZ_64
BNX2_TDMA_CONFIG_ONE_DMA
BNX2_TDMA_CONFIG_ONE_DMA
BNX2_TDMA_CONFIG_ONE_RECORD
BNX2_TDMA_CONFIG_ONE_RECORD
BNX2_TDMA_DBG_TRIGGER
BNX2_TDMA_DBG_TRIGGER
BNX2_TDMA_DBG_WATCHDOG
BNX2_TDMA_DBG_WATCHDOG
BNX2_TDMA_DMAD_FSM
BNX2_TDMA_DMAD_FSM
BNX2_TDMA_DMAD_FSM_ARB_CTX
BNX2_TDMA_DMAD_FSM_ARB_CTX
BNX2_TDMA_DMAD_FSM_ARB_TBDC
BNX2_TDMA_DMAD_FSM_ARB_TBDC
BNX2_TDMA_DMAD_FSM_BD
BNX2_TDMA_DMAD_FSM_BD
BNX2_TDMA_DMAD_FSM_BD_INVLD
BNX2_TDMA_DMAD_FSM_BD_INVLD
BNX2_TDMA_DMAD_FSM_DMAD
BNX2_TDMA_DMAD_FSM_DMAD
BNX2_TDMA_DMAD_FSM_DR_INTF
BNX2_TDMA_DMAD_FSM_DR_INTF
BNX2_TDMA_DMAD_FSM_PUSH
BNX2_TDMA_DMAD_FSM_PUSH
BNX2_TDMA_DMAD_STATUS
BNX2_TDMA_DMAD_STATUS
BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM
BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM
BNX2_TDMA_DMAD_STATUS_RHOLD_BD_
BNX2_TDMA_DMAD_STATUS_RHOLD_BD_
BNX2_TDMA_DMAD_STATUS_RHOLD_DMA
BNX2_TDMA_DMAD_STATUS_RHOLD_DMA
BNX2_TDMA_DMAD_STATUS_RHOLD_PUS
BNX2_TDMA_DMAD_STATUS_RHOLD_PUS
BNX2_TDMA_DR_INTF_FSM
BNX2_TDMA_DR_INTF_FSM
BNX2_TDMA_DR_INTF_FSM_DMAD
BNX2_TDMA_DR_INTF_FSM_DMAD
BNX2_TDMA_DR_INTF_FSM_DR_BUF
BNX2_TDMA_DR_INTF_FSM_DR_BUF
BNX2_TDMA_DR_INTF_FSM_L2_COMP
BNX2_TDMA_DR_INTF_FSM_L2_COMP
BNX2_TDMA_DR_INTF_FSM_TPATQ
BNX2_TDMA_DR_INTF_FSM_TPATQ
BNX2_TDMA_DR_INTF_FSM_TPBUF
BNX2_TDMA_DR_INTF_FSM_TPBUF
BNX2_TDMA_DR_INTF_STATUS
BNX2_TDMA_DR_INTF_STATUS
BNX2_TDMA_DR_INTF_STATUS_BYTE_C
BNX2_TDMA_DR_INTF_STATUS_BYTE_C
BNX2_TDMA_DR_INTF_STATUS_DATA_A
BNX2_TDMA_DR_INTF_STATUS_DATA_A
BNX2_TDMA_DR_INTF_STATUS_HOLE_P
BNX2_TDMA_DR_INTF_STATUS_HOLE_P
BNX2_TDMA_DR_INTF_STATUS_NXT_PN
BNX2_TDMA_DR_INTF_STATUS_NXT_PN
BNX2_TDMA_DR_INTF_STATUS_SHIFT_
BNX2_TDMA_DR_INTF_STATUS_SHIFT_
BNX2_TDMA_FTQ_CMD
BNX2_TDMA_FTQ_CMD
BNX2_TDMA_FTQ_CMD_ADD_DATA
BNX2_TDMA_FTQ_CMD_ADD_DATA
BNX2_TDMA_FTQ_CMD_ADD_INTERVEN
BNX2_TDMA_FTQ_CMD_ADD_INTERVEN
BNX2_TDMA_FTQ_CMD_BUSY
BNX2_TDMA_FTQ_CMD_BUSY
BNX2_TDMA_FTQ_CMD_INTERVENE_CLR
BNX2_TDMA_FTQ_CMD_INTERVENE_CLR
BNX2_TDMA_FTQ_CMD_OFFSET
BNX2_TDMA_FTQ_CMD_OFFSET
BNX2_TDMA_FTQ_CMD_POP
BNX2_TDMA_FTQ_CMD_POP
BNX2_TDMA_FTQ_CMD_RD_DATA
BNX2_TDMA_FTQ_CMD_RD_DATA
BNX2_TDMA_FTQ_CMD_SFT_RESET
BNX2_TDMA_FTQ_CMD_SFT_RESET
BNX2_TDMA_FTQ_CMD_WR_TOP
BNX2_TDMA_FTQ_CMD_WR_TOP
BNX2_TDMA_FTQ_CMD_WR_TOP_0
BNX2_TDMA_FTQ_CMD_WR_TOP_0
BNX2_TDMA_FTQ_CMD_WR_TOP_1
BNX2_TDMA_FTQ_CMD_WR_TOP_1
BNX2_TDMA_FTQ_CTL
BNX2_TDMA_FTQ_CTL
BNX2_TDMA_FTQ_CTL_CUR_DEPTH
BNX2_TDMA_FTQ_CTL_CUR_DEPTH
BNX2_TDMA_FTQ_CTL_FORCE_INTERVE
BNX2_TDMA_FTQ_CTL_FORCE_INTERVE
BNX2_TDMA_FTQ_CTL_INTERVENE
BNX2_TDMA_FTQ_CTL_INTERVENE
BNX2_TDMA_FTQ_CTL_MAX_DEPTH
BNX2_TDMA_FTQ_CTL_MAX_DEPTH
BNX2_TDMA_FTQ_CTL_OVERFLOW
BNX2_TDMA_FTQ_CTL_OVERFLOW
BNX2_TDMA_FTQ_DATA
BNX2_TDMA_FTQ_DATA
BNX2_TDMA_PAYLOAD_PROD
BNX2_TDMA_PAYLOAD_PROD
BNX2_TDMA_PAYLOAD_PROD_VALUE
BNX2_TDMA_PAYLOAD_PROD_VALUE
BNX2_TDMA_STATUS
BNX2_TDMA_STATUS
BNX2_TDMA_STATUS_BURST_CNT
BNX2_TDMA_STATUS_BURST_CNT
BNX2_TDMA_STATUS_DMA_WAIT
BNX2_TDMA_STATUS_DMA_WAIT
BNX2_TDMA_STATUS_FTQ_ENTRY_CNT
BNX2_TDMA_STATUS_FTQ_ENTRY_CNT
BNX2_TDMA_STATUS_LOCK_WAIT
BNX2_TDMA_STATUS_LOCK_WAIT
BNX2_TDMA_STATUS_PATCH_FTQ_WAIT
BNX2_TDMA_STATUS_PATCH_FTQ_WAIT
BNX2_TDMA_STATUS_PAYLOAD_WAIT
BNX2_TDMA_STATUS_PAYLOAD_WAIT
BNX2_TPAT_CPU_DATA_ACCESS
BNX2_TPAT_CPU_DATA_ACCESS
BNX2_TPAT_CPU_DEBUG_VECT_PEEK
BNX2_TPAT_CPU_DEBUG_VECT_PEEK
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2
BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2
BNX2_TPAT_CPU_EVENT_MASK
BNX2_TPAT_CPU_EVENT_MASK
BNX2_TPAT_CPU_EVENT_MASK_ALIGN_
BNX2_TPAT_CPU_EVENT_MASK_ALIGN_
BNX2_TPAT_CPU_EVENT_MASK_BAD_DA
BNX2_TPAT_CPU_EVENT_MASK_BAD_DA
BNX2_TPAT_CPU_EVENT_MASK_BAD_IN
BNX2_TPAT_CPU_EVENT_MASK_BAD_IN
BNX2_TPAT_CPU_EVENT_MASK_BAD_PC
BNX2_TPAT_CPU_EVENT_MASK_BAD_PC
BNX2_TPAT_CPU_EVENT_MASK_BREAKP
BNX2_TPAT_CPU_EVENT_MASK_BREAKP
BNX2_TPAT_CPU_EVENT_MASK_FIO_AB
BNX2_TPAT_CPU_EVENT_MASK_FIO_AB
BNX2_TPAT_CPU_EVENT_MASK_INTERR
BNX2_TPAT_CPU_EVENT_MASK_INTERR
BNX2_TPAT_CPU_EVENT_MASK_PAGE_0
BNX2_TPAT_CPU_EVENT_MASK_PAGE_0
BNX2_TPAT_CPU_EVENT_MASK_PAGE_0
BNX2_TPAT_CPU_EVENT_MASK_PAGE_0
BNX2_TPAT_CPU_EVENT_MASK_SOFT_H
BNX2_TPAT_CPU_EVENT_MASK_SOFT_H
BNX2_TPAT_CPU_EVENT_MASK_SPAD_U
BNX2_TPAT_CPU_EVENT_MASK_SPAD_U
BNX2_TPAT_CPU_HW_BREAKPOINT
BNX2_TPAT_CPU_HW_BREAKPOINT
BNX2_TPAT_CPU_HW_BREAKPOINT_ADD
BNX2_TPAT_CPU_HW_BREAKPOINT_ADD
BNX2_TPAT_CPU_HW_BREAKPOINT_DIS
BNX2_TPAT_CPU_HW_BREAKPOINT_DIS
BNX2_TPAT_CPU_INSTRUCTION
BNX2_TPAT_CPU_INSTRUCTION
BNX2_TPAT_CPU_INTERRUPT_ENABLE
BNX2_TPAT_CPU_INTERRUPT_ENABLE
BNX2_TPAT_CPU_INTERRUPT_SAVED_P
BNX2_TPAT_CPU_INTERRUPT_SAVED_P
BNX2_TPAT_CPU_INTERRUPT_VECTOR
BNX2_TPAT_CPU_INTERRUPT_VECTOR
BNX2_TPAT_CPU_LAST_BRANCH_ADDR
BNX2_TPAT_CPU_LAST_BRANCH_ADDR
BNX2_TPAT_CPU_LAST_BRANCH_ADDR_
BNX2_TPAT_CPU_LAST_BRANCH_ADDR_
BNX2_TPAT_CPU_LAST_BRANCH_ADDR_
BNX2_TPAT_CPU_LAST_BRANCH_ADDR_
BNX2_TPAT_CPU_LAST_BRANCH_ADDR_
BNX2_TPAT_CPU_LAST_BRANCH_ADDR_
BNX2_TPAT_CPU_LAST_BRANCH_ADDR_
BNX2_TPAT_CPU_LAST_BRANCH_ADDR_
BNX2_TPAT_CPU_MODE
BNX2_TPAT_CPU_MODE
BNX2_TPAT_CPU_MODE_BAD_DATA_HAL
BNX2_TPAT_CPU_MODE_BAD_DATA_HAL
BNX2_TPAT_CPU_MODE_BAD_INST_HAL
BNX2_TPAT_CPU_MODE_BAD_INST_HAL
BNX2_TPAT_CPU_MODE_FIO_ABORT_HA
BNX2_TPAT_CPU_MODE_FIO_ABORT_HA
BNX2_TPAT_CPU_MODE_INTERRUPT_EN
BNX2_TPAT_CPU_MODE_INTERRUPT_EN
BNX2_TPAT_CPU_MODE_LOCAL_RST
BNX2_TPAT_CPU_MODE_LOCAL_RST
BNX2_TPAT_CPU_MODE_MSG_BIT1
BNX2_TPAT_CPU_MODE_MSG_BIT1
BNX2_TPAT_CPU_MODE_PAGE_0_DATA_
BNX2_TPAT_CPU_MODE_PAGE_0_DATA_
BNX2_TPAT_CPU_MODE_PAGE_0_INST_
BNX2_TPAT_CPU_MODE_PAGE_0_INST_
BNX2_TPAT_CPU_MODE_SOFT_HALT
BNX2_TPAT_CPU_MODE_SOFT_HALT
BNX2_TPAT_CPU_MODE_SPAD_UNDERFL
BNX2_TPAT_CPU_MODE_SPAD_UNDERFL
BNX2_TPAT_CPU_MODE_STEP_ENA
BNX2_TPAT_CPU_MODE_STEP_ENA
BNX2_TPAT_CPU_PROGRAM_COUNTER
BNX2_TPAT_CPU_PROGRAM_COUNTER
BNX2_TPAT_CPU_REG_FILE
BNX2_TPAT_CPU_REG_FILE
BNX2_TPAT_CPU_STATE
BNX2_TPAT_CPU_STATE
BNX2_TPAT_CPU_STATE_ALIGN_HALTE
BNX2_TPAT_CPU_STATE_ALIGN_HALTE
BNX2_TPAT_CPU_STATE_BAD_DATA_AD
BNX2_TPAT_CPU_STATE_BAD_DATA_AD
BNX2_TPAT_CPU_STATE_BAD_INST_HA
BNX2_TPAT_CPU_STATE_BAD_INST_HA
BNX2_TPAT_CPU_STATE_BAD_pc_HALT
BNX2_TPAT_CPU_STATE_BAD_pc_HALT
BNX2_TPAT_CPU_STATE_BLOCKED_REA
BNX2_TPAT_CPU_STATE_BLOCKED_REA
BNX2_TPAT_CPU_STATE_BREAKPOINT
BNX2_TPAT_CPU_STATE_BREAKPOINT
BNX2_TPAT_CPU_STATE_DATA_ACCESS
BNX2_TPAT_CPU_STATE_DATA_ACCESS
BNX2_TPAT_CPU_STATE_FIO_ABORT_H
BNX2_TPAT_CPU_STATE_FIO_ABORT_H
BNX2_TPAT_CPU_STATE_INST_FETCH_
BNX2_TPAT_CPU_STATE_INST_FETCH_
BNX2_TPAT_CPU_STATE_INTERRRUPT
BNX2_TPAT_CPU_STATE_INTERRRUPT
BNX2_TPAT_CPU_STATE_PAGE_0_DATA
BNX2_TPAT_CPU_STATE_PAGE_0_DATA
BNX2_TPAT_CPU_STATE_PAGE_0_INST
BNX2_TPAT_CPU_STATE_PAGE_0_INST
BNX2_TPAT_CPU_STATE_SOFT_HALTED
BNX2_TPAT_CPU_STATE_SOFT_HALTED
BNX2_TPAT_CPU_STATE_SPAD_UNDERF
BNX2_TPAT_CPU_STATE_SPAD_UNDERF
BNX2_TPAT_FTQ_CMD
BNX2_TPAT_FTQ_CMD
BNX2_TPAT_FTQ_CMD_ADD_DATA
BNX2_TPAT_FTQ_CMD_ADD_DATA
BNX2_TPAT_FTQ_CMD_ADD_INTERVEN
BNX2_TPAT_FTQ_CMD_ADD_INTERVEN
BNX2_TPAT_FTQ_CMD_BUSY
BNX2_TPAT_FTQ_CMD_BUSY
BNX2_TPAT_FTQ_CMD_INTERVENE_CLR
BNX2_TPAT_FTQ_CMD_INTERVENE_CLR
BNX2_TPAT_FTQ_CMD_OFFSET
BNX2_TPAT_FTQ_CMD_OFFSET
BNX2_TPAT_FTQ_CMD_POP
BNX2_TPAT_FTQ_CMD_POP
BNX2_TPAT_FTQ_CMD_RD_DATA
BNX2_TPAT_FTQ_CMD_RD_DATA
BNX2_TPAT_FTQ_CMD_SFT_RESET
BNX2_TPAT_FTQ_CMD_SFT_RESET
BNX2_TPAT_FTQ_CMD_WR_TOP
BNX2_TPAT_FTQ_CMD_WR_TOP
BNX2_TPAT_FTQ_CMD_WR_TOP_0
BNX2_TPAT_FTQ_CMD_WR_TOP_0
BNX2_TPAT_FTQ_CMD_WR_TOP_1
BNX2_TPAT_FTQ_CMD_WR_TOP_1
BNX2_TPAT_FTQ_CTL
BNX2_TPAT_FTQ_CTL
BNX2_TPAT_FTQ_CTL_CUR_DEPTH
BNX2_TPAT_FTQ_CTL_CUR_DEPTH
BNX2_TPAT_FTQ_CTL_FORCE_INTERVE
BNX2_TPAT_FTQ_CTL_FORCE_INTERVE
BNX2_TPAT_FTQ_CTL_INTERVENE
BNX2_TPAT_FTQ_CTL_INTERVENE
BNX2_TPAT_FTQ_CTL_MAX_DEPTH
BNX2_TPAT_FTQ_CTL_MAX_DEPTH
BNX2_TPAT_FTQ_CTL_OVERFLOW
BNX2_TPAT_FTQ_CTL_OVERFLOW
BNX2_TPAT_FTQ_DATA
BNX2_TPAT_FTQ_DATA
BNX2_TPAT_SCRATCH
BNX2_TPAT_SCRATCH
bnx2_transmit
bnx2_transmit
BNX2_TXP_CPU_DATA_ACCESS
BNX2_TXP_CPU_DATA_ACCESS
BNX2_TXP_CPU_DEBUG_VECT_PEEK
BNX2_TXP_CPU_DEBUG_VECT_PEEK
BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_
BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_
BNX2_TXP_CPU_EVENT_MASK
BNX2_TXP_CPU_EVENT_MASK
BNX2_TXP_CPU_EVENT_MASK_ALIGN_H
BNX2_TXP_CPU_EVENT_MASK_ALIGN_H
BNX2_TXP_CPU_EVENT_MASK_BAD_DAT
BNX2_TXP_CPU_EVENT_MASK_BAD_DAT
BNX2_TXP_CPU_EVENT_MASK_BAD_INS
BNX2_TXP_CPU_EVENT_MASK_BAD_INS
BNX2_TXP_CPU_EVENT_MASK_BAD_PC_
BNX2_TXP_CPU_EVENT_MASK_BAD_PC_
BNX2_TXP_CPU_EVENT_MASK_BREAKPO
BNX2_TXP_CPU_EVENT_MASK_BREAKPO
BNX2_TXP_CPU_EVENT_MASK_FIO_ABO
BNX2_TXP_CPU_EVENT_MASK_FIO_ABO
BNX2_TXP_CPU_EVENT_MASK_INTERRU
BNX2_TXP_CPU_EVENT_MASK_INTERRU
BNX2_TXP_CPU_EVENT_MASK_PAGE_0_
BNX2_TXP_CPU_EVENT_MASK_PAGE_0_
BNX2_TXP_CPU_EVENT_MASK_PAGE_0_
BNX2_TXP_CPU_EVENT_MASK_PAGE_0_
BNX2_TXP_CPU_EVENT_MASK_SOFT_HA
BNX2_TXP_CPU_EVENT_MASK_SOFT_HA
BNX2_TXP_CPU_EVENT_MASK_SPAD_UN
BNX2_TXP_CPU_EVENT_MASK_SPAD_UN
BNX2_TXP_CPU_HW_BREAKPOINT
BNX2_TXP_CPU_HW_BREAKPOINT
BNX2_TXP_CPU_HW_BREAKPOINT_ADDR
BNX2_TXP_CPU_HW_BREAKPOINT_ADDR
BNX2_TXP_CPU_HW_BREAKPOINT_DISA
BNX2_TXP_CPU_HW_BREAKPOINT_DISA
BNX2_TXP_CPU_INSTRUCTION
BNX2_TXP_CPU_INSTRUCTION
BNX2_TXP_CPU_INTERRUPT_ENABLE
BNX2_TXP_CPU_INTERRUPT_ENABLE
BNX2_TXP_CPU_INTERRUPT_SAVED_PC
BNX2_TXP_CPU_INTERRUPT_SAVED_PC
BNX2_TXP_CPU_INTERRUPT_VECTOR
BNX2_TXP_CPU_INTERRUPT_VECTOR
BNX2_TXP_CPU_LAST_BRANCH_ADDR
BNX2_TXP_CPU_LAST_BRANCH_ADDR
BNX2_TXP_CPU_LAST_BRANCH_ADDR_L
BNX2_TXP_CPU_LAST_BRANCH_ADDR_L
BNX2_TXP_CPU_LAST_BRANCH_ADDR_T
BNX2_TXP_CPU_LAST_BRANCH_ADDR_T
BNX2_TXP_CPU_LAST_BRANCH_ADDR_T
BNX2_TXP_CPU_LAST_BRANCH_ADDR_T
BNX2_TXP_CPU_LAST_BRANCH_ADDR_T
BNX2_TXP_CPU_LAST_BRANCH_ADDR_T
BNX2_TXP_CPU_MODE
BNX2_TXP_CPU_MODE
BNX2_TXP_CPU_MODE_BAD_DATA_HALT
BNX2_TXP_CPU_MODE_BAD_DATA_HALT
BNX2_TXP_CPU_MODE_BAD_INST_HALT
BNX2_TXP_CPU_MODE_BAD_INST_HALT
BNX2_TXP_CPU_MODE_FIO_ABORT_HAL
BNX2_TXP_CPU_MODE_FIO_ABORT_HAL
BNX2_TXP_CPU_MODE_INTERRUPT_ENA
BNX2_TXP_CPU_MODE_INTERRUPT_ENA
BNX2_TXP_CPU_MODE_LOCAL_RST
BNX2_TXP_CPU_MODE_LOCAL_RST
BNX2_TXP_CPU_MODE_MSG_BIT1
BNX2_TXP_CPU_MODE_MSG_BIT1
BNX2_TXP_CPU_MODE_PAGE_0_DATA_E
BNX2_TXP_CPU_MODE_PAGE_0_DATA_E
BNX2_TXP_CPU_MODE_PAGE_0_INST_E
BNX2_TXP_CPU_MODE_PAGE_0_INST_E
BNX2_TXP_CPU_MODE_SOFT_HALT
BNX2_TXP_CPU_MODE_SOFT_HALT
BNX2_TXP_CPU_MODE_SPAD_UNDERFLO
BNX2_TXP_CPU_MODE_SPAD_UNDERFLO
BNX2_TXP_CPU_MODE_STEP_ENA
BNX2_TXP_CPU_MODE_STEP_ENA
BNX2_TXP_CPU_PROGRAM_COUNTER
BNX2_TXP_CPU_PROGRAM_COUNTER
BNX2_TXP_CPU_REG_FILE
BNX2_TXP_CPU_REG_FILE
BNX2_TXP_CPU_STATE
BNX2_TXP_CPU_STATE
BNX2_TXP_CPU_STATE_ALIGN_HALTED
BNX2_TXP_CPU_STATE_ALIGN_HALTED
BNX2_TXP_CPU_STATE_BAD_DATA_ADD
BNX2_TXP_CPU_STATE_BAD_DATA_ADD
BNX2_TXP_CPU_STATE_BAD_INST_HAL
BNX2_TXP_CPU_STATE_BAD_INST_HAL
BNX2_TXP_CPU_STATE_BAD_pc_HALTE
BNX2_TXP_CPU_STATE_BAD_pc_HALTE
BNX2_TXP_CPU_STATE_BLOCKED_READ
BNX2_TXP_CPU_STATE_BLOCKED_READ
BNX2_TXP_CPU_STATE_BREAKPOINT
BNX2_TXP_CPU_STATE_BREAKPOINT
BNX2_TXP_CPU_STATE_DATA_ACCESS_
BNX2_TXP_CPU_STATE_DATA_ACCESS_
BNX2_TXP_CPU_STATE_FIO_ABORT_HA
BNX2_TXP_CPU_STATE_FIO_ABORT_HA
BNX2_TXP_CPU_STATE_INST_FETCH_S
BNX2_TXP_CPU_STATE_INST_FETCH_S
BNX2_TXP_CPU_STATE_INTERRRUPT
BNX2_TXP_CPU_STATE_INTERRRUPT
BNX2_TXP_CPU_STATE_PAGE_0_DATA_
BNX2_TXP_CPU_STATE_PAGE_0_DATA_
BNX2_TXP_CPU_STATE_PAGE_0_INST_
BNX2_TXP_CPU_STATE_PAGE_0_INST_
BNX2_TXP_CPU_STATE_SOFT_HALTED
BNX2_TXP_CPU_STATE_SOFT_HALTED
BNX2_TXP_CPU_STATE_SPAD_UNDERFL
BNX2_TXP_CPU_STATE_SPAD_UNDERFL
BNX2_TXP_FTQ_CMD
BNX2_TXP_FTQ_CMD
BNX2_TXP_FTQ_CMD_ADD_DATA
BNX2_TXP_FTQ_CMD_ADD_DATA
BNX2_TXP_FTQ_CMD_ADD_INTERVEN
BNX2_TXP_FTQ_CMD_ADD_INTERVEN
BNX2_TXP_FTQ_CMD_BUSY
BNX2_TXP_FTQ_CMD_BUSY
BNX2_TXP_FTQ_CMD_INTERVENE_CLR
BNX2_TXP_FTQ_CMD_INTERVENE_CLR
BNX2_TXP_FTQ_CMD_OFFSET
BNX2_TXP_FTQ_CMD_OFFSET
BNX2_TXP_FTQ_CMD_POP
BNX2_TXP_FTQ_CMD_POP
BNX2_TXP_FTQ_CMD_RD_DATA
BNX2_TXP_FTQ_CMD_RD_DATA
BNX2_TXP_FTQ_CMD_SFT_RESET
BNX2_TXP_FTQ_CMD_SFT_RESET
BNX2_TXP_FTQ_CMD_WR_TOP
BNX2_TXP_FTQ_CMD_WR_TOP
BNX2_TXP_FTQ_CMD_WR_TOP_0
BNX2_TXP_FTQ_CMD_WR_TOP_0
BNX2_TXP_FTQ_CMD_WR_TOP_1
BNX2_TXP_FTQ_CMD_WR_TOP_1
BNX2_TXP_FTQ_CTL
BNX2_TXP_FTQ_CTL
BNX2_TXP_FTQ_CTL_CUR_DEPTH
BNX2_TXP_FTQ_CTL_CUR_DEPTH
BNX2_TXP_FTQ_CTL_FORCE_INTERVEN
BNX2_TXP_FTQ_CTL_FORCE_INTERVEN
BNX2_TXP_FTQ_CTL_INTERVENE
BNX2_TXP_FTQ_CTL_INTERVENE
BNX2_TXP_FTQ_CTL_MAX_DEPTH
BNX2_TXP_FTQ_CTL_MAX_DEPTH
BNX2_TXP_FTQ_CTL_OVERFLOW
BNX2_TXP_FTQ_CTL_OVERFLOW
BNX2_TXP_FTQ_DATA
BNX2_TXP_FTQ_DATA
BNX2_TXP_SCRATCH
BNX2_TXP_SCRATCH
bnx2_write_phy
bnx2_write_phy
board_found
board_found
board_found
board_found
board_found
board_found
board_found
board_found
BOARD_TYPE(_rev)
BOARD_TYPE(_rev)
bochs.h
bochsbp
BOCHSBP
BOLD
BOLD
boolean_t
boolean_t
boom_rx_desc
boom_rx_desc
boom_tx_desc
boom_tx_desc
BOOT_ARG_PTR_LOCATION
BOOT_ASSUMING_NO_CONFIGURATION_
BOOT_IN_RECOVERY_MODE
boot_infos
boot_next_server_and_filename	Boot using next-server and filename
BOOT_ON_FLASH_UPDATE
BOOT_ON_S2_RESUME
BOOT_ON_S3_RESUME
BOOT_ON_S4_RESUME
BOOT_ON_S5_RESUME
boot_root_path	Boot using root path
boot_text_mapped
BOOT_WITH_DEFAULT_SETTINGS
BOOT_WITH_FULL_CONFIGURATION
BOOT_WITH_FULL_CONFIGURATION_PL
BOOT_WITH_MINIMAL_CONFIGURATION
bootinfo
BOOTINFO_VERSION
bootp.h
BOOTP_BCAST
BOOTP_CLIENT
BOOTP_CLIENT
BOOTP_DHCPVEND
BOOTP_FL_BROADCAST
BOOTP_REP	*< A BOOTP reply packet
BOOTP_REPLY
BOOTP_REPLY
BOOTP_REQ	*< A BOOTP request packet
BOOTP_REQUEST
BOOTP_REQUEST
BOOTP_SERVER
BOOTP_SERVER
bootp_t
BOOTP_VENDOR_LEN
BOOTPC_PORT
bootpd_t
bootph
bootpip_t
BOOTPS_PORT
bootsector.c
bootsector.h
BOOTX_COLORTABLE_SIZE
box	@file
BOXDRAW_DOUBLE_DOWN_HORIZONTAL
BOXDRAW_DOUBLE_DOWN_LEFT
BOXDRAW_DOUBLE_DOWN_RIGHT
BOXDRAW_DOUBLE_HORIZONTAL
BOXDRAW_DOUBLE_UP_HORIZONTAL
BOXDRAW_DOUBLE_UP_LEFT
BOXDRAW_DOUBLE_UP_RIGHT
BOXDRAW_DOUBLE_VERTICAL
BOXDRAW_DOUBLE_VERTICAL_HORIZON
BOXDRAW_DOUBLE_VERTICAL_LEFT
BOXDRAW_DOUBLE_VERTICAL_RIGHT
BOXDRAW_DOWN_DOUBLE_HORIZONTAL
BOXDRAW_DOWN_DOUBLE_LEFT
BOXDRAW_DOWN_DOUBLE_RIGHT
BOXDRAW_DOWN_HORIZONTAL
BOXDRAW_DOWN_HORIZONTAL_DOUBLE
BOXDRAW_DOWN_LEFT
BOXDRAW_DOWN_LEFT_DOUBLE
BOXDRAW_DOWN_RIGHT
BOXDRAW_DOWN_RIGHT_DOUBLE
BOXDRAW_HORIZONTAL
BOXDRAW_UP_DOUBLE_HORIZONTAL
BOXDRAW_UP_DOUBLE_LEFT
BOXDRAW_UP_DOUBLE_RIGHT
BOXDRAW_UP_HORIZONTAL
BOXDRAW_UP_HORIZONTAL_DOUBLE
BOXDRAW_UP_LEFT
BOXDRAW_UP_LEFT_DOUBLE
BOXDRAW_UP_RIGHT
BOXDRAW_UP_RIGHT_DOUBLE
BOXDRAW_VERTICAL
BOXDRAW_VERTICAL_DOUBLE_HORIZON
BOXDRAW_VERTICAL_DOUBLE_LEFT
BOXDRAW_VERTICAL_DOUBLE_RIGHT
BOXDRAW_VERTICAL_HORIZONTAL
BOXDRAW_VERTICAL_HORIZONTAL_DOU
BOXDRAW_VERTICAL_LEFT
BOXDRAW_VERTICAL_LEFT_DOUBLE
BOXDRAW_VERTICAL_RIGHT
BOXDRAW_VERTICAL_RIGHT_DOUBLE
BPCMD_BPDNE
BPCMD_BPDNE
BPCMD_EBPRD
BPCMD_EBPRD
BPCMD_EBPWR
BPCMD_EBPWR
br32
br32
BS	Bank Select
BS	Bank Select
bss
bss
bss
bss
bswap_16(x)
bswap_32(x)
bswap_64(x)
BSWP	Byte SWaP
BSWP	Byte SWaP
btext.c
btext.c
btext.h
btext_clearscreen
btext_clearscreen
btext_drawchar
btext_drawchar
btext_drawhex
btext_drawhex
btext_drawstring
btext_drawstring
btext_flushscreen
btext_flushscreen
btext_init
btext_init
btext_putc
btext_putc
btext_setup_display
btext_setup_display
BUF	BUFfer size (1->32k, 0->64k)
BUF	BUFfer size (1->32k, 0->64k)
BUF_CFG
BUF_CFG
BUF_EVENT
BUF_EVENT
BUFFER_CRC
BUFFER_CRC
BUFFERED_FLASH_BYTE_ADDR_MASK
BUFFERED_FLASH_BYTE_ADDR_MASK
BUFFERED_FLASH_PAGE_BITS
BUFFERED_FLASH_PAGE_BITS
BUFFERED_FLASH_PAGE_SIZE
BUFFERED_FLASH_PAGE_SIZE
BUFFERED_FLASH_PHY_PAGE_SIZE
BUFFERED_FLASH_PHY_PAGE_SIZE
BUFFERED_FLASH_TOTAL_SIZE
BUFFERED_FLASH_TOTAL_SIZE
buffered_line	Retrieve buffered-up line
buffered_line	Retrieve buffered-up line
BUFLEN
BUFLEN
BUFLEN
BUFLEN
BUFMGR_DMA_DESC_POOL_ADDR
BUFMGR_DMA_DESC_POOL_ADDR
BUFMGR_DMA_DESC_POOL_SIZE
BUFMGR_DMA_DESC_POOL_SIZE
BUFMGR_DMA_HIGH_WATER
BUFMGR_DMA_HIGH_WATER
BUFMGR_DMA_LOW_WATER
BUFMGR_DMA_LOW_WATER
BUFMGR_HWDIAG_0
BUFMGR_HWDIAG_0
BUFMGR_HWDIAG_1
BUFMGR_HWDIAG_1
BUFMGR_HWDIAG_2
BUFMGR_HWDIAG_2
BUFMGR_MB_ALLOC_BIT
BUFMGR_MB_ALLOC_BIT
BUFMGR_MB_HIGH_WATER
BUFMGR_MB_HIGH_WATER
BUFMGR_MB_MACRX_LOW_WATER
BUFMGR_MB_MACRX_LOW_WATER
BUFMGR_MB_POOL_ADDR
BUFMGR_MB_POOL_ADDR
BUFMGR_MB_POOL_SIZE
BUFMGR_MB_POOL_SIZE
BUFMGR_MB_RDMA_LOW_WATER
BUFMGR_MB_RDMA_LOW_WATER
BUFMGR_MODE
BUFMGR_MODE
BUFMGR_MODE_ATTN_ENABLE
BUFMGR_MODE_ATTN_ENABLE
BUFMGR_MODE_BM_TEST
BUFMGR_MODE_BM_TEST
BUFMGR_MODE_ENABLE
BUFMGR_MODE_ENABLE
BUFMGR_MODE_MBLOW_ATTN_ENAB
BUFMGR_MODE_MBLOW_ATTN_ENAB
BUFMGR_MODE_RESET
BUFMGR_MODE_RESET
BUFMGR_RX_DMA_ALLOC_REQ
BUFMGR_RX_DMA_ALLOC_REQ
BUFMGR_RX_DMA_ALLOC_RESP
BUFMGR_RX_DMA_ALLOC_RESP
BUFMGR_RX_MB_ALLOC_REQ
BUFMGR_RX_MB_ALLOC_REQ
BUFMGR_RX_MB_ALLOC_RESP
BUFMGR_RX_MB_ALLOC_RESP
BUFMGR_STATUS
BUFMGR_STATUS
BUFMGR_STATUS_ERROR
BUFMGR_STATUS_ERROR
BUFMGR_STATUS_MBLOW
BUFMGR_STATUS_MBLOW
BUFMGR_TX_DMA_ALLOC_REQ
BUFMGR_TX_DMA_ALLOC_REQ
BUFMGR_TX_DMA_ALLOC_RESP
BUFMGR_TX_DMA_ALLOC_RESP
BUFMGR_TX_MB_ALLOC_REQ
BUFMGR_TX_MB_ALLOC_REQ
BUFMGR_TX_MB_ALLOC_RESP
BUFMGR_TX_MB_ALLOC_RESP
BUG()
BUG()
BUG()
BUG()
BUG_ON(condition)
BUG_ON(condition)
BUG_ON(condition)
BUG_ON(condition)
BUILD_ID_STR
BUILD_ID_STR
BUILD_ID_STR
BUILD_ID_STR
BUILD_SERIAL_STR
BUILD_SERIAL_STR
BUILD_SERIAL_STR
BUILD_SERIAL_STR
BUILD_STRING
BUILD_STRING
BUILD_STRING
BUILD_STRING
BUS_CONTROL
BUS_CONTROL
BUS_STATUS
BUS_STATUS
BUS_TYPE_EISA
BUS_TYPE_ISA
BUS_TYPE_ISAPNP
BUS_TYPE_MCA
BUS_TYPE_PCI
bw32
bw32
byBCR0
byBCR0
byBCR1
byBCR1
byCFGA
byCFGA
byCFGB
byCFGB
byCFGC
byCFGC
byCFGD
byCFGD
byCR0
byCR0
byCR1
byCR1
byEECSR
byEECSR
byGPIO
byGPIO
byIMR0
byIMR0
byIMR1
byIMR1
byISR0
byISR0
byISR1
byISR1
byMAR0
byMAR0
byMAR1
byMAR1
byMAR2
byMAR2
byMAR3
byMAR3
byMAR4
byMAR4
byMAR5
byMAR5
byMAR6
byMAR6
byMAR7
byMAR7
byMIIAD
byMIIAD
byMIICR
byMIICR
byMIISR
byMIISR
byMPHY
byMPHY
byPAR0
byPAR0
byPwrcsrClr
byPwrcsrClr
byRCR
byRCR
bySTICKHW
bySTICKHW
byTCR
byTCR
BYTE_REG_BITS_IS_ON(x,p)
BYTE_REG_BITS_IS_ON(x,p)
BYTE_REG_BITS_OFF(x,p)
BYTE_REG_BITS_OFF(x,p)
BYTE_REG_BITS_ON(x,p)
BYTE_REG_BITS_ON(x,p)
BYTE_REG_BITS_SET(x,m,p)
BYTE_REG_BITS_SET(x,m,p)
byTEST
byTEST
byteswap.h
byteswap.h
byteswap.h
byteswap.h
byWOLcgClr
byWOLcgClr
byWOLcrClr
byWOLcrClr
BZI_ASSUMED_RM_SIZE
BZI_BOOT_FLAG
BZI_CAN_USE_HEAP
BZI_CMDLINE_MAGIC
BZI_CMDLINE_OFFSET
BZI_CMDLINE_SIZE
BZI_HDR_OFFSET
BZI_INITRD_MAX
BZI_LOAD_HIGH
BZI_LOAD_HIGH_ADDR
BZI_LOAD_LOW_ADDR
BZI_LOADER_TYPE_ETHERBOOT
BZI_LOADER_TYPE_GPXE
BZI_SIGNATURE
BZI_STACK_SIZE
BZI_VID_MODE_ASK
BZI_VID_MODE_EXT
BZI_VID_MODE_NORMAL
bzimage.c
bzimage.h
bzimage_cmdline
bzimage_context
bzimage_exec	Execute bzImage image
bzimage_header
bzimage_load	Load bzImage image into memory
bzimage_load_initrd	Load initrd
bzimage_load_initrds	Load initrds, if any
bzimage_parse_cmdline	Parse kernel command line for bootloader parameters
bzimage_parse_header	Parse bzImage header
bzimage_set_cmdline	Set command line
bzimage_update_header	Update bzImage header in loaded kernel

C

C	A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 　[Top]

C_CARD_FAILURE
C_CARD_FAILURE
C_CARD_FAILURE
C_CARD_FAILURE
C_INT_RQD
C_INT_RQD
C_INT_RQD
C_INT_RQD
C_INTR_LATCH
C_INTR_LATCH
C_INTR_LATCH
C_INTR_LATCH
C_RX_COMPLETE
C_RX_COMPLETE
C_RX_COMPLETE
C_RX_COMPLETE
C_RX_EARLY
C_RX_EARLY
C_RX_EARLY
C_RX_EARLY
C_TX_AVAIL
C_TX_AVAIL
C_TX_AVAIL
C_TX_AVAIL
C_TX_COMPLETE
C_TX_COMPLETE
C_TX_COMPLETE
C_TX_COMPLETE
C_UPD_STATS
C_UPD_STATS
C_UPD_STATS
C_UPD_STATS
cached_info
calc_base
calc_base
call_bootsector	Jump to preloaded bootsector
CAM_CTRL_BUSY	CAM Busy
CAM_CTRL_BUSY	CAM Busy
CAM_CTRL_ENABLE	CAM Enable
CAM_CTRL_ENABLE	CAM Enable
CAM_CTRL_INDEX_MASK	Index Mask
CAM_CTRL_INDEX_MASK	Index Mask
CAM_CTRL_INDEX_SHIFT
CAM_CTRL_INDEX_SHIFT
CAM_CTRL_MSEL	Mask Select
CAM_CTRL_MSEL	Mask Select
CAM_CTRL_READ	Read
CAM_CTRL_READ	Read
CAM_CTRL_WRITE	Read
CAM_CTRL_WRITE	Read
CAM_DATA_HI_VALID	Valid Bit
CAM_DATA_HI_VALID	Valid Bit
CAMADDR_CAMEN
CAMADDR_CAMEN
CAMADDR_VCAMSL
CAMADDR_VCAMSL
CAMCR_AITR16
CAMCR_AITR16
CAMCR_AITRPKT
CAMCR_AITRPKT
CAMCR_CAMRD
CAMCR_CAMRD
CAMCR_CAMWR
CAMCR_CAMWR
CAMCR_PS_CAM_DATA
CAMCR_PS_CAM_DATA
CAMCR_PS_CAM_MASK
CAMCR_PS_CAM_MASK
CAMCR_PS_MAR
CAMCR_PS_MAR
CAMCR_PS0
CAMCR_PS0
CAMCR_PS1
CAMCR_PS1
can_change_color()
CAPS
CAPS
CAPSULE_FLAGS_PERSIST_ACROSS_RE
CAPSULE_FLAGS_POPULATE_SYSTEM_T
CardBus_NIC	*< CardBus network card
CARRIER_EXTENSION
CARRIER_EXTENSION
CB_ALIGN	Alignment of command blocks
cb_bridge_map
CB_DELAY_LOOP_WAIT	10ms
CB_DELAY_LOOP_WAIT	10ms
CB_INIT_RD_NUM	init # of RD, for setup default
CB_INIT_RD_NUM	init # of RD, for setup default
CB_INIT_RD_NUM_3119	init # of RD, for setup VT3119
CB_INIT_RD_NUM_3119	init # of RD, for setup VT3119
CB_INIT_TD_NUM	init # of TD, for setup default
CB_INIT_TD_NUM	init # of TD, for setup default
CB_INIT_TD_NUM_3119	init # of TD, for setup VT3119
CB_INIT_TD_NUM_3119	init # of TD, for setup VT3119
CB_MAX_RD_NUM	MAX # of RD
CB_MAX_RD_NUM	MAX # of RD
CB_MAX_SEG_PER_PKT	max data seg per packet (Tx)
CB_MAX_SEG_PER_PKT	max data seg per packet (Tx)
CB_MAX_TD_NUM	MAX # of TD
CB_MAX_TD_NUM	MAX # of TD
CB_MAX_TX_ABORT_RETRY
CB_MAX_TX_ABORT_RETRY
CB_RX_BUF_SIZE	max buffer size
CB_RX_BUF_SIZE	max buffer size
CB_TD_RING_NUM	# of TD rings.
CB_TD_RING_NUM	# of TD rings.
cbc.c
cbc.c
cbc.h
CBC_CIPHER( _cbc_name, _cbc_cipher, _raw_cipher, _raw_context, \ _blocksize )
cbc_decrypt	Decrypt data
cbc_decrypt	Decrypt data
cbc_encrypt	Encrypt data
cbc_encrypt	Encrypt data
cbc_xor	@file
cbc_xor	@file
CC_BYE
CC_ERR
CC_GET_FILE
CC_STAT
CCSR
CCSR
CDROM_DEVICE_PATH
ce_loader
CERR	Collision Error
CERR	Collision Error
CF
CFG
CFG
CFG_AUI_SELECT
CFG_AUI_SELECT
CFG_AUTO_1000
CFG_AUTO_1000
CFG_BEM
CFG_BEM
CFG_BROM_DIS
CFG_BROM_DIS
CFG_DATA64_EN
CFG_DATA64_EN
CFG_DUAL_MAC_MSK
CFG_DUAL_MAC_MSK
CFG_DUPSTS
CFG_DUPSTS
CFG_EXD
CFG_EXD
CFG_EXT_125
CFG_EXT_125
CFG_EXTSTS_EN
CFG_EXTSTS_EN
CFG_LED_MODE(x)
CFG_LED_MODE(x)
CFG_LNKSTS
CFG_LNKSTS
CFG_M64ADDR
CFG_M64ADDR
CFG_MODE_1000
CFG_MODE_1000
CFG_MRM_DIS
CFG_MRM_DIS
CFG_MWI_DIS
CFG_MWI_DIS
CFG_PCI64_DET
CFG_PCI64_DET
CFG_PESEL
CFG_PESEL
CFG_PHY_DIS
CFG_PHY_DIS
CFG_PHY_RST
CFG_PHY_RST
CFG_PINT_CTL
CFG_PINT_CTL
CFG_PINT_DUPSTS
CFG_PINT_DUPSTS
CFG_PINT_LNKSTS
CFG_PINT_LNKSTS
CFG_PINT_SPDSTS
CFG_PINT_SPDSTS
CFG_POW
CFG_POW
CFG_REQALG
CFG_REQALG
CFG_RESET_SAVE
CFG_RESET_SAVE
CFG_SB
CFG_SB
CFG_SPDSTS
CFG_SPDSTS
CFG_SPDSTS0
CFG_SPDSTS0
CFG_SPDSTS1
CFG_SPDSTS1
CFG_T64ADDR
CFG_T64ADDR
CFG_TBI_EN
CFG_TBI_EN
CFG_TMRTEST
CFG_TMRTEST
cfg_version
cfg_version
CFGA_ABSHDN
CFGA_ABSHDN
CFGA_AUTO
CFGA_AUTO
CFGA_EELOAD	enable eeprom embeded and direct programming
CFGA_EELOAD	enable eeprom embeded and direct programming
CFGA_GPIO1PD
CFGA_GPIO1PD
CFGA_JUMPER
CFGA_JUMPER
CFGA_MTGPIO
CFGA_MTGPIO
CFGA_PACPI
CFGA_PACPI
CFGA_PMHCTG
CFGA_PMHCTG
CFGA_T10EN
CFGA_T10EN
CFGB_BAKOPT
CFGB_BAKOPT
CFGB_CAP
CFGB_CAP
CFGB_CRANDOM
CFGB_CRANDOM
CFGB_CRSEOPT
CFGB_CRSEOPT
CFGB_GTCKOPT
CFGB_GTCKOPT
CFGB_LNKEN
CFGB_LNKEN
CFGB_MBA
CFGB_MBA
CFGB_MIIOPT
CFGB_MIIOPT
CFGB_OFSET
CFGB_OFSET
CFGB_PD
CFGB_PD
CFGB_POLEN
CFGB_POLEN
CFGC_BPS0	bootrom select[0]
CFGC_BPS0	bootrom select[0]
CFGC_BPS0	bootrom select[0]
CFGC_BPS0	bootrom select[0]
CFGC_BPS1	bootrom select[1]
CFGC_BPS1	bootrom select[1]
CFGC_BPS1	bootrom select[1]
CFGC_BPS1	bootrom select[1]
CFGC_BPS2	bootrom select[2]
CFGC_BPS2	bootrom select[2]
CFGC_BPS2	bootrom select[2]
CFGC_BPS2	bootrom select[2]
CFGC_BROPT
CFGC_BROPT
CFGC_BTSEL
CFGC_BTSEL
CFGC_BTSEL
CFGC_BTSEL
CFGC_DLYEN
CFGC_DLYEN
CFGC_DTSEL
CFGC_DTSEL
CFGC_EELOAD
CFGC_EELOAD
CFGC_M10POL
CFGC_M10POL
CFGC_M10TIO
CFGC_M10TIO
CFGC_PHY0
CFGC_PHY0
CFGC_PHY1
CFGC_PHY1
CFGCS
CFGCS
CFGD_CEREN
CFGD_CEREN
CFGD_CETEN
CFGD_CETEN
CFGD_CFDX
CFGD_CFDX
CFGD_CFGDACEN
CFGD_CFGDACEN
CFGD_DIAG
CFGD_DIAG
CFGD_GPIOEN
CFGD_GPIOEN
CFGD_HTMRL4
CFGD_HTMRL4
CFGD_IODIS
CFGD_IODIS
CFGD_MAGIC
CFGD_MAGIC
CFGD_MSLVDACEN
CFGD_MSLVDACEN
CFGD_PCI64EN
CFGD_PCI64EN
CFGD_RANDOM
CFGD_RANDOM
CHAIN_BIT
CHAIN_BIT
chain_exec	The "chain" command
CHAINED_IRQ
CHANNEL_108A
CHANNEL_108A
CHANNEL_108G
CHANNEL_108G
CHANNEL_2GHZ	2GHz channel.
CHANNEL_2GHZ	2GHz channel.
CHANNEL_5GHZ	5GHz channel
CHANNEL_5GHZ	5GHz channel
CHANNEL_A
CHANNEL_A
CHANNEL_ALL
CHANNEL_ALL
CHANNEL_ALL_NOTURBO
CHANNEL_ALL_NOTURBO
CHANNEL_B
CHANNEL_B
CHANNEL_CCK	CCK channel
CHANNEL_CCK	CCK channel
CHANNEL_CW_INT	Contention Window interference detected
CHANNEL_CW_INT	Contention Window interference detected
CHANNEL_DYN	Dynamic CCK-OFDM channel (for g operation)
CHANNEL_DYN	Dynamic CCK-OFDM channel (for g operation)
CHANNEL_G
CHANNEL_G
CHANNEL_MODES
CHANNEL_MODES
CHANNEL_OFDM	OFDM channel
CHANNEL_OFDM	OFDM channel
CHANNEL_PASSIVE	Only passive scan allowed
CHANNEL_PASSIVE	Only passive scan allowed
CHANNEL_T
CHANNEL_T
CHANNEL_TG
CHANNEL_TG
CHANNEL_TURBO	Turbo Channel
CHANNEL_TURBO	Turbo Channel
CHANNEL_X
CHANNEL_X
CHANNEL_XR	XR channel
CHANNEL_XR	XR channel
CHAOS_TYPE	*< Chaos
chap.c
chap.c
chap.h
chap_finish	Free resources used by a CHAP response
chap_finish	Free resources used by a CHAP response
chap_init	@file
chap_init	@file
chap_respond	Respond to the CHAP challenge
chap_respond	Respond to the CHAP challenge
chap_response
chap_update	Add data to the CHAP challenge
chap_update	Add data to the CHAP challenge
CHAR_256
CHAR_256
CHAR_BACKSPACE
CHAR_BIT
CHAR_BIT
CHAR_CARRIAGE_RETURN
CHAR_HEIGHT
CHAR_LEN	*< "hh" length modifier
CHAR_LEN	*< "hh" length modifier
CHAR_LINEFEED
CHAR_MAX
CHAR_MAX
CHAR_MIN
CHAR_MIN
CHAR_NULL
CHAR_TAB
check
check
check(A)	*< disappears in normal production mode
check(A)	*< disappears in normal production mode
check_connection_type
check_connection_type
check_duplex
check_duplex
check_duplex
check_duplex
CHECK_LINK_TIMES
CHECK_LINK_TIMES
check_region
check_region
CHIP_91100
CHIP_91100
CHIP_91100FD
CHIP_91100FD
CHIP_9190
CHIP_9190
CHIP_9194
CHIP_9194
CHIP_9195
CHIP_9195
CHIP_9196
CHIP_9196
chip_capability_flags
chip_capability_flags
chip_capability_flags
chip_capability_flags
chip_capability_flags
chip_capability_flags
CHIP_EISA_ID_SIG	Product ID Code for Crystal Chip (CS8900 spec 4.3)
CHIP_EISA_ID_SIG	Product ID Code for Crystal Chip (CS8900 spec 4.3)
chip_info
chip_info
CHIP_READ	Used to mark state of the repins code (chip or dma)
CHIP_READ	Used to mark state of the repins code (chip or dma)
chip_type
chip_type
ChipCmdBits
ChipCmdBits
ChipCmdBits
ChipCmdBits
ChipConfig_bits
ChipConfig_bits
CHIPGCR_FCFDX
CHIPGCR_FCFDX
CHIPGCR_FCGMII
CHIPGCR_FCGMII
CHIPGCR_FCMODE
CHIPGCR_FCMODE
CHIPGCR_FCRESV
CHIPGCR_FCRESV
CHIPGCR_LPSOPT
CHIPGCR_LPSOPT
CHIPGCR_PHYINTEN
CHIPGCR_PHYINTEN
CHIPGCR_TM0US
CHIPGCR_TM0US
CHIPGCR_TM1US
CHIPGCR_TM1US
CHIPID	Chip ID regsiter
CHIPID	Chip ID regsiter
CHIPREV_5700_AX
CHIPREV_5700_AX
CHIPREV_5700_BX
CHIPREV_5700_BX
CHIPREV_5700_CX
CHIPREV_5700_CX
CHIPREV_5701_AX
CHIPREV_5701_AX
CHIPREV_ID_5700_A0
CHIPREV_ID_5700_A0
CHIPREV_ID_5700_A1
CHIPREV_ID_5700_A1
CHIPREV_ID_5700_ALTIMA
CHIPREV_ID_5700_ALTIMA
CHIPREV_ID_5700_B0
CHIPREV_ID_5700_B0
CHIPREV_ID_5700_B1
CHIPREV_ID_5700_B1
CHIPREV_ID_5700_B3
CHIPREV_ID_5700_B3
CHIPREV_ID_5700_C0
CHIPREV_ID_5700_C0
CHIPREV_ID_5701_A0
CHIPREV_ID_5701_A0
CHIPREV_ID_5701_B0
CHIPREV_ID_5701_B0
CHIPREV_ID_5701_B2
CHIPREV_ID_5701_B2
CHIPREV_ID_5701_B5
CHIPREV_ID_5701_B5
CHIPREV_ID_5703_A0
CHIPREV_ID_5703_A0
CHIPREV_ID_5703_A1
CHIPREV_ID_5703_A1
CHIPREV_ID_5703_A2
CHIPREV_ID_5703_A2
CHIPREV_ID_5703_A3
CHIPREV_ID_5703_A3
CHIPREV_ID_5704_A0
CHIPREV_ID_5704_A0
CHIPREV_ID_5704_A1
CHIPREV_ID_5704_A1
CHIPREV_ID_5704_A2
CHIPREV_ID_5704_A2
CHIPREV_ID_5705_A0
CHIPREV_ID_5705_A0
CHIPREV_ID_5705_A1
CHIPREV_ID_5705_A1
CHIPREV_ID_5705_A2
CHIPREV_ID_5705_A2
CHIPREV_ID_5705_A3
CHIPREV_ID_5705_A3
CHIPREV_ID_5721
CHIPREV_ID_5721
CHIPREV_ID_5750_A0
CHIPREV_ID_5750_A0
CHIPREV_ID_5750_A1
CHIPREV_ID_5750_A1
CHIPREV_ID_5750_A3
CHIPREV_ID_5750_A3
CHK_IO_SIZE(pci_dev, dev_rev)
CHK_IO_SIZE(pci_dev, dev_rev)
CHKSUM_LEN
CHKSUM_LEN
CHKSUM_VAL
CHKSUM_VAL
churi	Change working URI
churi	Change working URI
CHURN_DETECTION_TIME
CHURN_DETECTION_TIME
cipher_algorithm
cipher_algorithm raw_cipher, void cbc_ctx __unused )
cipher_decrypt( cipher, ctx, src, dst, len )
cipher_encrypt( cipher, ctx, src, dst, len )
cipher_null_decrypt
cipher_null_decrypt
cipher_null_encrypt
cipher_null_encrypt
cipher_null_setiv
cipher_null_setiv
cipher_null_setkey
cipher_null_setkey
CIRC_INC( a, b )
CIRC_INC( a, b )
cirrus_state_t
cirrus_state_t
CIS_STEP
CIS_STEP
CISTPL_END
CISTPL_END
CISTPL_HEADER_LEN
CISTPL_HEADER_LEN
CISTPL_LEN_OFF
CISTPL_LEN_OFF
CISTPL_VERS_1
CISTPL_VERS_1
CISTPL_VERS_1_STR_OFF
CISTPL_VERS_1_STR_OFF
clear.c
clear_b0_fpga_memories
clear_b0_fpga_memories
clear_exec
clear_exec
clear_settings	Clear settings block
clear_settings	Clear settings block
clearmsg	Clear message on specified row
CLK312_EN_LBN
CLK312_EN_LBN
CLK312_EN_WIDTH
CLK312_EN_WIDTH
CLOCK_CTRL_44MHZ_CORE
CLOCK_CTRL_44MHZ_CORE
CLOCK_CTRL_625_CORE
CLOCK_CTRL_625_CORE
CLOCK_CTRL_ALTCLK
CLOCK_CTRL_ALTCLK
CLOCK_CTRL_CLKRUN_OENABLE
CLOCK_CTRL_CLKRUN_OENABLE
CLOCK_CTRL_CORECLK_DISABLE
CLOCK_CTRL_CORECLK_DISABLE
CLOCK_CTRL_DELAY_PCI_GRANT
CLOCK_CTRL_DELAY_PCI_GRANT
CLOCK_CTRL_FORCE_CLKRUN
CLOCK_CTRL_FORCE_CLKRUN
CLOCK_CTRL_PWRDOWN_PLL133
CLOCK_CTRL_PWRDOWN_PLL133
CLOCK_CTRL_RXCLK_DISABLE
CLOCK_CTRL_RXCLK_DISABLE
CLOCK_CTRL_TXCLK_DISABLE
CLOCK_CTRL_TXCLK_DISABLE
close	Close file
close	Close file
close_all_netdevs	Close all open net devices
close_listener	Close listener socket
clrline	Activate all of the available media and probe for network
clrline	Activate all of the available media and probe for network
cmapsz
cmapsz
cmapsz
cmapsz
cmd_line
CMD0	Command0 register
CMD0	Command0 register
CMD0_BITS
CMD0_BITS
CMD2	Command2 register
CMD2	Command2 register
CMD2_BITS
CMD2_BITS
CMD3	Command3 resiter
CMD3	Command3 resiter
CMD3_BITS
CMD3_BITS
CMD7	Command7 register
CMD7	Command7 register
CMD7_BITS
CMD7_BITS
cmdif_go_bit	Mtnic commands functions
cmdif_go_bit	Mtnic commands functions
CMDL_BUFFER_SIZE
CMDL_MAX_TAB_COMPLETE_RESULT
cmdl_param_list
CMDL_PROMPT_SIZE
cmdline.h
cmdlinelib.h
cmdlist.h
CMDSTS_DEST_MASK
CMDSTS_DEST_MASK
CMDSTS_DEST_MULTI
CMDSTS_DEST_MULTI
CMDSTS_DEST_SELF
CMDSTS_DEST_SELF
CMDSTS_ERR
CMDSTS_ERR
CMDSTS_INTR
CMDSTS_INTR
CMDSTS_LEN_MASK
CMDSTS_LEN_MASK
CMDSTS_MORE
CMDSTS_MORE
CMDSTS_OK
CMDSTS_OK
CMDSTS_OWN
CMDSTS_OWN
code_match
code_prefix_ss11
code_run
CODE_STATUS
CODE_STATUS
CODE_VERSION
CODE_VERSION
code32
CODEVIEW_SIGNATURE_NB10
CODEVIEW_SIGNATURE_RSDS
coff.h
COFF_filehdr
COFF_opthdr
COFF_scnhdr
COLL	Force Collision
COLL	Force Collision
COLOR_BG
COLOR_BLACK
COLOR_BLUE
color_content( c, r, g, b )
COLOR_CYAN
COLOR_FG
COLOR_GREEN
COLOR_MAGENTA
COLOR_PAIR(n)
COLOR_PAIRS
COLOR_RED
color_set( cpno, opts )
COLOR_WHITE
COLOR_YELLOW
COLORS
colour.c
COLOUR_BG
COLOUR_BLACK
COLOUR_BLUE
colour_content	Identify the RGB components of a given colour value
COLOUR_CYAN
COLOUR_FG
COLOUR_GREEN
COLOUR_MAGENTA
colour_pair
COLOUR_PAIR(n)
COLOUR_PAIRS	Arbitrary limit
COLOUR_RED
COLOUR_WHITE
COLOUR_YELLOW
COLOURS
COLS
COLS
COM1
COM1
COM2
COM2
COM3
COM3
com32.c
COM32_BOUNCE_SEG
com32_call.c
com32_cfarcall	CDECL farcall helper
com32_exec	Execute COMBOOT image
com32_external_esp
com32_farcall	Farcall helper
com32_farcall_proc
com32_identify	Check image name extension
com32_int_vector
com32_intcall	Interrupt call helper
com32_load	Load COM32 image into memory
com32_reg32_t
com32_regs
COM32_START_PHYS
com32sys_t
COM4
COM4
comboot.c
comboot.h
comboot_call.c
comboot_copy_cmdline	Copy command line to PSP
comboot_exec	Execute COMBOOT image
COMBOOT_EXIT
COMBOOT_EXIT_COMMAND
COMBOOT_EXIT_RUN_KERNEL
comboot_feature_flags
COMBOOT_FEATURE_IDLE_LOOP
COMBOOT_FEATURE_LOCAL_BOOT
comboot_fetch_kernel	Fetch kernel and optional initrd
COMBOOT_FILE_BLOCKSZ
comboot_force_text_mode	Set default text mode
comboot_identify	Check image name extension
comboot_init_psp	Initialize PSP
comboot_initial_regs
comboot_load	Load COMBOOT image into memory
comboot_load_image	Load COM32 image into memory
COMBOOT_MAX_CMDLINE_LEN
COMBOOT_MAX_SHUFFLE_DESCRIPTORS
comboot_prepare_bounce_buffer	Prepare COM32 low memory bounce buffer
comboot_prepare_segment	Load COMBOOT image into memory, preparing a segment and returning it
comboot_psp
COMBOOT_PSP_CMDLINE_OFFSET
COMBOOT_PSP_SEG
comboot_resolv
comboot_resolv.c
comboot_resolv_done
comboot_return
comboot_shuffle_descriptor
COMBOOT_VIDEO_GRAPHICS
COMBOOT_VIDEO_NONSTANDARD
COMBOOT_VIDEO_NOTEXT
COMBOOT_VIDEO_VESA
COMBRD
COMBRD
COMCONSOLE	I/O port address
COMCONSOLE
COMCONSOLE	I/O port address
COMCONSOLE
COMDATA	Data bits
COMDATA
COMDATA	Data bits
COMDATA
command
command.h
COMMAND_BUSM
COMMAND_BUSM
COMMAND_REG	Register 0
COMMAND_REG	Register 0
COMMAND_WAIT
COMMAND_WAIT
commands
Commands
Commands
COMMANDS
COMP_BIG_MSB
COMP_BIG_MSB	*< (Max dbl comp + 1)/ 2
COMP_BIG_MSB
COMP_BIG_MSB	*< (Max dbl comp + 1)/ 2
COMP_BIT_SIZE	*< Number of bits in a component.
COMP_BIT_SIZE	*< Number of bits in a component.
COMP_BYTE_SIZE	*< Number of bytes in a component.
COMP_BYTE_SIZE	*< Number of bytes in a component.
comp_left_shift	Take each component and shift it up (in terms of components)
comp_left_shift	Take each component and shift it up (in terms of components)
comp_mod
comp_mod
COMP_NUM_NIBBLES	*< Used For diagnostics only.
COMP_NUM_NIBBLES	*< Used For diagnostics only.
COMP_RADIX
COMP_RADIX	*< Max component + 1
COMP_RADIX
COMP_RADIX	*< Max component + 1
COMPARITY	Parity: 0=None, 1=Odd, 2=Even
COMPARITY
COMPARITY	Parity: 0=None, 1=Odd, 2=Even
COMPARITY
COMPEX_RL2000_TRIES
COMPEX_RL2000_TRIES
compiler.h
compiler.h
compiler.h
compiler.h
ComponentName2.h
COMSPEED	Baud rate
COMSPEED
COMSPEED	Baud rate
COMSPEED
COMSTOP	Stop bits
COMSTOP
COMSTOP	Stop bits
COMSTOP
ConfCmd
CONFIG
CONFIG
config.c
config.c
CONFIG_BIGINT_CLASSICAL
CONFIG_BIGINT_CLASSICAL
config_cmd.c
config_cmd.c
CONFIG_DEFAULTS(_platform)
CONFIG_DEFAULTS(_platform)
config_exec
config_exec
config_net80211.c
CONFIG_NETLINK
CONFIG_NETLINK
config_romprefix.c
CONFIG_SSL_CERT_VERIFICATION
CONFIG_SSL_CERT_VERIFICATION
CONFIG_SSL_ENABLE_CLIENT
CONFIG_SSL_ENABLE_CLIENT
CONFIG_SSL_EXPIRY_TIME
CONFIG_SSL_EXPIRY_TIME
CONFIG_SSL_MAX_CERTS
CONFIG_SSL_MAX_CERTS
CONFIG_X509_MAX_CA_CERTS
CONFIG_X509_MAX_CA_CERTS
Config1Bits
Config1Bits
CONGENB	Enable congestion control in the DP83840.
connector	for 3C509
connector	for 3C509
connector_entry
connector_entry
console.c
console.c
console.h
console.h
console.h
console_driver
CONSOLES
CONST
container_of(ptr, type, member)
CONTROL
CONTROL
CONTROL
CONTROL
control_dc_dc
control_dc_dc
CONTROLLER_DEVICE_PATH
copy_encap_settings	@file
copy_from_real
copy_settings	Copy settings to DHCP packet
copy_to_real
copy_user_to_rm_stack	Allocate space on the real-mode stack and copy data there from a
COR_OFFSET	COR attribute offset of Prism2 PC card
COR_OFFSET	COR attribute offset of Prism2 PC card
COR_VALUE	Enable PC card with irq in level trigger (but interrupts disabled)
COR_VALUE	Enable PC card with irq in level trigger (but interrupts disabled)
CORKSCREW
CORKSCREW
corkscrew_cmd
corkscrew_cmd
corkscrew_found_device
corkscrew_found_device
CORKSCREW_ID
CORKSCREW_ID
corkscrew_private
corkscrew_private
corkscrew_probe1
corkscrew_probe1
corkscrew_status
corkscrew_status
COUNTER
COUNTER
CPAIR_ALERT
CPAIR_EDIT
CPAIR_EDITBOX
CPAIR_LABEL
CPAIR_NORMAL
CPAIR_NORMAL
CPAIR_NORMAL
CPAIR_SELECT
CPAIR_SELECT
CPAIR_SHIFT
cpio.c
cpio.c
cpio.h
cpio_header
CPIO_MAGIC
cpio_set_field	Set field within a CPIO header
cpio_set_field	Set field within a CPIO header
cpu.c
cpu.h
cpu.h
Cpu.h
CPU_EVTMASK
CPU_EVTMASK
CPU_HW_BP
CPU_HW_BP
CPU_INSN
CPU_INSN
CPU_LAST_BRANCH_ADDR
CPU_LAST_BRANCH_ADDR
CPU_MODE
CPU_MODE
CPU_MODE_HALT
CPU_MODE_HALT
CPU_MODE_RESET
CPU_MODE_RESET
CPU_PC
CPU_PC
CPU_R0
CPU_R0
CPU_R1
CPU_R1
CPU_R10
CPU_R10
CPU_R11
CPU_R11
CPU_R12
CPU_R12
CPU_R13
CPU_R13
CPU_R14
CPU_R14
CPU_R15
CPU_R15
CPU_R16
CPU_R16
CPU_R17
CPU_R17
CPU_R18
CPU_R18
CPU_R19
CPU_R19
CPU_R2
CPU_R2
CPU_R20
CPU_R20
CPU_R21
CPU_R21
CPU_R22
CPU_R22
CPU_R23
CPU_R23
CPU_R24
CPU_R24
CPU_R25
CPU_R25
CPU_R26
CPU_R26
CPU_R27
CPU_R27
CPU_R28
CPU_R28
CPU_R29
CPU_R29
CPU_R3
CPU_R3
CPU_R30
CPU_R30
CPU_R31
CPU_R31
CPU_R4
CPU_R4
CPU_R5
CPU_R5
CPU_R6
CPU_R6
CPU_R7
CPU_R7
CPU_R8
CPU_R8
CPU_R9
CPU_R9
cpu_reg
cpu_reg
CPU_SPAD_UFLOW
CPU_SPAD_UFLOW
CPU_SPAD_UFLOW_SET
CPU_SPAD_UFLOW_SET
CPU_STACK_ALIGNMENT
CPU_STACK_ALIGNMENT
CPU_STATE
CPU_STATE
cpu_to_be16(x)
cpu_to_be16(x)
cpu_to_be16s(x)
cpu_to_be16s(x)
cpu_to_be32(x)
cpu_to_be32(x)
cpu_to_be32s(x)
cpu_to_be32s(x)
cpu_to_be64(x)
cpu_to_be64(x)
cpu_to_be64s(x)
cpu_to_be64s(x)
cpu_to_BIT32
cpu_to_BIT32
cpu_to_BIT64
cpu_to_BIT64
cpu_to_le16(x)
cpu_to_le16(x)
cpu_to_le16s(x)
cpu_to_le16s(x)
cpu_to_le32(x)
cpu_to_le32(x)
cpu_to_le32_array
cpu_to_le32_array
cpu_to_le32s(x)
cpu_to_le32s(x)
cpu_to_le64(x)
cpu_to_le64(x)
cpu_to_le64s(x)
cpu_to_le64s(x)
CPU_WDOG_CLEAR
CPU_WDOG_CLEAR
CPU_WDOG_PC
CPU_WDOG_PC
CPU_WDOG_SAVED_STATE
CPU_WDOG_SAVED_STATE
CPU_WDOG_VECTOR
CPU_WDOG_VECTOR
cpuinfo_x86
CpuIo.h
cputchar	Print character via a printf context
cputchar	Print character via a printf context
CR
CR
CR
CR_1000T_ASYM_PAUSE	Advertise asymmetric pause bit
CR_1000T_ASYM_PAUSE	Advertise asymmetric pause bit
CR_1000T_FD_CAPS	Advertise 1000T FD capability
CR_1000T_FD_CAPS	Advertise 1000T FD capability
CR_1000T_HD_CAPS	Advertise 1000T HD capability
CR_1000T_HD_CAPS	Advertise 1000T HD capability
CR_1000T_MS_ENABLE	1=Master/Slave manual config value
CR_1000T_MS_ENABLE	1=Master/Slave manual config value
CR_1000T_MS_VALUE	1=Configure PHY as Master
CR_1000T_MS_VALUE	1=Configure PHY as Master
CR_1000T_REPEATER_DTE	1=Repeater/switch device port
CR_1000T_REPEATER_DTE	1=Repeater/switch device port
CR_1000T_TEST_MODE_1	Transmit Waveform test
CR_1000T_TEST_MODE_1	Transmit Waveform test
CR_1000T_TEST_MODE_2	Master Transmit Jitter test
CR_1000T_TEST_MODE_2	Master Transmit Jitter test
CR_1000T_TEST_MODE_3	Slave Transmit Jitter test
CR_1000T_TEST_MODE_3	Slave Transmit Jitter test
CR_1000T_TEST_MODE_4	Transmitter Distortion test
CR_1000T_TEST_MODE_4	Transmitter Distortion test
CR_1000T_TEST_MODE_NORMAL	Normal Operation
CR_1000T_TEST_MODE_NORMAL	Normal Operation
CR_DPOLL	disable rx/tx auto polling
CR_DPOLL	disable rx/tx auto polling
CR_EREN	early rx mode
CR_EREN	early rx mode
CR_ETEN	early tx mode
CR_ETEN	early tx mode
CR_FDX	full duplex mode
CR_FDX	full duplex mode
CR_INIT	start init process
CR_INIT	start init process
CR_KEYPAG	turn on par/key
CR_KEYPAG	turn on par/key
CR_NEXTFRAME
CR_NEXTFRAME
CR_QUEUE_RX
CR_QUEUE_RX
CR_QUEUE_TX
CR_QUEUE_TX
CR_RDMD	rx descriptor polling demand
CR_RDMD	rx descriptor polling demand
CR_RDMD1	RDMD1
CR_RDMD1	RDMD1
CR_RST
CR_RST
CR_RXD
CR_RXD
CR_RXE
CR_RXE
CR_RXON
CR_RXON
CR_RXR
CR_RXR
CR_SFRST	software reset
CR_SFRST	software reset
CR_START_RX
CR_START_RX
CR_STOP	stop NIC, default = 1
CR_STOP	stop NIC, default = 1
CR_STOP_RX
CR_STOP_RX
CR_STOP_RX_DMA
CR_STOP_RX_DMA
CR_STOP_TX_DMA
CR_STOP_TX_DMA
CR_STRT	start NIC
CR_STRT	start NIC
CR_SWI
CR_SWI
CR_TDMD	tx descriptor polling demand
CR_TDMD	tx descriptor polling demand
CR_TDMD1	TDMD1
CR_TDMD1	TDMD1
CR_TX_UGO
CR_TX_UGO
CR_TXD
CR_TXD
CR_TXE
CR_TXE
CR_TXON
CR_TXON
CR_TXR
CR_TXR
CR0_DEFAULT	TX & RX burst mode
CR0_DEFAULT	TX & RX burst mode
CR0_DIAG
CR0_DIAG
CR0_DISAU
CR0_DISAU
CR0_DPOLL	disable rx/tx auto polling
CR0_DPOLL	disable rx/tx auto polling
CR0_FDXRFCEN	full-duplex RX flow control enable
CR0_FDXRFCEN	full-duplex RX flow control enable
CR0_FDXTFCEN	full-duplex TX flow control enable
CR0_FDXTFCEN	full-duplex TX flow control enable
CR0_FORSRST
CR0_FORSRST
CR0_FPHYRST
CR0_FPHYRST
CR0_GINTMSK0
CR0_GINTMSK0
CR0_GINTMSK1
CR0_GINTMSK1
CR0_GSPRST
CR0_GSPRST
CR0_HDXFCEN	half-duplex flow control enable
CR0_HDXFCEN	half-duplex flow control enable
CR0_INIT	start init process
CR0_INIT	start init process
CR0_INTPCTL
CR0_INTPCTL
CR0_RDMD	rx descriptor polling demand
CR0_RDMD	rx descriptor polling demand
CR0_RXON
CR0_RXON
CR0_RXON
CR0_RXON
CR0_SFRST	software reset
CR0_SFRST	software reset
CR0_STOP	stop NIC, default = 1
CR0_STOP	stop MAC, default = 1
CR0_STOP	stop NIC, default = 1
CR0_STOP	stop MAC, default = 1
CR0_STRT	start NIC
CR0_STRT	start MAC
CR0_STRT	start NIC
CR0_STRT	start MAC
CR0_TDMD	tx descriptor polling demand
CR0_TDMD	tx descriptor polling demand
CR0_TM0EN
CR0_TM0EN
CR0_TM1EN
CR0_TM1EN
CR0_TXON
CR0_TXON
CR0_TXON
CR0_TXON
CR0_XHITH0	TX XON high threshold 0
CR0_XHITH0	TX XON high threshold 0
CR0_XHITH1	TX XON high threshold 1
CR0_XHITH1	TX XON high threshold 1
CR0_XLTH0	TX pause frame low threshold 0
CR0_XLTH0	TX pause frame low threshold 0
CR0_XLTH1	TX pause frame low threshold 1
CR0_XLTH1	TX pause frame low threshold 1
CR0_XONEN
CR0_XONEN
CR1_DISAU
CR1_DISAU
CR1_DPOLL	disable rx/tx auto polling
CR1_DPOLL	disable rx/tx auto polling
CR1_DPOLL	disable rx/tx auto polling
CR1_DPOLL	disable rx/tx auto polling
CR1_EREN	early rx mode
CR1_EREN	early rx mode
CR1_ETEN	early tx mode
CR1_ETEN	early tx mode
CR1_FDX	full duplex mode
CR1_FDX	full duplex mode
CR1_KEYPAG	turn on par/key
CR1_KEYPAG	turn on par/key
CR1_RDMD1	RDMD1
CR1_RDMD1	RDMD1
CR1_SFRST	software reset
CR1_SFRST	software reset
CR1_SFRST	software reset
CR1_SFRST	software reset
CR1_TDMD1	TDMD1
CR1_TDMD1	TDMD1
CR1_TM0EN
CR1_TM0EN
CR1_TM1EN
CR1_TM1EN
CR15_DEFAULT	TxJabber RxWatchdog
CR15_DEFAULT	TxJabber RxWatchdog
CR2_FDXRFCEN	full-duplex RX flow control enable
CR2_FDXRFCEN	full-duplex RX flow control enable
CR2_FDXTFCEN	full-duplex TX flow control enable
CR2_FDXTFCEN	full-duplex TX flow control enable
CR2_HDXFCEN	half-duplex flow control enable
CR2_HDXFCEN	half-duplex flow control enable
CR2_XHITH0	TX XON high threshold 0
CR2_XHITH0	TX XON high threshold 0
CR2_XHITH1	TX XON high threshold 1
CR2_XHITH1	TX XON high threshold 1
CR2_XLTH0	TX pause frame low threshold 0
CR2_XLTH0	TX pause frame low threshold 0
CR2_XLTH1	TX pause frame low threshold 1
CR2_XLTH1	TX pause frame low threshold 1
CR2_XONEN
CR2_XONEN
CR3_DIAG
CR3_DIAG
CR3_FORSRST
CR3_FORSRST
CR3_FPHYRST
CR3_FPHYRST
CR3_GINTMSK0
CR3_GINTMSK0
CR3_GINTMSK1
CR3_GINTMSK1
CR3_GSPRST
CR3_GSPRST
CR3_INTPCTL
CR3_INTPCTL
CR6_DEFAULT	HD
CR6_DEFAULT	HD
CR7_DEFAULT
CR7_DEFAULT
CR9_CRDOUT
CR9_CRDOUT
CR9_SRCLK
CR9_SRCLK
CR9_SRCS
CR9_SRCS
CR9_SROM_READ
CR9_SROM_READ
crandom.c
CRC_LENGTH
CRC_LENGTH
CRC_SIZE
CRC_SIZE
CRC_SIZE
CRC_SIZE
CRC32
CRC32
crc32.c
crc32_le	Calculate 32-bit little-endian CRC checksum
CRCPOLY
create_debug_section	Create debug section
create_downloader	Instantiator
create_downloader	Instantiator
create_fakedhcpack	Create fake DHCPACK packet
create_fakedhcpdiscover	Create fake DHCPDISCOVER packet
create_fakepxebsack	Create fake PXE Boot Server ACK packet
create_reloc_section	Create relocations section
CRS_OK
CRS_OK
CRT_DC	CRT Controller Data Register - color emulation
CRT_DM	CRT Controller Data Register - mono emulation
CRT_IC	CRT Controller Index - color emulation
CRT_IM	CRT Controller Index - mono emulation
CRTC_C	25 CRT Controller Registers sequentially set
CRTC_CURSOR_END
CRTC_CURSOR_HI
CRTC_CURSOR_LO
CRTC_CURSOR_START
CRTC_H_BLANK_END
CRTC_H_BLANK_START
CRTC_H_DISP
CRTC_H_SYNC_END
CRTC_H_SYNC_START
CRTC_H_TOTAL
CRTC_LINE_COMPARE
CRTC_MAX_SCAN
CRTC_MODE
CRTC_OFFSET
CRTC_OVERFLOW
CRTC_PRESET_ROW
CRTC_START_HI
CRTC_START_LO
CRTC_UNDERLINE
CRTC_V_BLANK_END
CRTC_V_BLANK_START
CRTC_V_DISP_END
CRTC_V_SYNC_END
CRTC_V_SYNC_START
CRTC_V_TOTAL
crypto.h
crypto.h
crypto.h
crypto_null.c
crypto_null.c
CS8900
CS8900
CS8900_IRQ_MAP	This IRQ map is fixed
CS8900_IRQ_MAP	This IRQ map is fixed
CS8920
CS8920
CS8920_NO_INTS	Max CS8920 interrupt select #
CS8920_NO_INTS	Max CS8920 interrupt select #
CS8920M
CS8920M
cs89x0.c
cs89x0.c
cs89x0.h
cs89x0.h
cs89x0_disable
cs89x0_disable
cs89x0_irq
cs89x0_irq
cs89x0_poll	ETH_POLL - Wait for a frame
cs89x0_poll	ETH_POLL - Wait for a frame
cs89x0_probe
cs89x0_probe
cs89x0_probe_addr	ETH_PROBE - Look for an adapter
cs89x0_probe_addr	ETH_PROBE - Look for an adapter
cs89x0_reset	ETH_RESET - Reset adapter
cs89x0_reset	ETH_RESET - Reset adapter
cs89x0_transmit	ETH_TRANSMIT - Transmit a frame
cs89x0_transmit	ETH_TRANSMIT - Transmit a frame
CSCRBits
CSCRBits
CSI
CSM_FRAG	Fragment IP datagram
CSM_FRAG	Fragment IP datagram
CSM_IPKT	Received an IP packet
CSM_IPKT	Received an IP packet
CSM_IPOK	IP Checkusm validatiaon ok
CSM_IPOK	IP Checkusm validatiaon ok
CSM_TCPKT	Received a TCP packet
CSM_TCPKT	Received a TCP packet
CSM_TUPOK	TCP/UDP Checkusm validatiaon ok
CSM_TUPOK	TCP/UDP Checkusm validatiaon ok
CSM_UDPKT	Received a UDP packet
CSM_UDPKT	Received a UDP packet
CSR_CLR_RESET
csr_regs
csr_regs
csr_regs
CSR_SET_RESET
CSR0
CSR0
CSR1
CSR1
CSR2
CSR2
CSR3
CSR3
csr6_mode_bits
csr6_mode_bits
CSROffsets
CSTATE
CSTATE
CTL_AUTO_RELEASE
CTL_AUTO_RELEASE
CTL_CR_ENABLE
CTL_CR_ENABLE
CTL_EPROM_ACCESS	high if Eprom is being read
CTL_EPROM_ACCESS	high if Eprom is being read
CTL_LE_ENABLE
CTL_LE_ENABLE
CTL_POWERDOWN
CTL_POWERDOWN
CTL_TE_ENABLE
CTL_TE_ENABLE
ctlx_state
ctlx_state
CTRL_A
CTRL_B
CTRL_C
CTRL_D
CTRL_E
CTRL_F
CTRL_G
CTRL_H
CTRL_I
CTRL_J
CTRL_K
CTRL_L
CTRL_M
CTRL_N
CTRL_O
CTRL_P
CTRL_Q
CTRL_R
CTRL_S
CTRL_T
CTRL_U
CTRL_V
CTRL_W
CTRL_X
CTRL_Y
CTRL_Z
CTRL1	Control1 register
CTRL1	Control1 register
CTRL1_BITS
CTRL1_BITS
CTRL2	Control2 register
CTRL2	Control2 register
CTRL2_BITS
CTRL2_BITS
CTX_MASK
CTX_MASK
CTX_SHIFT
CTX_SHIFT
CTX_SIZE
CTX_SIZE
CTX_WR(bp, cid_addr, offset, val)
CTX_WR(bp, cid_addr, offset, val)
ctype.c
ctype.c
ctype.h
CU_CMD_BASE	Base address to add to add CU commands.
CU_CMD_TIMEOUT	CU command accept timeout in microseconds
CU_DUMPSTATS	Dump then reset stats counters.
CU_RESUME
CU_SHOWSTATS	Dump statistics counters.
CU_START
CU_STATSADDR
curses.h
cursor.h
cursor_pos
cwuri.c
cwuri.c
CYAN
CYAN

D

D	A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 　[Top]

D8390_COMMAND_PS0	Page 0 select
D8390_COMMAND_PS0	Page 0 select
D8390_COMMAND_PS1	Page 1 select
D8390_COMMAND_PS1	Page 1 select
D8390_COMMAND_PS2	Page 2 select
D8390_COMMAND_PS2	Page 2 select
D8390_COMMAND_RD0
D8390_COMMAND_RD0
D8390_COMMAND_RD1
D8390_COMMAND_RD1
D8390_COMMAND_RD2	Remote DMA control
D8390_COMMAND_RD2	Remote DMA control
D8390_COMMAND_STA	start
D8390_COMMAND_STA	start
D8390_COMMAND_STP	stop
D8390_COMMAND_STP	stop
D8390_COMMAND_TXP	transmit packet
D8390_COMMAND_TXP	transmit packet
D8390_DCR_FT1
D8390_DCR_FT1
D8390_DCR_LS	Loopback select
D8390_DCR_LS	Loopback select
D8390_DCR_WTS	Word transfer select
D8390_DCR_WTS	Word transfer select
D8390_ISR_CNT	Counter overflow
D8390_ISR_CNT	Counter overflow
D8390_ISR_OVW	Overflow
D8390_ISR_OVW	Overflow
D8390_ISR_PRX	successful recv
D8390_ISR_PRX	successful recv
D8390_ISR_PTX	successful xmit
D8390_ISR_PTX	successful xmit
D8390_ISR_RDC	Remote DMA complete
D8390_ISR_RDC	Remote DMA complete
D8390_ISR_RST	reset
D8390_ISR_RST	reset
D8390_ISR_RXE	receive error
D8390_ISR_RXE	receive error
D8390_ISR_TXE	transmit error
D8390_ISR_TXE	transmit error
D8390_P0_BOUND
D8390_P0_BOUND
D8390_P0_COMMAND
D8390_P0_COMMAND
D8390_P0_DCR
D8390_P0_DCR
D8390_P0_IMR
D8390_P0_IMR
D8390_P0_ISR
D8390_P0_ISR
D8390_P0_PSTART
D8390_P0_PSTART
D8390_P0_PSTOP
D8390_P0_PSTOP
D8390_P0_RBCR0
D8390_P0_RBCR0
D8390_P0_RBCR1
D8390_P0_RBCR1
D8390_P0_RCR
D8390_P0_RCR
D8390_P0_RSAR0
D8390_P0_RSAR0
D8390_P0_RSAR1
D8390_P0_RSAR1
D8390_P0_RSR
D8390_P0_RSR
D8390_P0_TBCR0
D8390_P0_TBCR0
D8390_P0_TBCR1
D8390_P0_TBCR1
D8390_P0_TCR
D8390_P0_TCR
D8390_P0_TPSR
D8390_P0_TPSR
D8390_P0_TSR
D8390_P0_TSR
D8390_P1_COMMAND
D8390_P1_COMMAND
D8390_P1_CURR
D8390_P1_CURR
D8390_P1_MAR0
D8390_P1_MAR0
D8390_P1_PAR0
D8390_P1_PAR0
D8390_P1_PAR1
D8390_P1_PAR1
D8390_P1_PAR2
D8390_P1_PAR2
D8390_P1_PAR3
D8390_P1_PAR3
D8390_P1_PAR4
D8390_P1_PAR4
D8390_P1_PAR5
D8390_P1_PAR5
D8390_PAGE_SIZE
D8390_PAGE_SIZE
D8390_RCR_MON	monitor mode
D8390_RCR_MON	monitor mode
D8390_RSTAT_CRC	CRC error
D8390_RSTAT_CRC	CRC error
D8390_RSTAT_FAE	Frame alignment error
D8390_RSTAT_FAE	Frame alignment error
D8390_RSTAT_OVER	FIFO overrun
D8390_RSTAT_OVER	FIFO overrun
D8390_RSTAT_PRX	successful recv
D8390_RSTAT_PRX	successful recv
D8390_RXBUF_END
D8390_RXBUF_END
D8390_TXBUF_SIZE
D8390_TXBUF_SIZE
DA( a, bit )
DA( a, bit )
daemonise	Daemonise
DATA_1
DATA_1
DATA_2
DATA_2
DATA_BLIND_DEF
DATA_BLIND_DEF
DATA_BLIND_DEF
DATA_BLIND_VAL(x)
DATA_BLIND_VAL(x)
DATA_BLIND_VAL(x)
DATA_PORT
DATA_PORT
data16
davicom.c
davicom.c
davicom_bufs __shared
davicom_bufs __shared
davicom_disable	eth_disable - Disable the interface
davicom_disable	eth_disable - Disable the interface
davicom_init_chain	davicom_init_chain - setup the tx and rx descriptors
davicom_init_chain	davicom_init_chain - setup the tx and rx descriptors
davicom_irq	eth_irq - enable, disable and force interrupts
davicom_irq	eth_irq - enable, disable and force interrupts
davicom_media_chk
davicom_media_chk
davicom_more
davicom_more
davicom_offsets
davicom_offsets
davicom_poll	eth_poll - Wait for a frame
davicom_poll	eth_poll - Wait for a frame
davicom_probe	eth_probe - Look for an adapter
davicom_probe	eth_probe - Look for an adapter
davicom_reset	davicom_reset - Reset adapter
davicom_reset	davicom_reset - Reset adapter
davicom_transmit	eth_transmit - Transmit a frame
davicom_transmit	eth_transmit - Transmit a frame
davicom_wait
davicom_wait
DBFENTER
DBFENTER
DBFEXIT
DBFEXIT
DBG( ... )
DBG_AC_IF( level, id )
dbg_autocolour	Choose colour index for debug autocolourisation
dbg_autocolour	Choose colour index for debug autocolourisation
dbg_autocolourise	Select automatic colour for debug messages
dbg_autocolourise	Select automatic colour for debug messages
DBG_DC_IF( level )
dbg_decolourise	Revert to normal colour
dbg_decolourise	Revert to normal colour
DBG_DISABLE( level )
DBG_DISABLE( level )
DBG_ENABLE( level )
DBG_ENABLE( level )
DBG_EXTRA
DBG_HD( ... )
DBG_HD_IF( level, data, len )
DBG_HDA( ... )
DBG_HDA_IF( level, dispaddr, data, len )
dbg_hex_dump_da	Print hex dump with specified display address
dbg_hex_dump_da	Print hex dump with specified display address
dbg_hex_dump_da_row	Print row of a hex dump with specified display address
dbg_hex_dump_da_row	Print row of a hex dump with specified display address
DBG_IF( level, ... )
DBG_IO
DBG_LOG
DBG_PROFILE
DBG2( ... )
DBG2_HD( ... )
DBG2_HDA( ... )
DBG2_RINGS( priv )
DBGC( ... )
DBGC_HD( ... )
DBGC_HD_IF( level, id, ... )
DBGC_HDA( ... )
DBGC_HDA_IF( level, id, ... )
DBGC_IF( level, id, ... )
DBGC2( ... )
DBGC2_HD( ... )
DBGC2_HDA( ... )
DBGCIO( ... )
DBGCIO_HD( ... )
DBGCIO_HDA( ... )
DBGCP( ... )
DBGCP_HD( ... )
DBGCP_HDA( ... )
DBGIO( ... )
DBGIO_HD( ... )
DBGIO_HDA( ... )
DBGLVL
DBGLVL
DBGLVL_EXTRA
DBGLVL_IO
DBGLVL_LOG
DBGLVL_MAX
DBGLVL_MAX
DBGLVL_PROFILE
DBGP( ... )
DBGP_HD( ... )
DBGP_HDA( ... )
dcbst
dcbst
DCFG_LATMEN
DCFG_LATMEN
DCFG_MRWAIT
DCFG_MRWAIT
DCFG_MWWAIT
DCFG_MWWAIT
DCFG_PERDIS
DCFG_PERDIS
DCFG_XMRL
DCFG_XMRL
DCFG_XMRM
DCFG_XMRM
DCFG_XMWI
DCFG_XMWI
deactivate_t509_device
deactivate_t509_device
dead_socket
DEBUG
DEBUG
debug.c
debug.c
DEBUG_SYMBOL
DEBUGFUNC(F)
DEBUGFUNC(F)
DEBUGFUNC(F)
DEBUGFUNC(F)
DEBUGOUT(S)
DEBUGOUT(S)
DEBUGOUT(S)
DEBUGOUT(S)
DEBUGOUT1(S, A...)
DEBUGOUT1(S, A...)
DEBUGOUT1(S, A...)
DEBUGOUT1(S, A...)
DEBUGOUT2
DEBUGOUT2
DEBUGOUT3
DEBUGOUT3
DEBUGOUT7
DEBUGOUT7
DebugSupport.h
Decode
decode_interrupt
decode_interrupt
DEF_IOBUF_SIZE
DEF_IOBUF_SIZE
DEF_MTU
DEF_MTU
DEF_RX_ACCEPT
DEF_RX_ACCEPT
DEFAULT_80003ES2LAN_TCTL_EXT_GC
DEFAULT_80003ES2LAN_TCTL_EXT_GC
DEFAULT_80003ES2LAN_TIPG_IPGR2
DEFAULT_80003ES2LAN_TIPG_IPGR2
DEFAULT_80003ES2LAN_TIPG_IPGT_1
DEFAULT_80003ES2LAN_TIPG_IPGT_1
DEFAULT_80003ES2LAN_TIPG_IPGT_1
DEFAULT_80003ES2LAN_TIPG_IPGT_1
DEFAULT_82542_TIPG_IPGR1
DEFAULT_82542_TIPG_IPGR1
DEFAULT_82542_TIPG_IPGR2
DEFAULT_82542_TIPG_IPGR2
DEFAULT_82542_TIPG_IPGT
DEFAULT_82542_TIPG_IPGT
DEFAULT_82543_TIPG_IPGR1
DEFAULT_82543_TIPG_IPGR1
DEFAULT_82543_TIPG_IPGR2
DEFAULT_82543_TIPG_IPGR2
DEFAULT_82543_TIPG_IPGT_COPPER
DEFAULT_82543_TIPG_IPGT_COPPER
DEFAULT_82543_TIPG_IPGT_FIBER
DEFAULT_82543_TIPG_IPGT_FIBER
DEFAULT_DMA_HIGH_WATER
DEFAULT_DMA_HIGH_WATER
DEFAULT_DMA_LOW_WATER
DEFAULT_DMA_LOW_WATER
DEFAULT_INTR
DEFAULT_INTR
DEFAULT_INTR
DEFAULT_INTR
DEFAULT_IPG
DEFAULT_IPG
DEFAULT_MAX_TIMEOUT
DEFAULT_MB_HIGH_WATER
DEFAULT_MB_HIGH_WATER
DEFAULT_MB_HIGH_WATER_5705
DEFAULT_MB_HIGH_WATER_5705
DEFAULT_MB_HIGH_WATER_JUMBO
DEFAULT_MB_HIGH_WATER_JUMBO
DEFAULT_MB_MACRX_LOW_WATER
DEFAULT_MB_MACRX_LOW_WATER
DEFAULT_MB_MACRX_LOW_WATER_5705
DEFAULT_MB_MACRX_LOW_WATER_5705
DEFAULT_MB_MACRX_LOW_WATER_JUMB
DEFAULT_MB_MACRX_LOW_WATER_JUMB
DEFAULT_MB_RDMA_LOW_WATER
DEFAULT_MB_RDMA_LOW_WATER
DEFAULT_MB_RDMA_LOW_WATER_5705
DEFAULT_MB_RDMA_LOW_WATER_5705
DEFAULT_MB_RDMA_LOW_WATER_JUMBO
DEFAULT_MB_RDMA_LOW_WATER_JUMBO
DEFAULT_MIN_TIMEOUT
DEFAULT_RXCOAL_MAXF_INT
DEFAULT_RXCOAL_MAXF_INT
DEFAULT_RXCOAL_TICK_INT
DEFAULT_RXCOAL_TICK_INT
DEFAULT_RXCOL_TICKS
DEFAULT_RXCOL_TICKS
DEFAULT_RXMAX_FRAMES
DEFAULT_RXMAX_FRAMES
DEFAULT_STAT_COAL_TICKS
DEFAULT_STAT_COAL_TICKS
DEFAULT_TXCOAL_MAXF_INT
DEFAULT_TXCOAL_MAXF_INT
DEFAULT_TXCOAL_TICK_INT
DEFAULT_TXCOAL_TICK_INT
DEFAULT_TXCOL_TICKS
DEFAULT_TXCOL_TICKS
DEFAULT_TXMAX_FRAMES
DEFAULT_TXMAX_FRAMES
default_xfer_alloc_iob	Allocate I/O buffer
default_xfer_alloc_iob	Allocate I/O buffer
DEFAULTIOBASE
DEFAULTIOBASE
defaults.h
defaults.h
defined
defined
DEFIO_PCI_ADDR
deinit_i82365
deinit_i82365
del_ipv4_miniroute	Delete IPv4 minirouting table entry
del_ipv6_address	Remove IPv6 interface
del_ipv6_miniroute	Delete IPv6 minirouting table entry
delay(nanosec)
delay(nanosec)
DELAY_LINK_CHECK
DELAY_LINK_CHECK
delete_character	Delete character at current cursor position
delete_character	Delete character at current cursor position
delwin	@file
depca.c
depca.c
DEPCA_ADDR	LANCE registers' address port
DEPCA_ADDR	LANCE registers' address port
DEPCA_CNFG	EISA Configuration port
DEPCA_CNFG	EISA Configuration port
DEPCA_DATA	LANCE registers' data port
DEPCA_DATA	LANCE registers' data port
depca_disable	DISABLE - Turn off ethernet interface
depca_disable	DISABLE - Turn off ethernet interface
DEPCA_HBASE	EISA high memory base address reg.
DEPCA_HBASE	EISA high memory base address reg.
depca_init
depca_init
depca_init_ring
depca_init_ring
depca_irq	IRQ - Interrupt Control
depca_irq	IRQ - Interrupt Control
DEPCA_MODEL
DEPCA_MODEL
DEPCA_NICSR	Network interface CSR
DEPCA_NICSR	Network interface CSR
depca_poll	POLL - Wait for a frame
depca_poll	POLL - Wait for a frame
depca_private
depca_private
depca_probe	PROBE - Look for an adapter, this routine's visible to the outside
depca_probe	PROBE - Look for an adapter, this routine's visible to the outside
depca_probe1
depca_probe1
DEPCA_PROM	Ethernet address ROM data port
DEPCA_PROM	Ethernet address ROM data port
DEPCA_RAM_BASE
DEPCA_RAM_BASE
DEPCA_RBI	RAM buffer index (2k buffer mode)
DEPCA_RBI	RAM buffer index (2k buffer mode)
DEPCA_RBSA	RAM buffer starting address (2k buff.)
DEPCA_RBSA	RAM buffer starting address (2k buff.)
depca_reset	RESET - Reset adapter
depca_reset	RESET - Reset adapter
depca_rx_desc
depca_rx_desc
depca_transmit	TRANSMIT - Transmit a frame
depca_transmit	TRANSMIT - Transmit a frame
depca_tx_desc
depca_tx_desc
derwin	Create a new derived window
desc.h
desc.h
DESC_ALL_CNT
DESC_ALL_CNT
DESC_CTRL_CMASK	Core specific bits
DESC_CTRL_CMASK	Core specific bits
DESC_CTRL_EOF	End of Frame
DESC_CTRL_EOF	End of Frame
DESC_CTRL_EOT	End of Table
DESC_CTRL_EOT	End of Table
DESC_CTRL_IOC	Interrupt On Completion
DESC_CTRL_IOC	Interrupt On Completion
DESC_CTRL_LEN
DESC_CTRL_LEN
DESC_CTRL_SOF	Start of Frame
DESC_CTRL_SOF	Start of Frame
DESC_RING_WRAP
DESC_RING_WRAP
DESC_SIZE	Should be cache line sized
DESC_SIZE	Should be cache line sized
desc_status_bit
desc_status_bit
desc_status_bits
desc_status_bits
desc_status_bits
desc_status_bits
desc_status_bits
desc_status_bits
desc_status_bits
desc_status_bits
DESC_VER_1
DESC_VER_1
DESC_VER_2
DESC_VER_2
DESELECT_SLAVE
DESELECT_SLAVE
detect_aui
detect_aui
detect_bnc
detect_bnc
detect_tp
detect_tp
DEV_IRQMASK_1	use NVREG_IRQMASK_WANTED_1 for irq mask
DEV_IRQMASK_1	use NVREG_IRQMASK_WANTED_1 for irq mask
DEV_IRQMASK_2	use NVREG_IRQMASK_WANTED_2 for irq mask
DEV_IRQMASK_2	use NVREG_IRQMASK_WANTED_2 for irq mask
DEV_NEED_LASTPACKET1	set LASTPACKET1 in tx flags
DEV_NEED_LASTPACKET1	set LASTPACKET1 in tx flags
DEV_NEED_LINKTIMER	poll link settings. Relies on the timer irq
DEV_NEED_LINKTIMER	poll link settings. Relies on the timer irq
DEV_NEED_TIMERIRQ	set the timer irq flag in the irq mask
DEV_NEED_TIMERIRQ	set the timer irq flag in the irq mask
dev_pci_struct
dev_pci_struct
DEV_PRESENT_BIT(_b)
DEV_PRESENT_BIT(_b)
DEVCTRL_EPR	EPHY Reset
DEVCTRL_EPR	EPHY Reset
DEVCTRL_IPP	Internal EPHY Present
DEVCTRL_IPP	Internal EPHY Present
DEVCTRL_MPM	MP PME Enable (B0 only)
DEVCTRL_MPM	MP PME Enable (B0 only)
DEVCTRL_PADDR	PHY Address
DEVCTRL_PADDR	PHY Address
DEVCTRL_PADDR_SHIFT
DEVCTRL_PADDR_SHIFT
DEVCTRL_PFE	Pattern Filtering Enable
DEVCTRL_PFE	Pattern Filtering Enable
DEVCTRL_PMCE	PHY Mode Clocks Enable
DEVCTRL_PMCE	PHY Mode Clocks Enable
DEVCTRL_PME	PHY Mode Enable
DEVCTRL_PME	PHY Mode Enable
device
DEVICE
DEVICE
device.c
device.c
device.h
DEVICE_CAP_MAX_PAYLOAD_MASK
DEVICE_CAP_MAX_PAYLOAD_MASK
DEVICE_CAP_MAX_PAYLOAD_SHIFT
DEVICE_CAP_MAX_PAYLOAD_SHIFT
DEVICE_CTRL_MAX_PAYLOAD_MASK
DEVICE_CTRL_MAX_PAYLOAD_MASK
DEVICE_CTRL_MAX_PAYLOAD_SHIFT
DEVICE_CTRL_MAX_PAYLOAD_SHIFT
DEVICE_CTRL_MAX_RREQ_SZ_MASK
DEVICE_CTRL_MAX_RREQ_SZ_MASK
DEVICE_CTRL_MAX_RREQ_SZ_SHIFT
DEVICE_CTRL_MAX_RREQ_SZ_SHIFT
device_description
DEVICE_ID_NOCARE
DEVICE_LOGICAL_UNIT_DEVICE_PATH
DEVICE_PATH_MESSAGING_PC_ANSI
DEVICE_PATH_MESSAGING_SAS
DEVICE_PATH_MESSAGING_UART_FLOW
DEVICE_PATH_MESSAGING_VT_100
DEVICE_PATH_MESSAGING_VT_100_PL
DEVICE_PATH_MESSAGING_VT_UTF8
DEVICE_PATH_PROTOCOL
DEVICE_SPEED_MASK	Device Ctrl Reg Speed Mask
DEVICE_SPEED_MASK	Device Ctrl Reg Speed Mask
DevicePath.h
dhcp	@file
dhcp.c
dhcp.h
DHCP_BOOTFILE_NAME
DHCP_BYTE( value )
dhcp_chaddr	Packet construction
DHCP_CLIENT_ARCHITECTURE
dhcp_client_id
DHCP_CLIENT_ID
DHCP_CLIENT_NDI
dhcp_client_uuid
DHCP_CLIENT_UUID
DHCP_CLIENT_UUID_TYPE
dhcp_cmd.c
dhcp_cmd.c
dhcp_create_packet	Create a DHCP packet
dhcp_create_request	Create DHCP request packet
dhcp_deliver_iob	Receive new data
dhcp_discovery_expired	Handle timer expiry during DHCP discovery
dhcp_discovery_rx	Handle received packet during DHCP discovery
dhcp_discovery_tx	DHCP state machine
DHCP_DNS_SERVERS
DHCP_DOMAIN_NAME
DHCP_DWORD( value )
DHCP_EB_BIOS_DRIVE
DHCP_EB_BUS_ID
DHCP_EB_ENCAP
DHCP_EB_FEATURE_AOE	*< AoE protocol
DHCP_EB_FEATURE_BZIMAGE	*< bzImage format
DHCP_EB_FEATURE_COMBOOT	*< COMBOOT format
DHCP_EB_FEATURE_DNS	*< DNS protocol
DHCP_EB_FEATURE_EFI	*< EFI format
DHCP_EB_FEATURE_ELF	*< ELF format
DHCP_EB_FEATURE_FTP	*< FTP protocol
DHCP_EB_FEATURE_HTTP	*< HTTP protocol
DHCP_EB_FEATURE_HTTPS	*< HTTPS protocol
DHCP_EB_FEATURE_ISCSI	*< iSCSI protocol
DHCP_EB_FEATURE_MULTIBOOT	*< Multiboot format
DHCP_EB_FEATURE_NBI	*< NBI format
DHCP_EB_FEATURE_PXE	*< PXE format
DHCP_EB_FEATURE_PXE_EXT	*< PXE API extensions
DHCP_EB_FEATURE_SLAM	*< SLAM protocol
DHCP_EB_FEATURE_SRP	*< SRP protocol
DHCP_EB_FEATURE_TFTP	*< TFTP protocol
DHCP_EB_KEEP_SAN
DHCP_EB_NO_PXEDHCP
DHCP_EB_PASSWORD
DHCP_EB_PRIORITY
DHCP_EB_REVERSE_PASSWORD
DHCP_EB_REVERSE_USERNAME
DHCP_EB_SIADDR
DHCP_EB_USERNAME
DHCP_EB_VERSION
DHCP_EB_YIADDR
DHCP_ENCAP( ... )
DHCP_ENCAP_OPT( encapsulator, encapsulated )
DHCP_ENCAPSULATED( encap_opt )
DHCP_ENCAPSULATOR( encap_opt )
DHCP_END
dhcp_exec	The "dhcp" command
dhcp_exec	The "dhcp" command
DHCP_FEATURE( feature_opt, ... )
DHCP_FEATURES
dhcp_finished	Mark DHCP session as complete
dhcp_free	Free DHCP session
DHCP_HOST_NAME
DHCP_IS_ENCAP_OPT( opt )
DHCP_ISCSI_INITIATOR_IQN
DHCP_ISCSI_PRIMARY_TARGET_IQN
DHCP_ISCSI_SECONDARY_TARGET_IQN
dhcp_job_kill	Job control interface
DHCP_LEASE_TIME
DHCP_LOG_SERVERS
DHCP_MAGIC_COOKIE
DHCP_MAX_LEN
DHCP_MAX_MESSAGE_SIZE
DHCP_MAX_OPTION
DHCP_MAX_TIMEOUT
DHCP_MESSAGE_TYPE
DHCP_MIN_LEN
DHCP_MIN_OPTION
DHCP_MIN_TIMEOUT
dhcp_msgtype_name	Name a DHCP packet type
dhcp_netdev_desc
DHCP_OPT_LEN
dhcp_option
DHCP_OPTION( ... )
DHCP_OPTION_HEADER_LEN
dhcp_option_len	Calculate length of any DHCP option
DHCP_OPTION_OVERLOAD
DHCP_OPTION_OVERLOAD_FILE
DHCP_OPTION_OVERLOAD_SNAME
dhcp_options
dhcp_packet
dhcp_packet_field	Get address of a DHCP packet field
dhcp_packet_field
DHCP_PACKET_FIELD( _tag, _field, _used_len )
DHCP_PAD
DHCP_PARAMETER_REQUEST_LIST
dhcp_proxy_expired	Handle timer expiry during ProxyDHCP request
dhcp_proxy_rx	Handle received packet during ProxyDHCP request
dhcp_proxy_tx	Construct transmitted packet for ProxyDHCP request
dhcp_pxe_boot_menu
DHCP_PXE_BOOT_MENU
dhcp_pxe_boot_menu_item
DHCP_PXE_BOOT_MENU_ITEM
dhcp_pxe_boot_menu_prompt
DHCP_PXE_BOOT_MENU_PROMPT
dhcp_pxe_boot_server
DHCP_PXE_BOOT_SERVER_MCAST
DHCP_PXE_BOOT_SERVERS
dhcp_pxe_discovery_control
DHCP_PXE_DISCOVERY_CONTROL
dhcp_pxebs_accept	Check to see if PXE Boot Server address is acceptable
dhcp_pxebs_expired	Handle timer expiry during PXE Boot Server Discovery
dhcp_pxebs_rx	Handle received packet during PXE Boot Server Discovery
dhcp_pxebs_tx	Construct transmitted packet for PXE Boot Server Discovery
dhcp_request_expired	Handle timer expiry during DHCP discovery
dhcp_request_rx	Handle received packet during DHCP request
dhcp_request_tx	Construct transmitted packet for DHCP request
DHCP_REQUESTED_ADDRESS
DHCP_ROOT_PATH
DHCP_ROUTERS
DHCP_SERVER_IDENTIFIER
dhcp_session
dhcp_session_state
dhcp_set_state	Transition to new DHCP session state
DHCP_SETTINGS_NAME
DHCP_STRING( ... )
DHCP_SUBNET_MASK
dhcp_syntax	@file
dhcp_syntax	@file
dhcp_tag_name	@file
DHCP_TFTP_SERVER_NAME
dhcp_timer_expired	Handle DHCP retry timer expiry
dhcp_tx	Data transfer interface
DHCP_USER_CLASS_ID
DHCP_VENDOR_CLASS_ID
DHCP_VENDOR_ENCAP
DHCP_WORD( value )
dhcp_xid	Calculate DHCP transaction ID for a network device
DHCPACK
DHCPACK
DHCPDECLINE
DHCPDISCOVER
DHCPDISCOVER
dhcphdr
DHCPINFORM
dhcpmgmt.c
dhcpmgmt.h
DHCPNAK
DHCPNONE
DHCPOFFER
DHCPOFFER
dhcpopt_extensible_store	Store value of DHCP option setting, extending options block if necessary
dhcpopt_fetch	Fetch value of DHCP option setting
dhcpopt_init	Initialise prepopulated block of DHCP options
dhcpopt_store	Store value of DHCP option setting
dhcpopt_update_len	Recalculate length of DHCP options block
dhcpopts.c
dhcpopts.h
dhcppkt.c
dhcppkt.h
dhcppkt_fetch	Fetch value of DHCP packet setting
dhcppkt_init	Constructor
dhcppkt_settings_fetch	Fetch value of DHCP setting
dhcppkt_settings_store	DHCP packet settings interface
dhcppkt_store	Store value of DHCP packet setting
DHCPRELEASE
DHCPREQUEST
DHCPREQUEST
DIAGNOSE_CMD
DIAGNOSE_CMD
DiagnosticReg
DiagnosticReg
digest_algorithm
digest_cmd.c
digest_exec	The "digest" command
digest_null_final
digest_null_final
digest_null_init
digest_null_init
digest_null_update
digest_null_update
digest_syntax	"digest" command syntax message
dirname	Return directory name from path
dirname	Return directory name from path
disable_irq(x)
DISABLE_UTP
DISABLE_UTP
DISABLE_UTP
DISABLE_UTP
DISK_IDE
DISK_MEM
DISK_USB
disp_bi
DIV_ROUND_UP(n,d)
DIV_ROUND_UP(n,d)
DLY_INT_A	Group A delayed interrupt register
DLY_INT_A	Group A delayed interrupt register
DLY_INT_A_BITS
DLY_INT_A_BITS
DLY_INT_B	Group B delayed interrupt register
DLY_INT_B	Group B delayed interrupt register
DLY_INT_B_BITS
DLY_INT_B_BITS
DM9102_IO_SIZE
DM9102_IO_SIZE
DM9102A_IO_SIZE
DM9102A_IO_SIZE
DM910X_RESET
DM910X_RESET
dm9132_id_table
dm9132_id_table
DM9801_NOISE_FLOOR
DM9801_NOISE_FLOOR
DM9802_NOISE_FLOOR
DM9802_NOISE_FLOOR
dma_addr_t
dma_addr_t
dma_addr_t
dma_addr_t
DMA_ADDR_T_WIDTH
DMA_ADDR_T_WIDTH
DMA_BASE	DMA controller base
DMA_BASE	DMA controller base
DMA_BASE_2	DMA controller base
DMA_BASE_2	DMA controller base
DMA_BURST
DMA_BURST
DMA_BURST_MODE
DMA_BURST_MODE
DMA_CTRL_DMAR_BURST_LEN_MASK
DMA_CTRL_DMAR_BURST_LEN_MASK
DMA_CTRL_DMAR_BURST_LEN_SHIFT
DMA_CTRL_DMAR_BURST_LEN_SHIFT
DMA_CTRL_DMAR_DLY_CNT_MASK
DMA_CTRL_DMAR_DLY_CNT_MASK
DMA_CTRL_DMAR_DLY_CNT_SHIFT
DMA_CTRL_DMAR_DLY_CNT_SHIFT
DMA_CTRL_DMAR_ENH_ORDER
DMA_CTRL_DMAR_ENH_ORDER
DMA_CTRL_DMAR_IN_ORDER
DMA_CTRL_DMAR_IN_ORDER
DMA_CTRL_DMAR_OUT_ORDER
DMA_CTRL_DMAR_OUT_ORDER
DMA_CTRL_DMAR_REQ_PRI
DMA_CTRL_DMAR_REQ_PRI
DMA_CTRL_DMAW_BURST_LEN_MASK
DMA_CTRL_DMAW_BURST_LEN_MASK
DMA_CTRL_DMAW_BURST_LEN_SHIFT
DMA_CTRL_DMAW_BURST_LEN_SHIFT
DMA_CTRL_DMAW_DLY_CNT_MASK
DMA_CTRL_DMAW_DLY_CNT_MASK
DMA_CTRL_DMAW_DLY_CNT_SHIFT
DMA_CTRL_DMAW_DLY_CNT_SHIFT
DMA_CTRL_RCB_VALUE
DMA_CTRL_RCB_VALUE
DMA_CTRL_RXCMB_EN
DMA_CTRL_RXCMB_EN
DMA_CTRL_TXCMB_EN
DMA_CTRL_TXCMB_EN
dma_desc
dma_desc
DMA_DISABLE	Disable channel n
DMA_DISABLE	Disable channel n
DMA_ENABLE	Enable channel n
DMA_ENABLE	Enable channel n
DMA_LENGTH_DEF
DMA_LENGTH_DEF
DMA_LENGTH_MAX
DMA_LENGTH_MAX
DMA_LENGTH_MIN
DMA_LENGTH_MIN
DMA_MASK	DMA controller mask register
DMA_MASK	DMA controller mask register
DMA_MODE	DMA controller mode register
DMA_MODE	DMA controller mode register
DMA_NO_MASK
DMA_NO_MASK
DMA_READ	Used to mark state of the repins code (chip or dma)
DMA_READ	Used to mark state of the repins code (chip or dma)
DMA_READ_CHANS
DMA_READ_CHANS
DMA_RESETFF	DMA controller first/last flip flop
DMA_RESETFF	DMA controller first/last flip flop
DMA_RWCTRL_ASSERT_ALL_BE
DMA_RWCTRL_ASSERT_ALL_BE
DMA_RWCTRL_MIN_DMA
DMA_RWCTRL_MIN_DMA
DMA_RWCTRL_MIN_DMA_SHIFT
DMA_RWCTRL_MIN_DMA_SHIFT
DMA_RWCTRL_ONE_DMA
DMA_RWCTRL_ONE_DMA
DMA_RWCTRL_PCI_READ_CMD
DMA_RWCTRL_PCI_READ_CMD
DMA_RWCTRL_PCI_READ_CMD_SHIFT
DMA_RWCTRL_PCI_READ_CMD_SHIFT
DMA_RWCTRL_PCI_WRITE_CMD
DMA_RWCTRL_PCI_WRITE_CMD
DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
DMA_RWCTRL_READ_BNDRY_1024
DMA_RWCTRL_READ_BNDRY_1024
DMA_RWCTRL_READ_BNDRY_128
DMA_RWCTRL_READ_BNDRY_128
DMA_RWCTRL_READ_BNDRY_16
DMA_RWCTRL_READ_BNDRY_16
DMA_RWCTRL_READ_BNDRY_256
DMA_RWCTRL_READ_BNDRY_256
DMA_RWCTRL_READ_BNDRY_32
DMA_RWCTRL_READ_BNDRY_32
DMA_RWCTRL_READ_BNDRY_512
DMA_RWCTRL_READ_BNDRY_512
DMA_RWCTRL_READ_BNDRY_64
DMA_RWCTRL_READ_BNDRY_64
DMA_RWCTRL_READ_BNDRY_DISAB
DMA_RWCTRL_READ_BNDRY_DISAB
DMA_RWCTRL_READ_BNDRY_MASK
DMA_RWCTRL_READ_BNDRY_MASK
DMA_RWCTRL_READ_WATER
DMA_RWCTRL_READ_WATER
DMA_RWCTRL_READ_WATER_SHIFT
DMA_RWCTRL_READ_WATER_SHIFT
DMA_RWCTRL_USE_MEM_READ_MULT
DMA_RWCTRL_USE_MEM_READ_MULT
DMA_RWCTRL_WRITE_BNDRY_1024
DMA_RWCTRL_WRITE_BNDRY_1024
DMA_RWCTRL_WRITE_BNDRY_128
DMA_RWCTRL_WRITE_BNDRY_128
DMA_RWCTRL_WRITE_BNDRY_16
DMA_RWCTRL_WRITE_BNDRY_16
DMA_RWCTRL_WRITE_BNDRY_256
DMA_RWCTRL_WRITE_BNDRY_256
DMA_RWCTRL_WRITE_BNDRY_32
DMA_RWCTRL_WRITE_BNDRY_32
DMA_RWCTRL_WRITE_BNDRY_512
DMA_RWCTRL_WRITE_BNDRY_512
DMA_RWCTRL_WRITE_BNDRY_64
DMA_RWCTRL_WRITE_BNDRY_64
DMA_RWCTRL_WRITE_BNDRY_DISAB
DMA_RWCTRL_WRITE_BNDRY_DISAB
DMA_RWCTRL_WRITE_BNDRY_MASK
DMA_RWCTRL_WRITE_BNDRY_MASK
DMA_RWCTRL_WRITE_WATER
DMA_RWCTRL_WRITE_WATER
DMA_RWCTRL_WRITE_WATER_SHIFT
DMA_RWCTRL_WRITE_WATER_SHIFT
DMA_RX_MODE
DMA_RX_MODE
DMA_SIZE	Size of dma buffer - 16k
DMA_SIZE	Size of dma buffer - 16k
DMA_STAT	DMA controller status register
DMA_STAT	DMA controller status register
DMA_TX_MODE
DMA_TX_MODE
DMA_WRITE_CHANS
DMA_WRITE_CHANS
DMAC_MODE
DMAC_MODE
DMAC_MODE_ENABLE
DMAC_MODE_ENABLE
DMAC_MODE_RESET
DMAC_MODE_RESET
DMAFIFO_AD_OMASK	Offset Mask
DMAFIFO_AD_OMASK	Offset Mask
DMAFIFO_AD_SMASK	Select Mask
DMAFIFO_AD_SMASK	Select Mask
DMAFIFO_AD_SRDD	Select Receive DMA Data
DMAFIFO_AD_SRDD	Select Receive DMA Data
DMAFIFO_AD_SRDP	Sel Receive DMA Pointers
DMAFIFO_AD_SRDP	Sel Receive DMA Pointers
DMAFIFO_AD_SRFD	Select Receive FIFO Data
DMAFIFO_AD_SRFD	Select Receive FIFO Data
DMAFIFO_AD_SRFP	Sel Receive FIFO Pointers
DMAFIFO_AD_SRFP	Sel Receive FIFO Pointers
DMAFIFO_AD_SXDD	Select Transmit DMA Data
DMAFIFO_AD_SXDD	Select Transmit DMA Data
DMAFIFO_AD_SXDP	Sel Transmit DMA Pointers
DMAFIFO_AD_SXDP	Sel Transmit DMA Pointers
DMAFIFO_AD_SXFD	Select Transmit FIFO Data
DMAFIFO_AD_SXFD	Select Transmit FIFO Data
DMAFIFO_AD_SXFP	Sel Transmit FIFO Pointers
DMAFIFO_AD_SXFP	Sel Transmit FIFO Pointers
DMAR_DLY_CNT
DMAR_DLY_CNT
DMARX_CTRL_ENABLE	Enable
DMARX_CTRL_ENABLE	Enable
DMARX_CTRL_ROMASK	Receive Offset Mask
DMARX_CTRL_ROMASK	Receive Offset Mask
DMARX_CTRL_ROSHIFT	Receive Offset Shift
DMARX_CTRL_ROSHIFT	Receive Offset Shift
DMARX_STAT_CDMASK	Current Descriptor Mask
DMARX_STAT_CDMASK	Current Descriptor Mask
DMARX_STAT_EBEBW	Error on Buffer Write
DMARX_STAT_EBEBW	Error on Buffer Write
DMARX_STAT_EBEDA	Bus Error on Desc. Access
DMARX_STAT_EBEDA	Bus Error on Desc. Access
DMARX_STAT_EDFO	Error Data FIFO Overflow
DMARX_STAT_EDFO	Error Data FIFO Overflow
DMARX_STAT_EDPE	Error Desc. Protocol Error
DMARX_STAT_EDPE	Error Desc. Protocol Error
DMARX_STAT_EMASK	Error Mask
DMARX_STAT_EMASK	Error Mask
DMARX_STAT_ENONE	Error None
DMARX_STAT_ENONE	Error None
DMARX_STAT_SACTIVE	State Active
DMARX_STAT_SACTIVE	State Active
DMARX_STAT_SDISABLED	State Disbaled
DMARX_STAT_SDISABLED	State Disbaled
DMARX_STAT_SIDLE	State Idle Wait
DMARX_STAT_SIDLE	State Idle Wait
DMARX_STAT_SMASK	State Mask
DMARX_STAT_SMASK	State Mask
DMARX_STAT_SSTOPPED	State Stopped
DMARX_STAT_SSTOPPED	State Stopped
DMATX_CTRL_ENABLE	Enable
DMATX_CTRL_ENABLE	Enable
DMATX_CTRL_FAIRPRIOR	Fair Priority
DMATX_CTRL_FAIRPRIOR	Fair Priority
DMATX_CTRL_FLUSH	Flush Request
DMATX_CTRL_FLUSH	Flush Request
DMATX_CTRL_LPBACK	Loopback Enable
DMATX_CTRL_LPBACK	Loopback Enable
DMATX_CTRL_SUSPEND	Suepend Request
DMATX_CTRL_SUSPEND	Suepend Request
DMATX_STAT_CDMASK	Current Descriptor Mask
DMATX_STAT_CDMASK	Current Descriptor Mask
DMATX_STAT_EBEBR	Bus Error on Buffer Read
DMATX_STAT_EBEBR	Bus Error on Buffer Read
DMATX_STAT_EBEDA	Bus Error on Desc. Access
DMATX_STAT_EBEDA	Bus Error on Desc. Access
DMATX_STAT_EDFU	Error Data FIFO Underrun
DMATX_STAT_EDFU	Error Data FIFO Underrun
DMATX_STAT_EDPE	Error Desc. Protocol Error
DMATX_STAT_EDPE	Error Desc. Protocol Error
DMATX_STAT_EMASK	Error Mask
DMATX_STAT_EMASK	Error Mask
DMATX_STAT_ENONE	Error None
DMATX_STAT_ENONE	Error None
DMATX_STAT_FLUSHED	Flushed
DMATX_STAT_FLUSHED	Flushed
DMATX_STAT_SACTIVE	State Active
DMATX_STAT_SACTIVE	State Active
DMATX_STAT_SDISABLED	State Disabled
DMATX_STAT_SDISABLED	State Disabled
DMATX_STAT_SIDLE	State Idle Wait
DMATX_STAT_SIDLE	State Idle Wait
DMATX_STAT_SMASK	State Mask
DMATX_STAT_SMASK	State Mask
DMATX_STAT_SSTOPPED	State Stopped
DMATX_STAT_SSTOPPED	State Stopped
DMATX_STAT_SSUSP	State Suspend Pending
DMATX_STAT_SSUSP	State Suspend Pending
DMAW_DLY_CNT
DMAW_DLY_CNT
dmfe.c
dmfe.c
DMFE_100MFD
DMFE_100MFD
DMFE_100MHF
DMFE_100MHF
DMFE_10MFD
DMFE_10MFD
DMFE_10MHF
DMFE_10MHF
DMFE_1M_HPNA
DMFE_1M_HPNA
DMFE_AUTO
DMFE_AUTO
dmfe_bufs __shared
dmfe_bufs __shared
dmfe_CR6_bits
dmfe_CR6_bits
DMFE_DBUG(dbug_now, msg, value)
DMFE_DBUG(dbug_now, msg, value)
dmfe_descriptor_init
dmfe_descriptor_init
dmfe_disable	DISABLE - Turn off ethernet interface
dmfe_disable	DISABLE - Turn off ethernet interface
dmfe_init_dm910x
dmfe_init_dm910x
dmfe_irq
dmfe_irq
DMFE_MAX_MULTICAST
DMFE_MAX_MULTICAST
dmfe_offsets
dmfe_offsets
dmfe_parse_srom
dmfe_parse_srom
dmfe_poll	POLL - Wait for a frame
dmfe_poll	POLL - Wait for a frame
dmfe_private
dmfe_private
dmfe_probe
dmfe_probe
dmfe_process_mode
dmfe_process_mode
dmfe_program_DM9801
dmfe_program_DM9801
dmfe_program_DM9802
dmfe_program_DM9802
dmfe_reset
dmfe_reset
dmfe_sense_speed
dmfe_sense_speed
dmfe_set_phyxcer
dmfe_set_phyxcer
DMFE_TIMER_WUT	timer wakeup time : 1 second
DMFE_TIMER_WUT	timer wakeup time : 1 second
dmfe_transmit	TRANSMIT - Transmit a frame
dmfe_transmit	TRANSMIT - Transmit a frame
DMFE_TX_KICK	tx packet Kick-out time 0.5 s"
DMFE_TX_KICK	tx packet Kick-out time 0.5 s"
DMFE_TX_TIMEOUT	tx packet time-out time 1.5 s"
DMFE_TX_TIMEOUT	tx packet time-out time 1.5 s"
DMFE_TXTH_128	TX TH 128 byte
DMFE_TXTH_128	TX TH 128 byte
DMFE_TXTH_1K	TX TH 1K byte
DMFE_TXTH_1K	TX TH 1K byte
DMFE_TXTH_256	TX TH 256 byte
DMFE_TXTH_256	TX TH 256 byte
DMFE_TXTH_512	TX TH 512 byte
DMFE_TXTH_512	TX TH 512 byte
DMFE_TXTH_72	TX TH 72 byte
DMFE_TXTH_72	TX TH 72 byte
DMFE_TXTH_96	TX TH 96 byte
DMFE_TXTH_96	TX TH 96 byte
dns.c
dns.h
DNS_CLASS_CH
DNS_CLASS_CS
DNS_CLASS_HS
DNS_CLASS_IN
dns_decompress_name	Decompress a DNS name
dns_done	Mark DNS request as complete
dns_find_rr	Find an RR in a reply packet corresponding to our query
DNS_FLAG_BROADCAST
DNS_FLAG_OPCODE(flags)
DNS_FLAG_OPCODE_IQUERY
DNS_FLAG_OPCODE_QUERY
DNS_FLAG_OPCODE_STATUS
DNS_FLAG_QR(flags)
DNS_FLAG_QUERY
DNS_FLAG_RA
DNS_FLAG_RCODE(flags)
DNS_FLAG_RCODE_NX
DNS_FLAG_RCODE_OK
DNS_FLAG_RD
DNS_FLAG_RESPONSE
dns_header
dns_make_name	Convert a standard NUL-terminated string to a DNS name
DNS_MAX_CNAME_RECURSION
DNS_MAX_RETRIES
dns_name_cmp	Compare DNS reply name against the query name from the original request
DNS_PORT
dns_qualify_name	Append DHCP domain name if available and name is not fully qualified
dns_query
dns_query_info
dns_request
dns_resolv	Resolve name using DNS
dns_rr_info
dns_rr_info_a
dns_rr_info_cname
dns_rr_info_common
dns_rr_info_nb
dns_send_packet	Send next packet in DNS request
dns_skip_name	Skip over a (possibly compressed) DNS name
dns_timer_expired	Handle DNS retransmission timer expiry
DNS_TYPE_A
DNS_TYPE_ANY
DNS_TYPE_CNAME
DNS_TYPE_NB
dns_unmake_name	Convert an uncompressed DNS name to a NUL-terminated string
dns_xfer_close	Receive new data
dns_xfer_deliver_raw	Receive new data
do_eeprom_cmd
DO_QUERY_CAP(cap, mod, var)
DO_QUERY_CAP(cap, mod, var)
DOT11_RATE5_ISBASIC_GET(r)
DOT11_RATE5_ISBASIC_GET(r)
downloader
downloader
downloader.c
downloader.c
downloader.h
downloader_ensure_size	Ensure that download buffer is large enough for the specified size
downloader_ensure_size	Ensure that download buffer is large enough for the specified size
downloader_finished	Terminate download
downloader_finished	Terminate download
downloader_free	Free downloader object
downloader_free	Free downloader object
downloader_job_kill	Job control interface
downloader_job_kill	Job control interface
downloader_job_progress	Report progress of download job
downloader_job_progress	Report progress of download job
downloader_xfer_close	Handle close() event received via data transfer interface
downloader_xfer_close	Handle close() event received via data transfer interface
downloader_xfer_deliver_iob	Data transfer interface
downloader_xfer_deliver_iob	Data transfer interface
DPLX_DET_FULL
DPLX_DET_FULL
DPLX_FULL
DPLX_FULL
dprintf(...)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
dprintf(x)
draw_byte
draw_byte
draw_byte_16
draw_byte_16
draw_byte_32
draw_byte_32
draw_byte_8
draw_byte_8
draw_editbox	Draw text box widget
draw_info_row	Draw information row
draw_instruction_row	Draw instruction row
draw_setting	Draw setting widget
draw_title_row	Draw title row
DRIVER(_name_text,_unused2,_unused3,_name,_probe,_disable)
DRIVER_DEBUG
DRIVER_DEBUG
driver_interact_t
DriverBinding.h
DRTY	Disable Retry
DRTY	Disable Retry
drv_date
drv_date
drv_date
drv_date
drv_date
drv_date
drv_date
drv_date
DRV_NAME
DRV_NAME
DRV_NAME
DRV_NAME
DRV_NAME
DRV_PULSE_PERIOD_MS
DRV_PULSE_PERIOD_MS
DRV_STATE_START
DRV_STATE_START
DRV_STATE_SUSPEND
DRV_STATE_SUSPEND
DRV_STATE_UNLOAD
DRV_STATE_UNLOAD
DRV_STATE_WOL
DRV_STATE_WOL
drv_version
drv_version
drv_version
drv_version
drv_version
drv_version
drv_version
drv_version
DRV_VERSION
DRV_VERSION
DRV_VERSION
DRV_VERSION
DRV_VERSION
DRVR_INT	Driver generated interrupt.
DRX	Disable the Receiver
DRX	Disable the Receiver
DSIZE
DSIZE
DSIZE
DSP_RESET_DISABLE
DSP_RESET_DISABLE
DSP_RESET_ENABLE
DSP_RESET_ENABLE
DSPCFG_COEF	see coefficient (in TSTDAT) bit in DSPCFG
DSPCFG_COEF	see coefficient (in TSTDAT) bit in DSPCFG
DSPCFG_LOCK	coefficient lock bit in DSPCFG
DSPCFG_LOCK	coefficient lock bit in DSPCFG
DSPCFG_VAL
DSPCFG_VAL
DTCR	Disable Transmit CRC
DTCR	Disable Transmit CRC
DTX	Disable the Transmitter
DTX	Disable the Transmitter
dummy_connect
dummy_connect
dummy_irq
dummy_irq
dump_uri	Dump URI for debugging
dump_uri	Dump URI for debugging
dumpregs.c
duplex
DUPLEX_FULL
DUPLEX_FULL
DUPLEX_FULL
DUPLEX_FULL
DUPLEX_FULL
DUPLEX_FULL
DUPLEX_FULL
DUPLEX_FULL
DUPLEX_FULL
DUPLEX_FULL
DUPLEX_FULL
DUPLEX_HALF
DUPLEX_HALF
DUPLEX_HALF
DUPLEX_HALF
DUPLEX_HALF
DUPLEX_HALF
DUPLEX_HALF
DUPLEX_HALF
DUPLEX_HALF
DUPLEX_HALF
DUPLEX_HALF
DUPLEX_INVALID
DUPLEX_INVALID
DUPLEX_INVALID
DUPLEX_INVALID
DUPLEX_INVALID
DUPLEX_INVALID
dupwin	Create a duplicate of the specified window
dwCurrentRDSE0
dwCurrentRDSE0
dwCurrentRDSE1
dwCurrentRDSE1
dwCurrentRDSE2
dwCurrentRDSE2
dwCurrentRDSE3
dwCurrentRDSE3
dwCurrentRxDescAddr
dwCurrentRxDescAddr
dwCurrentTDSE0
dwCurrentTDSE0
dwCurrentTDSE1
dwCurrentTDSE1
dwCurrentTDSE2
dwCurrentTDSE2
dwCurrentTDSE3
dwCurrentTDSE3
dwCurrentTxDescAddr
dwCurrentTxDescAddr
dwCurrRxDMAPtr
dwCurrRxDMAPtr
dwCurrTxDMAPtr
dwCurrTxDMAPtr
dwNextRDSE0
dwNextRDSE0
dwNextRDSE1
dwNextRDSE1
dwNextRDSE2
dwNextRDSE2
dwNextRDSE3
dwNextRDSE3
dwNextTDSE0
dwNextTDSE0
dwNextTDSE1
dwNextTDSE1
dwNextTDSE2
dwNextTDSE2
dwNextTDSE3
dwNextTDSE3
DWORD_REG_BITS_IS_ON(x,p)
DWORD_REG_BITS_IS_ON(x,p)
DWORD_REG_BITS_OFF(x,p)
DWORD_REG_BITS_OFF(x,p)
DWORD_REG_BITS_ON(x,p)
DWORD_REG_BITS_ON(x,p)
DWORD_REG_BITS_SET(x,m,p)
DWORD_REG_BITS_SET(x,m,p)
DXE_SERVICES
DXE_SERVICES_REVISION
DXE_SERVICES_SIGNATURE

E

E	A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 　[Top]

e1000.c
e1000.c
e1000.h
e1000.h
e1000_1000t_rx_status
e1000_1000t_rx_status
e1000_10bt_ext_dist_enable
e1000_10bt_ext_dist_enable
E1000_82542_2_0_REV_ID
E1000_82542_2_0_REV_ID
E1000_82542_2_1_REV_ID
E1000_82542_2_1_REV_ID
E1000_82542_AIT
E1000_82542_AIT
E1000_82542_ALGNERRC
E1000_82542_ALGNERRC
E1000_82542_BPRC
E1000_82542_BPRC
E1000_82542_BPTC
E1000_82542_BPTC
E1000_82542_CEXTERR
E1000_82542_CEXTERR
E1000_82542_COLC
E1000_82542_COLC
E1000_82542_CPUVEC
E1000_82542_CPUVEC
E1000_82542_CRCERRS
E1000_82542_CRCERRS
E1000_82542_CTRL
E1000_82542_CTRL
E1000_82542_CTRL_DUP
E1000_82542_CTRL_DUP
E1000_82542_CTRL_EXT
E1000_82542_CTRL_EXT
E1000_82542_DC
E1000_82542_DC
E1000_82542_DCA_RXCTRL(_n)
E1000_82542_DCA_RXCTRL(_n)
E1000_82542_ECOL
E1000_82542_ECOL
E1000_82542_EEARBC
E1000_82542_EEARBC
E1000_82542_EECD
E1000_82542_EECD
E1000_82542_EEMNGCTL
E1000_82542_EEMNGCTL
E1000_82542_EEMNGCTL
E1000_82542_EEMNGCTL
E1000_82542_EERD
E1000_82542_EERD
E1000_82542_EEWR
E1000_82542_EEWR
E1000_82542_ERT
E1000_82542_ERT
E1000_82542_EXTCNF_CTRL
E1000_82542_EXTCNF_CTRL
E1000_82542_EXTCNF_SIZE
E1000_82542_EXTCNF_SIZE
E1000_82542_FACTPS
E1000_82542_FACTPS
E1000_82542_FCAH
E1000_82542_FCAH
E1000_82542_FCAL
E1000_82542_FCAL
E1000_82542_FCRTH
E1000_82542_FCRTH
E1000_82542_FCRTL
E1000_82542_FCRTL
E1000_82542_FCRUC
E1000_82542_FCRUC
E1000_82542_FCT
E1000_82542_FCT
E1000_82542_FCTTV
E1000_82542_FCTTV
E1000_82542_FEXTNVM
E1000_82542_FEXTNVM
E1000_82542_FFLT
E1000_82542_FFLT
E1000_82542_FFLT_DBG
E1000_82542_FFLT_DBG
E1000_82542_FFMT
E1000_82542_FFMT
E1000_82542_FFVT
E1000_82542_FFVT
E1000_82542_FLA
E1000_82542_FLA
E1000_82542_FLASHT
E1000_82542_FLASHT
E1000_82542_FLOP
E1000_82542_FLOP
E1000_82542_FLSWCNT
E1000_82542_FLSWCNT
E1000_82542_FLSWCTL
E1000_82542_FLSWCTL
E1000_82542_FLSWDATA
E1000_82542_FLSWDATA
E1000_82542_FWSM
E1000_82542_FWSM
E1000_82542_GCR
E1000_82542_GCR
E1000_82542_GORCH
E1000_82542_GORCH
E1000_82542_GORCL
E1000_82542_GORCL
E1000_82542_GOTCH
E1000_82542_GOTCH
E1000_82542_GOTCL
E1000_82542_GOTCL
E1000_82542_GPRC
E1000_82542_GPRC
E1000_82542_GPTC
E1000_82542_GPTC
E1000_82542_GSCL_1
E1000_82542_GSCL_1
E1000_82542_GSCL_2
E1000_82542_GSCL_2
E1000_82542_GSCL_3
E1000_82542_GSCL_3
E1000_82542_GSCL_4
E1000_82542_GSCL_4
E1000_82542_HICR
E1000_82542_HICR
E1000_82542_HOST_IF
E1000_82542_HOST_IF
E1000_82542_IAC
E1000_82542_IAC
E1000_82542_IAM
E1000_82542_IAM
E1000_82542_ICR
E1000_82542_ICR
E1000_82542_ICRXATC
E1000_82542_ICRXATC
E1000_82542_ICRXDMTC
E1000_82542_ICRXDMTC
E1000_82542_ICRXOC
E1000_82542_ICRXOC
E1000_82542_ICRXPTC
E1000_82542_ICRXPTC
E1000_82542_ICS
E1000_82542_ICS
E1000_82542_ICTXATC
E1000_82542_ICTXATC
E1000_82542_ICTXPTC
E1000_82542_ICTXPTC
E1000_82542_ICTXQEC
E1000_82542_ICTXQEC
E1000_82542_ICTXQMTC
E1000_82542_ICTXQMTC
E1000_82542_IMC
E1000_82542_IMC
E1000_82542_IMS
E1000_82542_IMS
E1000_82542_IP4AT
E1000_82542_IP4AT
E1000_82542_IP6AT
E1000_82542_IP6AT
E1000_82542_IPAV
E1000_82542_IPAV
E1000_82542_ITR
E1000_82542_ITR
E1000_82542_KABGTXD
E1000_82542_KABGTXD
E1000_82542_KUMCTRLSTA
E1000_82542_KUMCTRLSTA
E1000_82542_LATECOL
E1000_82542_LATECOL
E1000_82542_LEDCTL
E1000_82542_LEDCTL
E1000_82542_MANC
E1000_82542_MANC
E1000_82542_MANC2H
E1000_82542_MANC2H
E1000_82542_MCC
E1000_82542_MCC
E1000_82542_MDIC
E1000_82542_MDIC
E1000_82542_MGTPDC
E1000_82542_MGTPDC
E1000_82542_MGTPRC
E1000_82542_MGTPRC
E1000_82542_MGTPTC
E1000_82542_MGTPTC
E1000_82542_MPC
E1000_82542_MPC
E1000_82542_MPRC
E1000_82542_MPRC
E1000_82542_MPTC
E1000_82542_MPTC
E1000_82542_MRQC
E1000_82542_MRQC
E1000_82542_MTA
E1000_82542_MTA
E1000_82542_PBA
E1000_82542_PBA
E1000_82542_PBS
E1000_82542_PBS
E1000_82542_PHY_CTRL
E1000_82542_PHY_CTRL
E1000_82542_PRC1023
E1000_82542_PRC1023
E1000_82542_PRC127
E1000_82542_PRC127
E1000_82542_PRC1522
E1000_82542_PRC1522
E1000_82542_PRC255
E1000_82542_PRC255
E1000_82542_PRC511
E1000_82542_PRC511
E1000_82542_PRC64
E1000_82542_PRC64
E1000_82542_PSRCTL
E1000_82542_PSRCTL
E1000_82542_PTC1023
E1000_82542_PTC1023
E1000_82542_PTC127
E1000_82542_PTC127
E1000_82542_PTC1522
E1000_82542_PTC1522
E1000_82542_PTC255
E1000_82542_PTC255
E1000_82542_PTC511
E1000_82542_PTC511
E1000_82542_PTC64
E1000_82542_PTC64
E1000_82542_RA
E1000_82542_RA
E1000_82542_RADV
E1000_82542_RADV
E1000_82542_RAID
E1000_82542_RAID
E1000_82542_RCTL
E1000_82542_RCTL
E1000_82542_RDBAH
E1000_82542_RDBAH
E1000_82542_RDBAH0
E1000_82542_RDBAH0
E1000_82542_RDBAH1
E1000_82542_RDBAH1
E1000_82542_RDBAH2	RX Desc Base High Queue 2 - RW
E1000_82542_RDBAH2	RX Desc Base High Queue 2 - RW
E1000_82542_RDBAH3	RX Desc Base High Queue 3 - RW
E1000_82542_RDBAH3	RX Desc Base High Queue 3 - RW
E1000_82542_RDBAL
E1000_82542_RDBAL
E1000_82542_RDBAL0
E1000_82542_RDBAL0
E1000_82542_RDBAL1
E1000_82542_RDBAL1
E1000_82542_RDBAL2	RX Desc Base Low Queue 2 - RW
E1000_82542_RDBAL2	RX Desc Base Low Queue 2 - RW
E1000_82542_RDBAL3	RX Desc Low Queue 3 - RW
E1000_82542_RDBAL3	RX Desc Low Queue 3 - RW
E1000_82542_RDH
E1000_82542_RDH
E1000_82542_RDH0
E1000_82542_RDH0
E1000_82542_RDH1
E1000_82542_RDH1
E1000_82542_RDH2	RX Desc Head Queue 2 - RW
E1000_82542_RDH2	RX Desc Head Queue 2 - RW
E1000_82542_RDH3	RX Desc Head Queue 3 - RW
E1000_82542_RDH3	RX Desc Head Queue 3 - RW
E1000_82542_RDLEN
E1000_82542_RDLEN
E1000_82542_RDLEN0
E1000_82542_RDLEN0
E1000_82542_RDLEN1
E1000_82542_RDLEN1
E1000_82542_RDLEN2	RX Desc Length Queue 2 - RW
E1000_82542_RDLEN2	RX Desc Length Queue 2 - RW
E1000_82542_RDLEN3	RX Desc Length Queue 3 - RW
E1000_82542_RDLEN3	RX Desc Length Queue 3 - RW
E1000_82542_RDT
E1000_82542_RDT
E1000_82542_RDT0
E1000_82542_RDT0
E1000_82542_RDT1
E1000_82542_RDT1
E1000_82542_RDT2	RX Desc Tail Queue 2 - RW
E1000_82542_RDT2	RX Desc Tail Queue 2 - RW
E1000_82542_RDT3	RX Desc Tail Queue 3 - RW
E1000_82542_RDT3	RX Desc Tail Queue 3 - RW
E1000_82542_RDTR
E1000_82542_RDTR
E1000_82542_RDTR0
E1000_82542_RDTR0
E1000_82542_RDTR1
E1000_82542_RDTR1
E1000_82542_RETA
E1000_82542_RETA
E1000_82542_RFC
E1000_82542_RFC
E1000_82542_RFCTL
E1000_82542_RFCTL
E1000_82542_RJC
E1000_82542_RJC
E1000_82542_RLEC
E1000_82542_RLEC
E1000_82542_RNBC
E1000_82542_RNBC
E1000_82542_ROC
E1000_82542_ROC
E1000_82542_RSRPD
E1000_82542_RSRPD
E1000_82542_RSSIM
E1000_82542_RSSIM
E1000_82542_RSSIR
E1000_82542_RSSIR
E1000_82542_RSSRK
E1000_82542_RSSRK
E1000_82542_RUC
E1000_82542_RUC
E1000_82542_RXCSUM
E1000_82542_RXCSUM
E1000_82542_RXCW
E1000_82542_RXCW
E1000_82542_RXDCTL
E1000_82542_RXDCTL
E1000_82542_RXDCTL1
E1000_82542_RXDCTL1
E1000_82542_RXERRC
E1000_82542_RXERRC
E1000_82542_SCC
E1000_82542_SCC
E1000_82542_SCTL
E1000_82542_SCTL
E1000_82542_SEC
E1000_82542_SEC
E1000_82542_SRRCTL(_n)	Split and Replication
E1000_82542_SRRCTL(_n)	Split and Replication
E1000_82542_STATUS
E1000_82542_STATUS
E1000_82542_SW_FW_SYNC
E1000_82542_SW_FW_SYNC
E1000_82542_SWSM
E1000_82542_SWSM
E1000_82542_SYMERRS
E1000_82542_SYMERRS
E1000_82542_TADV
E1000_82542_TADV
E1000_82542_TARC0
E1000_82542_TARC0
E1000_82542_TARC1
E1000_82542_TARC1
E1000_82542_TBT
E1000_82542_TBT
E1000_82542_TCTL
E1000_82542_TCTL
E1000_82542_TCTL_EXT
E1000_82542_TCTL_EXT
E1000_82542_TDBAH
E1000_82542_TDBAH
E1000_82542_TDBAH1
E1000_82542_TDBAH1
E1000_82542_TDBAL
E1000_82542_TDBAL
E1000_82542_TDBAL1
E1000_82542_TDBAL1
E1000_82542_TDFH
E1000_82542_TDFH
E1000_82542_TDFHS
E1000_82542_TDFHS
E1000_82542_TDFPC
E1000_82542_TDFPC
E1000_82542_TDFT
E1000_82542_TDFT
E1000_82542_TDFTS
E1000_82542_TDFTS
E1000_82542_TDH
E1000_82542_TDH
E1000_82542_TDH1
E1000_82542_TDH1
E1000_82542_TDLEN
E1000_82542_TDLEN
E1000_82542_TDLEN1
E1000_82542_TDLEN1
E1000_82542_TDT
E1000_82542_TDT
E1000_82542_TDT1
E1000_82542_TDT1
E1000_82542_TIDV
E1000_82542_TIDV
E1000_82542_TIPG
E1000_82542_TIPG
E1000_82542_TNCRS
E1000_82542_TNCRS
E1000_82542_TORH
E1000_82542_TORH
E1000_82542_TORL
E1000_82542_TORL
E1000_82542_TOTH
E1000_82542_TOTH
E1000_82542_TOTL
E1000_82542_TOTL
E1000_82542_TPR
E1000_82542_TPR
E1000_82542_TPT
E1000_82542_TPT
E1000_82542_TSCTC
E1000_82542_TSCTC
E1000_82542_TSCTFC
E1000_82542_TSCTFC
E1000_82542_TSPMT
E1000_82542_TSPMT
E1000_82542_TXCW
E1000_82542_TXCW
E1000_82542_TXDCTL
E1000_82542_TXDCTL
E1000_82542_TXDCTL1
E1000_82542_TXDCTL1
E1000_82542_TXDMAC
E1000_82542_TXDMAC
E1000_82542_VET
E1000_82542_VET
E1000_82542_VFTA
E1000_82542_VFTA
E1000_82542_WUC
E1000_82542_WUC
E1000_82542_WUFC
E1000_82542_WUFC
E1000_82542_WUPL
E1000_82542_WUPL
E1000_82542_WUPM
E1000_82542_WUPM
E1000_82542_WUS
E1000_82542_WUS
E1000_82542_XOFFRXC
E1000_82542_XOFFRXC
E1000_82542_XOFFTXC
E1000_82542_XOFFTXC
E1000_82542_XONRXC
E1000_82542_XONRXC
E1000_82542_XONTXC
E1000_82542_XONTXC
e1000_acquire_eeprom	Prepares EEPROM for access
e1000_acquire_eeprom	Prepares EEPROM for access
e1000_adapter
e1000_adapter
e1000_adjust_serdes_amplitude	Adjust SERDES output amplitude based on EEPROM setting.
e1000_adjust_serdes_amplitude	Adjust SERDES output amplitude based on EEPROM setting.
E1000_AIT	Adaptive Interframe Spacing Throttle - RW
E1000_AIT	Adaptive Interframe Spacing Throttle - RW
E1000_ALGNERRC	Alignment Error Count - R/clr
E1000_ALGNERRC	Alignment Error Count - R/clr
e1000_align_type
e1000_align_type
e1000_arc_subsystem_valid
e1000_arc_subsystem_valid
e1000_auto_x_mode
e1000_auto_x_mode
e1000_blink_led_start	Used on 82571 and later Si that has LED blink bits.
e1000_blink_led_start	Used on 82571 and later Si that has LED blink bits.
E1000_BLK_PHY_RESET
E1000_BLK_PHY_RESET
E1000_BPRC	Broadcast Packets RX Count - R/clr
E1000_BPRC	Broadcast Packets RX Count - R/clr
E1000_BPTC	Broadcast Packets TX Count - R/clr
E1000_BPTC	Broadcast Packets TX Count - R/clr
e1000_buffer
e1000_buffer
e1000_bus_speed
e1000_bus_speed
e1000_bus_type
e1000_bus_type
e1000_bus_width
e1000_bus_width
E1000_BYTE_SWAP_WORD(_value)
E1000_BYTE_SWAP_WORD(_value)
e1000_cable_length
e1000_cable_length
e1000_calculate_mng_checksum	This function calculates the checksum.
e1000_calculate_mng_checksum	This function calculates the checksum.
E1000_CEXTERR	Carrier Extension Error Count - R/clr
E1000_CEXTERR	Carrier Extension Error Count - R/clr
e1000_check_downshift	Check if Downshift occured
e1000_check_downshift	Check if Downshift occured
e1000_check_for_link	Checks to see if the link status of the hardware has changed.
e1000_check_for_link	Checks to see if the link status of the hardware has changed.
e1000_check_mng_mode	This function checks the mode of the firmware.
e1000_check_mng_mode	This function checks the mode of the firmware.
e1000_check_phy_reset_block	Checks if PHY reset is blocked due to SOL/IDER session, for example.
e1000_check_phy_reset_block	Checks if PHY reset is blocked due to SOL/IDER session, for example.
e1000_check_polarity	Check the cable polarity
e1000_check_polarity	Check the cable polarity
e1000_cleanup_led	Restores the saved state of the SW controlable LED.
e1000_cleanup_led	Restores the saved state of the SW controlable LED.
e1000_clear_hw_cntrs	Clears all hardware statistics counters.
e1000_clear_hw_cntrs	Clears all hardware statistics counters.
e1000_clear_vfta	Clears the VLAN filer table
e1000_clear_vfta	Clears the VLAN filer table
e1000_close	Functions that implement the gPXE driver API *
e1000_close	Functions that implement the gPXE driver API *
E1000_COLC	Collision Count - R/clr
E1000_COLC	Collision Count - R/clr
E1000_COLD_SHIFT
E1000_COLD_SHIFT
E1000_COLLISION_DISTANCE
E1000_COLLISION_DISTANCE
E1000_COLLISION_DISTANCE_82542
E1000_COLLISION_DISTANCE_82542
E1000_COLLISION_THRESHOLD
E1000_COLLISION_THRESHOLD
e1000_commit_shadow_ram	Flushes the cached eeprom to NVM. This is done by saving the modified values
e1000_commit_shadow_ram	Flushes the cached eeprom to NVM. This is done by saving the modified values
e1000_config_collision_dist	Sets the collision distance in the Transmit Control register
e1000_config_collision_dist	Sets the collision distance in the Transmit Control register
e1000_config_dsp_after_link_change	82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
e1000_config_dsp_after_link_change	82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
e1000_config_fc_after_link_up	Configures flow control settings after link is established
e1000_config_fc_after_link_up	Configures flow control settings after link is established
e1000_config_mac_to_phy	Sets MAC speed and duplex settings to reflect the those in the PHY
e1000_config_mac_to_phy	Sets MAC speed and duplex settings to reflect the those in the PHY
e1000_configure_kmrn_for_10_100	Configure the MAC-to-PHY interface for 10/100Mbps
e1000_configure_kmrn_for_10_100	Configure the MAC-to-PHY interface for 10/100Mbps
e1000_configure_kmrn_for_1000
e1000_configure_kmrn_for_1000
e1000_configure_rx	e1000_configure_rx - Configure 8254x Receive Unit after Reset
e1000_configure_rx	e1000_configure_rx - Configure 8254x Receive Unit after Reset
e1000_configure_tx	e1000_configure_tx - Configure 8254x Transmit Unit after Reset
e1000_configure_tx	e1000_configure_tx - Configure 8254x Transmit Unit after Reset
e1000_context_desc
e1000_context_desc
E1000_CONTEXT_DESC(R, i)
E1000_CONTEXT_DESC(R, i)
e1000_copper_link_autoneg	Setup auto-negotiation and flow control advertisements,
e1000_copper_link_autoneg	Setup auto-negotiation and flow control advertisements,
e1000_copper_link_ggp_setup	Copper link setup for e1000_phy_gg82563 series.
e1000_copper_link_ggp_setup	Copper link setup for e1000_phy_gg82563 series.
e1000_copper_link_igp_setup	Copper link setup for e1000_phy_igp series.
e1000_copper_link_igp_setup	Copper link setup for e1000_phy_igp series.
e1000_copper_link_mgp_setup	Copper link setup for e1000_phy_m88 series.
e1000_copper_link_mgp_setup	Copper link setup for e1000_phy_m88 series.
e1000_copper_link_postconfig	Config the MAC and the PHY after link is up.
e1000_copper_link_postconfig	Config the MAC and the PHY after link is up.
e1000_copper_link_preconfig	Make sure we have a valid PHY and change PHY mode before link setup.
e1000_copper_link_preconfig	Make sure we have a valid PHY and change PHY mode before link setup.
E1000_CPUVEC	CPU Vector Register - RW
E1000_CPUVEC	CPU Vector Register - RW
E1000_CRCERRS	CRC Error Count - R/clr
E1000_CRCERRS	CRC Error Count - R/clr
E1000_CRTL_EXT_PB_PAREN	packet buffer parity error detection enabled
E1000_CRTL_EXT_PB_PAREN	packet buffer parity error detection enabled
E1000_CT_SHIFT
E1000_CT_SHIFT
E1000_CTRL	Device Control - RW
E1000_CTRL	Device Control - RW
E1000_CTRL_ASDE	Auto-speed detect enable
E1000_CTRL_ASDE	Auto-speed detect enable
E1000_CTRL_BEM	Endian Mode.0=little,1=big
E1000_CTRL_BEM	Endian Mode.0=little,1=big
E1000_CTRL_BEM32	Big Endian 32 mode
E1000_CTRL_BEM32	Big Endian 32 mode
E1000_CTRL_D_UD_EN	Dock/Undock enable
E1000_CTRL_D_UD_EN	Dock/Undock enable
E1000_CTRL_D_UD_POLARITY	Defined polarity of Dock/Undock indication in SDP[0]
E1000_CTRL_D_UD_POLARITY	Defined polarity of Dock/Undock indication in SDP[0]
E1000_CTRL_DUP	Device Control Duplicate (Shadow) - RW
E1000_CTRL_DUP	Device Control Duplicate (Shadow) - RW
E1000_CTRL_EXT	Extended Device Control - RW
E1000_CTRL_EXT	Extended Device Control - RW
E1000_CTRL_EXT_ASDCHK	Initiate an ASD sequence
E1000_CTRL_EXT_ASDCHK	Initiate an ASD sequence
E1000_CTRL_EXT_DF_PAREN	descriptor FIFO parity error detection enable
E1000_CTRL_EXT_DF_PAREN	descriptor FIFO parity error detection enable
E1000_CTRL_EXT_DRV_LOAD	Driver loaded bit for FW
E1000_CTRL_EXT_DRV_LOAD	Driver loaded bit for FW
E1000_CTRL_EXT_EE_RST	Reinitialize from EEPROM
E1000_CTRL_EXT_EE_RST	Reinitialize from EEPROM
E1000_CTRL_EXT_GHOST_PAREN
E1000_CTRL_EXT_GHOST_PAREN
E1000_CTRL_EXT_GPI0_EN	Maps SDP4 to GPI0
E1000_CTRL_EXT_GPI0_EN	Maps SDP4 to GPI0
E1000_CTRL_EXT_GPI1_EN	Maps SDP5 to GPI1
E1000_CTRL_EXT_GPI1_EN	Maps SDP5 to GPI1
E1000_CTRL_EXT_GPI2_EN	Maps SDP6 to GPI2
E1000_CTRL_EXT_GPI2_EN	Maps SDP6 to GPI2
E1000_CTRL_EXT_GPI3_EN	Maps SDP7 to GPI3
E1000_CTRL_EXT_GPI3_EN	Maps SDP7 to GPI3
E1000_CTRL_EXT_IAME	Interrupt acknowledge Auto-mask
E1000_CTRL_EXT_IAME	Interrupt acknowledge Auto-mask
E1000_CTRL_EXT_INT_TIMER_CLR	Clear Interrupt timers after IMS clear
E1000_CTRL_EXT_INT_TIMER_CLR	Clear Interrupt timers after IMS clear
E1000_CTRL_EXT_IPS	Invert Power State
E1000_CTRL_EXT_IPS	Invert Power State
E1000_CTRL_EXT_LINK_EN	enable link status from external LINK_0 and LINK_1 pins
E1000_CTRL_EXT_LINK_EN	enable link status from external LINK_0 and LINK_1 pins
E1000_CTRL_EXT_LINK_MODE_GMII
E1000_CTRL_EXT_LINK_MODE_GMII
E1000_CTRL_EXT_LINK_MODE_KMRN
E1000_CTRL_EXT_LINK_MODE_KMRN
E1000_CTRL_EXT_LINK_MODE_MASK
E1000_CTRL_EXT_LINK_MODE_MASK
E1000_CTRL_EXT_LINK_MODE_SERDES
E1000_CTRL_EXT_LINK_MODE_SERDES
E1000_CTRL_EXT_LINK_MODE_SGMII
E1000_CTRL_EXT_LINK_MODE_SGMII
E1000_CTRL_EXT_LINK_MODE_TBI
E1000_CTRL_EXT_LINK_MODE_TBI
E1000_CTRL_EXT_PHY_INT
E1000_CTRL_EXT_PHY_INT
E1000_CTRL_EXT_PHYINT_EN
E1000_CTRL_EXT_PHYINT_EN
E1000_CTRL_EXT_RO_DIS	Relaxed Ordering disable
E1000_CTRL_EXT_RO_DIS	Relaxed Ordering disable
E1000_CTRL_EXT_SDP4_DATA	Value of SW Defineable Pin 4
E1000_CTRL_EXT_SDP4_DATA	Value of SW Defineable Pin 4
E1000_CTRL_EXT_SDP4_DIR	Direction of SDP4 0=in 1=out
E1000_CTRL_EXT_SDP4_DIR	Direction of SDP4 0=in 1=out
E1000_CTRL_EXT_SDP5_DATA	Value of SW Defineable Pin 5
E1000_CTRL_EXT_SDP5_DATA	Value of SW Defineable Pin 5
E1000_CTRL_EXT_SDP5_DIR	Direction of SDP5 0=in 1=out
E1000_CTRL_EXT_SDP5_DIR	Direction of SDP5 0=in 1=out
E1000_CTRL_EXT_SDP6_DATA	Value of SW Defineable Pin 6
E1000_CTRL_EXT_SDP6_DATA	Value of SW Defineable Pin 6
E1000_CTRL_EXT_SDP6_DIR	Direction of SDP6 0=in 1=out
E1000_CTRL_EXT_SDP6_DIR	Direction of SDP6 0=in 1=out
E1000_CTRL_EXT_SDP7_DATA	Value of SW Defineable Pin 7
E1000_CTRL_EXT_SDP7_DATA	Value of SW Defineable Pin 7
E1000_CTRL_EXT_SDP7_DIR	Direction of SDP7 0=in 1=out
E1000_CTRL_EXT_SDP7_DIR	Direction of SDP7 0=in 1=out
E1000_CTRL_EXT_SPD_BYPS	Speed Select Bypass
E1000_CTRL_EXT_SPD_BYPS	Speed Select Bypass
E1000_CTRL_EXT_WR_WMARK_256
E1000_CTRL_EXT_WR_WMARK_256
E1000_CTRL_EXT_WR_WMARK_320
E1000_CTRL_EXT_WR_WMARK_320
E1000_CTRL_EXT_WR_WMARK_384
E1000_CTRL_EXT_WR_WMARK_384
E1000_CTRL_EXT_WR_WMARK_448
E1000_CTRL_EXT_WR_WMARK_448
E1000_CTRL_EXT_WR_WMARK_MASK
E1000_CTRL_EXT_WR_WMARK_MASK
E1000_CTRL_FD	Full duplex.0=half; 1=full
E1000_CTRL_FD	Full duplex.0=half; 1=full
E1000_CTRL_FORCE_PHY_RESET	Reset both PHY ports, through PHYRST_N pin
E1000_CTRL_FORCE_PHY_RESET	Reset both PHY ports, through PHYRST_N pin
E1000_CTRL_FRCDPX	Force Duplex
E1000_CTRL_FRCDPX	Force Duplex
E1000_CTRL_FRCSPD	Force Speed
E1000_CTRL_FRCSPD	Force Speed
E1000_CTRL_GIO_MASTER_DISABLE	Blocks new Master requests
E1000_CTRL_GIO_MASTER_DISABLE	Blocks new Master requests
E1000_CTRL_ILOS	Invert Loss-Of Signal
E1000_CTRL_ILOS	Invert Loss-Of Signal
E1000_CTRL_LRST	Link reset. 0=normal,1=reset
E1000_CTRL_LRST	Link reset. 0=normal,1=reset
E1000_CTRL_MDC
E1000_CTRL_MDC
E1000_CTRL_MDC_DIR
E1000_CTRL_MDC_DIR
E1000_CTRL_MDIO
E1000_CTRL_MDIO
E1000_CTRL_MDIO_DIR
E1000_CTRL_MDIO_DIR
E1000_CTRL_PHY_RESET
E1000_CTRL_PHY_RESET
E1000_CTRL_PHY_RESET_DIR
E1000_CTRL_PHY_RESET_DIR
E1000_CTRL_PHY_RESET_DIR4
E1000_CTRL_PHY_RESET_DIR4
E1000_CTRL_PHY_RESET4
E1000_CTRL_PHY_RESET4
E1000_CTRL_PHY_RST	PHY Reset
E1000_CTRL_PHY_RST	PHY Reset
E1000_CTRL_PRIOR	Priority on PCI. 0=rx,1=fair
E1000_CTRL_PRIOR	Priority on PCI. 0=rx,1=fair
E1000_CTRL_RFCE	Receive Flow Control enable
E1000_CTRL_RFCE	Receive Flow Control enable
E1000_CTRL_RST	Global reset
E1000_CTRL_RST	Global reset
E1000_CTRL_RTE	Routing tag enable
E1000_CTRL_RTE	Routing tag enable
E1000_CTRL_SLE	Serial Link on 0=dis,1=en
E1000_CTRL_SLE	Serial Link on 0=dis,1=en
E1000_CTRL_SLU	Set link up (Force Link)
E1000_CTRL_SLU	Set link up (Force Link)
E1000_CTRL_SPD_10	Force 10Mb
E1000_CTRL_SPD_10	Force 10Mb
E1000_CTRL_SPD_100	Force 100Mb
E1000_CTRL_SPD_100	Force 100Mb
E1000_CTRL_SPD_1000	Force 1Gb
E1000_CTRL_SPD_1000	Force 1Gb
E1000_CTRL_SPD_SEL	Speed Select Mask
E1000_CTRL_SPD_SEL	Speed Select Mask
E1000_CTRL_SW2FW_INT	Initiate an interrupt to manageability engine
E1000_CTRL_SW2FW_INT	Initiate an interrupt to manageability engine
E1000_CTRL_SWDPIN0	SWDPIN 0 value
E1000_CTRL_SWDPIN0	SWDPIN 0 value
E1000_CTRL_SWDPIN1	SWDPIN 1 value
E1000_CTRL_SWDPIN1	SWDPIN 1 value
E1000_CTRL_SWDPIN2	SWDPIN 2 value
E1000_CTRL_SWDPIN2	SWDPIN 2 value
E1000_CTRL_SWDPIN3	SWDPIN 3 value
E1000_CTRL_SWDPIN3	SWDPIN 3 value
E1000_CTRL_SWDPIO0	SWDPIN 0 Input or output
E1000_CTRL_SWDPIO0	SWDPIN 0 Input or output
E1000_CTRL_SWDPIO1	SWDPIN 1 input or output
E1000_CTRL_SWDPIO1	SWDPIN 1 input or output
E1000_CTRL_SWDPIO2	SWDPIN 2 input or output
E1000_CTRL_SWDPIO2	SWDPIN 2 input or output
E1000_CTRL_SWDPIO3	SWDPIN 3 input or output
E1000_CTRL_SWDPIO3	SWDPIN 3 input or output
E1000_CTRL_TFCE	Transmit flow control enable
E1000_CTRL_TFCE	Transmit flow control enable
E1000_CTRL_TME	Test mode. 0=normal,1=test
E1000_CTRL_TME	Test mode. 0=normal,1=test
E1000_CTRL_VME	IEEE VLAN mode enable
E1000_CTRL_VME	IEEE VLAN mode enable
e1000_data_desc
e1000_data_desc
E1000_DC	Defer Count - R/clr
E1000_DC	Defer Count - R/clr
E1000_DESC_UNUSED(R)
E1000_DESC_UNUSED(R)
e1000_detect_gig_phy	Probes the expected PHY address for known PHY IDs
e1000_detect_gig_phy	Probes the expected PHY address for known PHY IDs
E1000_DEV_ID_80003ES2LAN_COPPER
E1000_DEV_ID_80003ES2LAN_COPPER
E1000_DEV_ID_80003ES2LAN_COPPER
E1000_DEV_ID_80003ES2LAN_COPPER
E1000_DEV_ID_80003ES2LAN_SERDES
E1000_DEV_ID_80003ES2LAN_SERDES
E1000_DEV_ID_80003ES2LAN_SERDES
E1000_DEV_ID_80003ES2LAN_SERDES
E1000_DEV_ID_82540EM
E1000_DEV_ID_82540EM
E1000_DEV_ID_82540EM_LOM
E1000_DEV_ID_82540EM_LOM
E1000_DEV_ID_82540EP
E1000_DEV_ID_82540EP
E1000_DEV_ID_82540EP_LOM
E1000_DEV_ID_82540EP_LOM
E1000_DEV_ID_82540EP_LP
E1000_DEV_ID_82540EP_LP
E1000_DEV_ID_82541EI
E1000_DEV_ID_82541EI
E1000_DEV_ID_82541EI_MOBILE
E1000_DEV_ID_82541EI_MOBILE
E1000_DEV_ID_82541ER
E1000_DEV_ID_82541ER
E1000_DEV_ID_82541ER_LOM
E1000_DEV_ID_82541ER_LOM
E1000_DEV_ID_82541GI
E1000_DEV_ID_82541GI
E1000_DEV_ID_82541GI_LF
E1000_DEV_ID_82541GI_LF
E1000_DEV_ID_82541GI_MOBILE
E1000_DEV_ID_82541GI_MOBILE
E1000_DEV_ID_82542
E1000_DEV_ID_82542
E1000_DEV_ID_82543GC_COPPER
E1000_DEV_ID_82543GC_COPPER
E1000_DEV_ID_82543GC_FIBER
E1000_DEV_ID_82543GC_FIBER
E1000_DEV_ID_82544EI_COPPER
E1000_DEV_ID_82544EI_COPPER
E1000_DEV_ID_82544EI_FIBER
E1000_DEV_ID_82544EI_FIBER
E1000_DEV_ID_82544GC_COPPER
E1000_DEV_ID_82544GC_COPPER
E1000_DEV_ID_82544GC_LOM
E1000_DEV_ID_82544GC_LOM
E1000_DEV_ID_82545EM_COPPER
E1000_DEV_ID_82545EM_COPPER
E1000_DEV_ID_82545EM_FIBER
E1000_DEV_ID_82545EM_FIBER
E1000_DEV_ID_82545GM_COPPER
E1000_DEV_ID_82545GM_COPPER
E1000_DEV_ID_82545GM_FIBER
E1000_DEV_ID_82545GM_FIBER
E1000_DEV_ID_82545GM_SERDES
E1000_DEV_ID_82545GM_SERDES
E1000_DEV_ID_82546EB_COPPER
E1000_DEV_ID_82546EB_COPPER
E1000_DEV_ID_82546EB_FIBER
E1000_DEV_ID_82546EB_FIBER
E1000_DEV_ID_82546EB_QUAD_COPPE
E1000_DEV_ID_82546EB_QUAD_COPPE
E1000_DEV_ID_82546GB_COPPER
E1000_DEV_ID_82546GB_COPPER
E1000_DEV_ID_82546GB_FIBER
E1000_DEV_ID_82546GB_FIBER
E1000_DEV_ID_82546GB_PCIE
E1000_DEV_ID_82546GB_PCIE
E1000_DEV_ID_82546GB_QUAD_COPPE
E1000_DEV_ID_82546GB_QUAD_COPPE
E1000_DEV_ID_82546GB_QUAD_COPPE
E1000_DEV_ID_82546GB_QUAD_COPPE
E1000_DEV_ID_82546GB_SERDES
E1000_DEV_ID_82546GB_SERDES
E1000_DEV_ID_82547EI
E1000_DEV_ID_82547EI
E1000_DEV_ID_82547EI_MOBILE
E1000_DEV_ID_82547EI_MOBILE
E1000_DEV_ID_82547GI
E1000_DEV_ID_82547GI
E1000_DEV_ID_82571EB_COPPER
E1000_DEV_ID_82571EB_COPPER
E1000_DEV_ID_82571EB_FIBER
E1000_DEV_ID_82571EB_FIBER
E1000_DEV_ID_82571EB_QUAD_COPPE
E1000_DEV_ID_82571EB_QUAD_COPPE
E1000_DEV_ID_82571EB_QUAD_COPPE
E1000_DEV_ID_82571EB_QUAD_COPPE
E1000_DEV_ID_82571EB_QUAD_FIBER
E1000_DEV_ID_82571EB_QUAD_FIBER
E1000_DEV_ID_82571EB_SERDES
E1000_DEV_ID_82571EB_SERDES
E1000_DEV_ID_82571EB_SERDES_DUA
E1000_DEV_ID_82571EB_SERDES_DUA
E1000_DEV_ID_82571EB_SERDES_QUA
E1000_DEV_ID_82571EB_SERDES_QUA
E1000_DEV_ID_82572EI
E1000_DEV_ID_82572EI
E1000_DEV_ID_82572EI_COPPER
E1000_DEV_ID_82572EI_COPPER
E1000_DEV_ID_82572EI_FIBER
E1000_DEV_ID_82572EI_FIBER
E1000_DEV_ID_82572EI_SERDES
E1000_DEV_ID_82572EI_SERDES
E1000_DEV_ID_82573E
E1000_DEV_ID_82573E
E1000_DEV_ID_82573E_IAMT
E1000_DEV_ID_82573E_IAMT
E1000_DEV_ID_82573L
E1000_DEV_ID_82573L
E1000_DEV_ID_82576
E1000_DEV_ID_82576
E1000_DEV_ID_ICH8_IFE
E1000_DEV_ID_ICH8_IFE
E1000_DEV_ID_ICH8_IFE_G
E1000_DEV_ID_ICH8_IFE_G
E1000_DEV_ID_ICH8_IFE_GT
E1000_DEV_ID_ICH8_IFE_GT
E1000_DEV_ID_ICH8_IGP_AMT
E1000_DEV_ID_ICH8_IGP_AMT
E1000_DEV_ID_ICH8_IGP_C
E1000_DEV_ID_ICH8_IGP_C
E1000_DEV_ID_ICH8_IGP_M
E1000_DEV_ID_ICH8_IGP_M
E1000_DEV_ID_ICH8_IGP_M_AMT
E1000_DEV_ID_ICH8_IGP_M_AMT
e1000_disable_pciex_master	Disables PCI-Express master access and verifies there are no pending requests
e1000_disable_pciex_master	Disables PCI-Express master access and verifies there are no pending requests
E1000_DISABLE_SERDES_LOOPBACK
E1000_DISABLE_SERDES_LOOPBACK
e1000_downshift
e1000_downshift
e1000_dsp_config
e1000_dsp_config
E1000_ECOL	Excessive Collision Count - R/clr
E1000_ECOL	Excessive Collision Count - R/clr
E1000_EEARBC	EEPROM Auto Read Bus Control
E1000_EEARBC	EEPROM Auto Read Bus Control
E1000_EECD	EEPROM/Flash Control - RW
E1000_EECD	EEPROM/Flash Control - RW
E1000_EECD_ADDR_BITS	EEPROM Addressing bits based on type
E1000_EECD_ADDR_BITS	EEPROM Addressing bits based on type
E1000_EECD_AUPDEN	Enable Autonomous FLASH update
E1000_EECD_AUPDEN	Enable Autonomous FLASH update
E1000_EECD_AUTO_RD	EEPROM Auto Read done
E1000_EECD_AUTO_RD	EEPROM Auto Read done
E1000_EECD_CS	EEPROM Chip Select
E1000_EECD_CS	EEPROM Chip Select
E1000_EECD_DI	EEPROM Data In
E1000_EECD_DI	EEPROM Data In
E1000_EECD_DO	EEPROM Data Out
E1000_EECD_DO	EEPROM Data Out
E1000_EECD_FLUPD	Update FLASH
E1000_EECD_FLUPD	Update FLASH
E1000_EECD_FWE_DIS	Disable FLASH writes
E1000_EECD_FWE_DIS	Disable FLASH writes
E1000_EECD_FWE_EN	Enable FLASH writes
E1000_EECD_FWE_EN	Enable FLASH writes
E1000_EECD_FWE_MASK
E1000_EECD_FWE_MASK
E1000_EECD_FWE_SHIFT
E1000_EECD_FWE_SHIFT
E1000_EECD_GNT	EEPROM Access Grant
E1000_EECD_GNT	EEPROM Access Grant
E1000_EECD_INITSRAM	Initialize Shadow RAM
E1000_EECD_INITSRAM	Initialize Shadow RAM
E1000_EECD_NVADDS	NVM Address Size
E1000_EECD_NVADDS	NVM Address Size
E1000_EECD_PRES	EEPROM Present
E1000_EECD_PRES	EEPROM Present
E1000_EECD_REQ	EEPROM Access Request
E1000_EECD_REQ	EEPROM Access Request
E1000_EECD_SEC1VAL	Sector One Valid
E1000_EECD_SEC1VAL	Sector One Valid
E1000_EECD_SECVAL_SHIFT
E1000_EECD_SECVAL_SHIFT
E1000_EECD_SELSHAD	Select Shadow RAM
E1000_EECD_SELSHAD	Select Shadow RAM
E1000_EECD_SHADV	Shadow RAM Data Valid
E1000_EECD_SHADV	Shadow RAM Data Valid
E1000_EECD_SIZE	EEPROM Size (0=64 word 1=256 word)
E1000_EECD_SIZE	EEPROM Size (0=64 word 1=256 word)
E1000_EECD_SIZE_EX_MASK	EEprom Size
E1000_EECD_SIZE_EX_MASK	EEprom Size
E1000_EECD_SIZE_EX_SHIFT
E1000_EECD_SIZE_EX_SHIFT
E1000_EECD_SK	EEPROM Clock
E1000_EECD_SK	EEPROM Clock
E1000_EECD_TYPE	EEPROM Type (1-SPI, 0-Microwire)
E1000_EECD_TYPE	EEPROM Type (1-SPI, 0-Microwire)
E1000_EEMNGCTL	MNG EEprom Control
E1000_EEMNGCTL	MNG EEprom Control
E1000_EEPROM_82544_APM
E1000_EEPROM_82544_APM
E1000_EEPROM_APME
E1000_EEPROM_APME
E1000_EEPROM_CFG_DONE	MNG config cycle done
E1000_EEPROM_CFG_DONE	MNG config cycle done
E1000_EEPROM_CFG_DONE_PORT_1	...for second port
E1000_EEPROM_CFG_DONE_PORT_1	...for second port
E1000_EEPROM_GRANT_ATTEMPTS	EEPROM # attempts to gain grant
E1000_EEPROM_GRANT_ATTEMPTS	EEPROM # attempts to gain grant
E1000_EEPROM_ICH8_APME
E1000_EEPROM_ICH8_APME
e1000_eeprom_info
e1000_eeprom_info
E1000_EEPROM_LED_LOGIC	Led Logic Word
E1000_EEPROM_LED_LOGIC	Led Logic Word
E1000_EEPROM_POLL_READ	Flag for polling for read complete
E1000_EEPROM_POLL_READ	Flag for polling for read complete
E1000_EEPROM_POLL_WRITE	Flag for polling for write complete
E1000_EEPROM_POLL_WRITE	Flag for polling for write complete
E1000_EEPROM_RW_ADDR_SHIFT	Shift to the address bits
E1000_EEPROM_RW_ADDR_SHIFT	Shift to the address bits
E1000_EEPROM_RW_REG_DATA	Offset to data in EEPROM read/write registers
E1000_EEPROM_RW_REG_DATA	Offset to data in EEPROM read/write registers
E1000_EEPROM_RW_REG_DONE	Offset to READ/WRITE done bit
E1000_EEPROM_RW_REG_DONE	Offset to READ/WRITE done bit
E1000_EEPROM_RW_REG_START	First bit for telling part to start operation
E1000_EEPROM_RW_REG_START	First bit for telling part to start operation
E1000_EEPROM_SWDPIN0	SWDPIN 0 EEPROM Value
E1000_EEPROM_SWDPIN0	SWDPIN 0 EEPROM Value
e1000_eeprom_type
e1000_eeprom_type
E1000_EERD	EEPROM Read - RW
E1000_EERD	EEPROM Read - RW
E1000_EERD_ADDR_MASK	Read Address
E1000_EERD_ADDR_MASK	Read Address
E1000_EERD_ADDR_SHIFT
E1000_EERD_ADDR_SHIFT
E1000_EERD_DATA_MASK	Read Data
E1000_EERD_DATA_MASK	Read Data
E1000_EERD_DATA_SHIFT
E1000_EERD_DATA_SHIFT
E1000_EERD_DONE	Read Done
E1000_EERD_DONE	Read Done
E1000_EERD_START	Start Read
E1000_EERD_START	Start Read
E1000_EEWR	EEPROM Write Register - RW
E1000_EEWR	EEPROM Write Register - RW
e1000_enable_mng_pass_thru	Verifies the hardware needs to allow ARPs to be processed by the host
e1000_enable_mng_pass_thru	Verifies the hardware needs to allow ARPs to be processed by the host
e1000_enable_tx_pkt_filtering	This function checks whether tx pkt filtering needs to be enabled or not.
e1000_enable_tx_pkt_filtering	This function checks whether tx pkt filtering needs to be enabled or not.
e1000_erase_ich8_4k_segment	Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
e1000_erase_ich8_4k_segment	Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
E1000_ERR_CONFIG
E1000_ERR_CONFIG
E1000_ERR_EEPROM
E1000_ERR_EEPROM
E1000_ERR_HOST_INTERFACE_COMMAN
E1000_ERR_HOST_INTERFACE_COMMAN
E1000_ERR_MAC_TYPE
E1000_ERR_MAC_TYPE
E1000_ERR_MASTER_REQUESTS_PENDI
E1000_ERR_MASTER_REQUESTS_PENDI
E1000_ERR_PARAM
E1000_ERR_PARAM
E1000_ERR_PHY
E1000_ERR_PHY
E1000_ERR_PHY_TYPE
E1000_ERR_PHY_TYPE
E1000_ERR_RESET
E1000_ERR_RESET
E1000_ERR_SWFW_SYNC
E1000_ERR_SWFW_SYNC
E1000_ERT	Early Rx Threshold - RW
E1000_ERT	Early Rx Threshold - RW
E1000_ERT_2048
E1000_ERT_2048
E1000_EXTCNF_CTRL	Extended Configuration Control
E1000_EXTCNF_CTRL	Extended Configuration Control
E1000_EXTCNF_CTRL_D_UD_ENABLE
E1000_EXTCNF_CTRL_D_UD_ENABLE
E1000_EXTCNF_CTRL_D_UD_LATENCY
E1000_EXTCNF_CTRL_D_UD_LATENCY
E1000_EXTCNF_CTRL_D_UD_OWNER
E1000_EXTCNF_CTRL_D_UD_OWNER
E1000_EXTCNF_CTRL_EXT_CNF_POINT
E1000_EXTCNF_CTRL_EXT_CNF_POINT
E1000_EXTCNF_CTRL_LCD_WRITE_ENA
E1000_EXTCNF_CTRL_LCD_WRITE_ENA
E1000_EXTCNF_CTRL_MDIO_HW_OWNER
E1000_EXTCNF_CTRL_MDIO_HW_OWNER
E1000_EXTCNF_CTRL_MDIO_SW_OWNER
E1000_EXTCNF_CTRL_MDIO_SW_OWNER
E1000_EXTCNF_CTRL_PCIE_WRITE_EN
E1000_EXTCNF_CTRL_PCIE_WRITE_EN
E1000_EXTCNF_CTRL_PHY_WRITE_ENA
E1000_EXTCNF_CTRL_PHY_WRITE_ENA
E1000_EXTCNF_CTRL_SWFLAG
E1000_EXTCNF_CTRL_SWFLAG
E1000_EXTCNF_SIZE	Extended Configuration Size
E1000_EXTCNF_SIZE	Extended Configuration Size
E1000_EXTCNF_SIZE_EXT_DOCK_LENG
E1000_EXTCNF_SIZE_EXT_DOCK_LENG
E1000_EXTCNF_SIZE_EXT_PCIE_LENG
E1000_EXTCNF_SIZE_EXT_PCIE_LENG
E1000_EXTCNF_SIZE_EXT_PHY_LENGT
E1000_EXTCNF_SIZE_EXT_PHY_LENGT
E1000_FACTPS	Function Active and Power State to MNG
E1000_FACTPS	Function Active and Power State to MNG
E1000_FACTPS_FUNC0_AUX_EN
E1000_FACTPS_FUNC0_AUX_EN
E1000_FACTPS_FUNC0_POWER_STATE_
E1000_FACTPS_FUNC0_POWER_STATE_
E1000_FACTPS_FUNC1_AUX_EN
E1000_FACTPS_FUNC1_AUX_EN
E1000_FACTPS_FUNC1_POWER_STATE_
E1000_FACTPS_FUNC1_POWER_STATE_
E1000_FACTPS_FUNC1_POWER_STATE_
E1000_FACTPS_FUNC1_POWER_STATE_
E1000_FACTPS_FUNC2_AUX_EN
E1000_FACTPS_FUNC2_AUX_EN
E1000_FACTPS_FUNC2_POWER_STATE_
E1000_FACTPS_FUNC2_POWER_STATE_
E1000_FACTPS_FUNC2_POWER_STATE_
E1000_FACTPS_FUNC2_POWER_STATE_
E1000_FACTPS_FUNC3_AUX_EN
E1000_FACTPS_FUNC3_AUX_EN
E1000_FACTPS_FUNC3_POWER_STATE_
E1000_FACTPS_FUNC3_POWER_STATE_
E1000_FACTPS_FUNC3_POWER_STATE_
E1000_FACTPS_FUNC3_POWER_STATE_
E1000_FACTPS_FUNC4_AUX_EN
E1000_FACTPS_FUNC4_AUX_EN
E1000_FACTPS_FUNC4_POWER_STATE_
E1000_FACTPS_FUNC4_POWER_STATE_
E1000_FACTPS_FUNC4_POWER_STATE_
E1000_FACTPS_FUNC4_POWER_STATE_
E1000_FACTPS_IDE_ENABLE
E1000_FACTPS_IDE_ENABLE
E1000_FACTPS_IPMI_ENABLE
E1000_FACTPS_IPMI_ENABLE
E1000_FACTPS_LAN_FUNC_SEL
E1000_FACTPS_LAN_FUNC_SEL
E1000_FACTPS_LAN0_VALID
E1000_FACTPS_LAN0_VALID
E1000_FACTPS_LAN1_VALID
E1000_FACTPS_LAN1_VALID
E1000_FACTPS_MNGCG
E1000_FACTPS_MNGCG
E1000_FACTPS_PM_STATE_CHANGED
E1000_FACTPS_PM_STATE_CHANGED
E1000_FACTPS_SP_ENABLE
E1000_FACTPS_SP_ENABLE
E1000_FC_HIGH_DIFF	High: 5688 bytes below Rx FIFO size
E1000_FC_HIGH_DIFF	High: 5688 bytes below Rx FIFO size
E1000_FC_LOW_DIFF	Low: 5696 bytes below Rx FIFO size
E1000_FC_LOW_DIFF	Low: 5696 bytes below Rx FIFO size
E1000_FC_PAUSE_TIME	858 usec
E1000_FC_PAUSE_TIME	858 usec
e1000_fc_type
e1000_fc_type
E1000_FCAH	Flow Control Address High -RW
E1000_FCAH	Flow Control Address High -RW
E1000_FCAL	Flow Control Address Low - RW
E1000_FCAL	Flow Control Address Low - RW
E1000_FCRTH	Flow Control Receive Threshold High - RW
E1000_FCRTH	Flow Control Receive Threshold High - RW
E1000_FCRTH_RTH	Mask Bits[15:3] for RTH
E1000_FCRTH_RTH	Mask Bits[15:3] for RTH
E1000_FCRTH_XFCE	External Flow Control Enable
E1000_FCRTH_XFCE	External Flow Control Enable
E1000_FCRTL	Flow Control Receive Threshold Low - RW
E1000_FCRTL	Flow Control Receive Threshold Low - RW
E1000_FCRTL_RTL	Mask Bits[15:3] for RTL
E1000_FCRTL_RTL	Mask Bits[15:3] for RTL
E1000_FCRTL_XONE	Enable XON frame transmission
E1000_FCRTL_XONE	Enable XON frame transmission
E1000_FCRUC	Flow Control RX Unsupported Count- R/clr
E1000_FCRUC	Flow Control RX Unsupported Count- R/clr
E1000_FCT	Flow Control Type - RW
E1000_FCT	Flow Control Type - RW
E1000_FCTTV	Flow Control Transmit Timer Value - RW
E1000_FCTTV	Flow Control Transmit Timer Value - RW
E1000_FDX_COLLISION_DISTANCE
E1000_FDX_COLLISION_DISTANCE
E1000_FEXTNVM	Future Extended NVM register
E1000_FEXTNVM	Future Extended NVM register
e1000_ffe_config
e1000_ffe_config
E1000_FFLT	Flexible Filter Length Table - RW Array
E1000_FFLT	Flexible Filter Length Table - RW Array
E1000_FFLT_DBG	Debug Register
E1000_FFLT_DBG	Debug Register
E1000_FFLT_DBG_INVC	Invalid /C/ code handling
E1000_FFLT_DBG_INVC	Invalid /C/ code handling
e1000_fflt_entry
e1000_fflt_entry
E1000_FFLT_SIZE
E1000_FFLT_SIZE
E1000_FFMT	Flexible Filter Mask Table - RW Array
E1000_FFMT	Flexible Filter Mask Table - RW Array
e1000_ffmt_entry
e1000_ffmt_entry
E1000_FFMT_SIZE
E1000_FFMT_SIZE
E1000_FFVT	Flexible Filter Value Table - RW Array
E1000_FFVT	Flexible Filter Value Table - RW Array
e1000_ffvt_entry
e1000_ffvt_entry
E1000_FFVT_SIZE
E1000_FFVT_SIZE
E1000_FLA	Flash Access - RW
E1000_FLA	Flash Access - RW
E1000_FLASH_UPDATES
E1000_FLASH_UPDATES
E1000_FLASHT	FLASH Timer Register
E1000_FLASHT	FLASH Timer Register
E1000_FLEXIBLE_FILTER_COUNT_MAX
E1000_FLEXIBLE_FILTER_COUNT_MAX
E1000_FLEXIBLE_FILTER_SIZE_MAX
E1000_FLEXIBLE_FILTER_SIZE_MAX
E1000_FLOP	FLASH Opcode Register
E1000_FLOP	FLASH Opcode Register
E1000_FLSWCNT	FLASH Access Counter
E1000_FLSWCNT	FLASH Access Counter
E1000_FLSWCTL	FLASH control register
E1000_FLSWCTL	FLASH control register
E1000_FLSWDATA	FLASH data register
E1000_FLSWDATA	FLASH data register
e1000_force_mac_fc	Forces the MAC's flow control settings.
e1000_force_mac_fc	Forces the MAC's flow control settings.
e1000_free_rx_resources
e1000_free_rx_resources
e1000_free_tx_resources
e1000_free_tx_resources
E1000_FWSM	FW Semaphore
E1000_FWSM	FW Semaphore
E1000_FWSM_DISSW	FW disable SW Write Access
E1000_FWSM_DISSW	FW disable SW Write Access
E1000_FWSM_FW_VALID	FW established a valid mode
E1000_FWSM_FW_VALID	FW established a valid mode
E1000_FWSM_MODE_MASK	FW mode
E1000_FWSM_MODE_MASK	FW mode
E1000_FWSM_MODE_SHIFT
E1000_FWSM_MODE_SHIFT
E1000_FWSM_RSPCIPHY	Reset PHY on PCI reset
E1000_FWSM_RSPCIPHY	Reset PHY on PCI reset
E1000_FWSM_SKUEL_SHIFT
E1000_FWSM_SKUEL_SHIFT
E1000_FWSM_SKUSEL_CONS	Consumer SKU
E1000_FWSM_SKUSEL_CONS	Consumer SKU
E1000_FWSM_SKUSEL_EMB	Embedded SKU
E1000_FWSM_SKUSEL_EMB	Embedded SKU
E1000_FWSM_SKUSEL_MASK	LAN SKU select
E1000_FWSM_SKUSEL_MASK	LAN SKU select
E1000_FWSM_SKUSEL_PERF_100	Perf & Corp 10/100 SKU
E1000_FWSM_SKUSEL_PERF_100	Perf & Corp 10/100 SKU
E1000_FWSM_SKUSEL_PERF_GBE	Perf & Copr GbE SKU
E1000_FWSM_SKUSEL_PERF_GBE	Perf & Copr GbE SKU
E1000_FWSTS_FWS_MASK	FW Status
E1000_FWSTS_FWS_MASK	FW Status
E1000_GCR	PCI-Ex Control
E1000_GCR	PCI-Ex Control
E1000_GCR_L1_ACT_WITHOUT_L0S_RX
E1000_GCR_L1_ACT_WITHOUT_L0S_RX
E1000_GCR_RXD_NO_SNOOP
E1000_GCR_RXD_NO_SNOOP
E1000_GCR_RXDSCR_NO_SNOOP
E1000_GCR_RXDSCR_NO_SNOOP
E1000_GCR_RXDSCW_NO_SNOOP
E1000_GCR_RXDSCW_NO_SNOOP
E1000_GCR_TXD_NO_SNOOP
E1000_GCR_TXD_NO_SNOOP
E1000_GCR_TXDSCR_NO_SNOOP
E1000_GCR_TXDSCR_NO_SNOOP
E1000_GCR_TXDSCW_NO_SNOOP
E1000_GCR_TXDSCW_NO_SNOOP
e1000_get_auto_rd_done	Check for EEPROM Auto Read bit done.
e1000_get_auto_rd_done	Check for EEPROM Auto Read bit done.
e1000_get_bus_info	Gets the current PCI bus type, speed, and width of the hardware
e1000_get_bus_info	Gets the current PCI bus type, speed, and width of the hardware
e1000_get_cable_length	Estimates the cable length.
e1000_get_cable_length	Estimates the cable length.
E1000_GET_DESC(R, i, type)
E1000_GET_DESC(R, i, type)
e1000_get_hw_control	e1000_get_hw_control - get control of the h/w from f/w
e1000_get_hw_control	e1000_get_hw_control - get control of the h/w from f/w
e1000_get_hw_eeprom_semaphore	Using the combination of SMBI and SWESMBI semaphore bits when resetting
e1000_get_hw_eeprom_semaphore	Using the combination of SMBI and SWESMBI semaphore bits when resetting
e1000_get_phy_cfg_done	Checks if the PHY configuration is done
e1000_get_phy_cfg_done	Checks if the PHY configuration is done
e1000_get_software_flag	Get software semaphore FLAG bit (SWFLAG).
e1000_get_software_flag	Get software semaphore FLAG bit (SWFLAG).
e1000_get_software_semaphore	Obtaining software semaphore bit (SMBI) before resetting PHY.
e1000_get_software_semaphore	Obtaining software semaphore bit (SMBI) before resetting PHY.
e1000_get_speed_and_duplex	Detects the current speed and duplex settings of the hardware.
e1000_get_speed_and_duplex	Detects the current speed and duplex settings of the hardware.
e1000_gg_cable_length
e1000_gg_cable_length
E1000_GORCH	Good Octets RX Count High - R/clr
E1000_GORCH	Good Octets RX Count High - R/clr
E1000_GORCL	Good Octets RX Count Low - R/clr
E1000_GORCL	Good Octets RX Count Low - R/clr
E1000_GOTCH	Good Octets TX Count High - R/clr
E1000_GOTCH	Good Octets TX Count High - R/clr
E1000_GOTCL	Good Octets TX Count Low - R/clr
E1000_GOTCL	Good Octets TX Count Low - R/clr
E1000_GPRC	Good Packets RX Count - R/clr
E1000_GPRC	Good Packets RX Count - R/clr
E1000_GPTC	Good Packets TX Count - R/clr
E1000_GPTC	Good Packets TX Count - R/clr
E1000_GSCL_1	PCI-Ex Statistic Control #1
E1000_GSCL_1	PCI-Ex Statistic Control #1
E1000_GSCL_2	PCI-Ex Statistic Control #2
E1000_GSCL_2	PCI-Ex Statistic Control #2
E1000_GSCL_3	PCI-Ex Statistic Control #3
E1000_GSCL_3	PCI-Ex Statistic Control #3
E1000_GSCL_4	PCI-Ex Statistic Control #4
E1000_GSCL_4	PCI-Ex Statistic Control #4
e1000_hash_mc_addr	Hashes an address to determine its location in the multicast table
e1000_hash_mc_addr	Hashes an address to determine its location in the multicast table
E1000_HDX_COLLISION_DISTANCE
E1000_HDX_COLLISION_DISTANCE
E1000_HI_COMMAND_TIMEOUT	Time in ms to process HI command
E1000_HI_COMMAND_TIMEOUT	Time in ms to process HI command
E1000_HI_MAX_BLOCK_BYTE_LENGTH	Number of bytes in range
E1000_HI_MAX_BLOCK_BYTE_LENGTH	Number of bytes in range
E1000_HI_MAX_BLOCK_DWORD_LENGTH	Number of dwords in range
E1000_HI_MAX_BLOCK_DWORD_LENGTH	Number of dwords in range
E1000_HI_MAX_DATA_LENGTH	Host Interface data length
E1000_HI_MAX_DATA_LENGTH	Host Interface data length
E1000_HI_MAX_MNG_DATA_LENGTH	Host Interface data length
E1000_HI_MAX_MNG_DATA_LENGTH	Host Interface data length
E1000_HICR	Host Inteface Control
E1000_HICR	Host Inteface Control
E1000_HICR_C	Driver sets this bit when done
E1000_HICR_C	Driver sets this bit when done
E1000_HICR_EN	Enable Bit - RO
E1000_HICR_EN	Enable Bit - RO
E1000_HICR_FW_RESET
E1000_HICR_FW_RESET
E1000_HICR_FWR	FW reset. Set by the Host
E1000_HICR_FWR	FW reset. Set by the Host
E1000_HICR_SV	Status Validity
E1000_HICR_SV	Status Validity
e1000_host_command_header
e1000_host_command_header
e1000_host_command_info
e1000_host_command_info
E1000_HOST_IF	Host Interface
E1000_HOST_IF	Host Interface
E1000_HOST_IF_MAX_SIZE
E1000_HOST_IF_MAX_SIZE
e1000_host_if_read_cookie	This function reads the cookie from ARC ram.
e1000_host_if_read_cookie	This function reads the cookie from ARC ram.
e1000_host_mng_command_header
e1000_host_mng_command_header
e1000_host_mng_command_info
e1000_host_mng_command_info
e1000_host_mng_dhcp_cookie
e1000_host_mng_dhcp_cookie
e1000_host_mng_dhcp_cookie
e1000_host_mng_dhcp_cookie
E1000_HSMC0R_CLKIN	SMB Clock in
E1000_HSMC0R_CLKIN	SMB Clock in
E1000_HSMC0R_CLKOUT	SMB Clock out
E1000_HSMC0R_CLKOUT	SMB Clock out
E1000_HSMC0R_DATAIN	SMB Data in
E1000_HSMC0R_DATAIN	SMB Data in
E1000_HSMC0R_DATAOUT	SMB Data out
E1000_HSMC0R_DATAOUT	SMB Data out
E1000_HSMC1R_CLKIN
E1000_HSMC1R_CLKIN
E1000_HSMC1R_CLKOUT
E1000_HSMC1R_CLKOUT
E1000_HSMC1R_DATAIN
E1000_HSMC1R_DATAIN
E1000_HSMC1R_DATAOUT
E1000_HSMC1R_DATAOUT
e1000_hw
e1000_hw
e1000_hw.c
e1000_hw.c
e1000_hw.h
e1000_hw.h
e1000_hw_stats
e1000_hw_stats
E1000_IAC	Interrupt Assertion Count
E1000_IAC	Interrupt Assertion Count
E1000_IAM	Interrupt Acknowledge Auto Mask
E1000_IAM	Interrupt Acknowledge Auto Mask
E1000_IAMT_SIGNATURE	Intel(R) Active Management Technology signature
E1000_IAMT_SIGNATURE	Intel(R) Active Management Technology signature
E1000_ICH_NVM_SIG_MASK
E1000_ICH_NVM_SIG_MASK
E1000_ICH_NVM_SIG_WORD
E1000_ICH_NVM_SIG_WORD
e1000_ich8_cycle_init	This function does initial flash setup so that a new read/write/erase cycle
e1000_ich8_cycle_init	This function does initial flash setup so that a new read/write/erase cycle
e1000_ich8_flash_cycle	This function starts a flash cycle and waits for its completion
e1000_ich8_flash_cycle	This function starts a flash cycle and waits for its completion
E1000_ICR	Interrupt Cause Read - R/clr
E1000_ICR	Interrupt Cause Read - R/clr
E1000_ICR_ACK	Receive Ack frame
E1000_ICR_ACK	Receive Ack frame
E1000_ICR_ALL_PARITY	all parity error bits
E1000_ICR_ALL_PARITY	all parity error bits
E1000_ICR_DOCK	Dock/Undock
E1000_ICR_DOCK	Dock/Undock
E1000_ICR_DOUTSYNC	NIC DMA out of sync
E1000_ICR_DOUTSYNC	NIC DMA out of sync
E1000_ICR_DSW	FW changed the status of DISSW bit in the FWSM
E1000_ICR_DSW	FW changed the status of DISSW bit in the FWSM
E1000_ICR_EPRST	ME handware reset occurs
E1000_ICR_EPRST	ME handware reset occurs
E1000_ICR_GPI_EN0	GP Int 0
E1000_ICR_GPI_EN0	GP Int 0
E1000_ICR_GPI_EN1	GP Int 1
E1000_ICR_GPI_EN1	GP Int 1
E1000_ICR_GPI_EN2	GP Int 2
E1000_ICR_GPI_EN2	GP Int 2
E1000_ICR_GPI_EN3	GP Int 3
E1000_ICR_GPI_EN3	GP Int 3
E1000_ICR_HOST_ARB_PAR	host arb read buffer parity error
E1000_ICR_HOST_ARB_PAR	host arb read buffer parity error
E1000_ICR_INT_ASSERTED	If this bit asserted, the driver should claim the interrupt
E1000_ICR_INT_ASSERTED	If this bit asserted, the driver should claim the interrupt
E1000_ICR_LSC	Link Status Change
E1000_ICR_LSC	Link Status Change
E1000_ICR_MDAC	MDIO access complete
E1000_ICR_MDAC	MDIO access complete
E1000_ICR_MNG	Manageability event
E1000_ICR_MNG	Manageability event
E1000_ICR_PB_PAR	packet buffer parity error
E1000_ICR_PB_PAR	packet buffer parity error
E1000_ICR_PHYINT	LAN connected device generates an interrupt
E1000_ICR_PHYINT	LAN connected device generates an interrupt
E1000_ICR_RXCFG	RX /c/ ordered set
E1000_ICR_RXCFG	RX /c/ ordered set
E1000_ICR_RXD_FIFO_PAR0	queue 0 Rx descriptor FIFO parity error
E1000_ICR_RXD_FIFO_PAR0	queue 0 Rx descriptor FIFO parity error
E1000_ICR_RXD_FIFO_PAR1	queue 1 Rx descriptor FIFO parity error
E1000_ICR_RXD_FIFO_PAR1	queue 1 Rx descriptor FIFO parity error
E1000_ICR_RXDMT0	rx desc min. threshold (0)
E1000_ICR_RXDMT0	rx desc min. threshold (0)
E1000_ICR_RXO	rx overrun
E1000_ICR_RXO	rx overrun
E1000_ICR_RXSEQ	rx sequence error
E1000_ICR_RXSEQ	rx sequence error
E1000_ICR_RXT0	rx timer intr (ring 0)
E1000_ICR_RXT0	rx timer intr (ring 0)
E1000_ICR_SRPD
E1000_ICR_SRPD
E1000_ICR_TXD_FIFO_PAR0	queue 0 Tx descriptor FIFO parity error
E1000_ICR_TXD_FIFO_PAR0	queue 0 Tx descriptor FIFO parity error
E1000_ICR_TXD_FIFO_PAR1	queue 1 Tx descriptor FIFO parity error
E1000_ICR_TXD_FIFO_PAR1	queue 1 Tx descriptor FIFO parity error
E1000_ICR_TXD_LOW
E1000_ICR_TXD_LOW
E1000_ICR_TXDW	Transmit desc written back
E1000_ICR_TXDW	Transmit desc written back
E1000_ICR_TXQE	Transmit Queue empty
E1000_ICR_TXQE	Transmit Queue empty
E1000_ICRXATC	Interrupt Cause Rx Absolute Timer Expire Count
E1000_ICRXATC	Interrupt Cause Rx Absolute Timer Expire Count
E1000_ICRXDMTC	Interrupt Cause Rx Descriptor Minimum Threshold Count
E1000_ICRXDMTC	Interrupt Cause Rx Descriptor Minimum Threshold Count
E1000_ICRXOC	Interrupt Cause Receiver Overrun Count
E1000_ICRXOC	Interrupt Cause Receiver Overrun Count
E1000_ICRXPTC	Interrupt Cause Rx Packet Timer Expire Count
E1000_ICRXPTC	Interrupt Cause Rx Packet Timer Expire Count
E1000_ICS	Interrupt Cause Set - WO
E1000_ICS	Interrupt Cause Set - WO
E1000_ICS_ACK	Receive Ack frame
E1000_ICS_ACK	Receive Ack frame
E1000_ICS_DOCK	Dock/Undock
E1000_ICS_DOCK	Dock/Undock
E1000_ICS_DSW
E1000_ICS_DSW
E1000_ICS_EPRST
E1000_ICS_EPRST
E1000_ICS_GPI_EN0	GP Int 0
E1000_ICS_GPI_EN0	GP Int 0
E1000_ICS_GPI_EN1	GP Int 1
E1000_ICS_GPI_EN1	GP Int 1
E1000_ICS_GPI_EN2	GP Int 2
E1000_ICS_GPI_EN2	GP Int 2
E1000_ICS_GPI_EN3	GP Int 3
E1000_ICS_GPI_EN3	GP Int 3
E1000_ICS_HOST_ARB_PAR	host arb read buffer parity error
E1000_ICS_HOST_ARB_PAR	host arb read buffer parity error
E1000_ICS_LSC	Link Status Change
E1000_ICS_LSC	Link Status Change
E1000_ICS_MDAC	MDIO access complete
E1000_ICS_MDAC	MDIO access complete
E1000_ICS_MNG	Manageability event
E1000_ICS_MNG	Manageability event
E1000_ICS_PB_PAR	packet buffer parity error
E1000_ICS_PB_PAR	packet buffer parity error
E1000_ICS_PHYINT
E1000_ICS_PHYINT
E1000_ICS_RXCFG	RX /c/ ordered set
E1000_ICS_RXCFG	RX /c/ ordered set
E1000_ICS_RXD_FIFO_PAR0	queue 0 Rx descriptor FIFO parity error
E1000_ICS_RXD_FIFO_PAR0	queue 0 Rx descriptor FIFO parity error
E1000_ICS_RXD_FIFO_PAR1	queue 1 Rx descriptor FIFO parity error
E1000_ICS_RXD_FIFO_PAR1	queue 1 Rx descriptor FIFO parity error
E1000_ICS_RXDMT0	rx desc min. threshold
E1000_ICS_RXDMT0	rx desc min. threshold
E1000_ICS_RXO	rx overrun
E1000_ICS_RXO	rx overrun
E1000_ICS_RXSEQ	rx sequence error
E1000_ICS_RXSEQ	rx sequence error
E1000_ICS_RXT0	rx timer intr
E1000_ICS_RXT0	rx timer intr
E1000_ICS_SRPD
E1000_ICS_SRPD
E1000_ICS_TXD_FIFO_PAR0	queue 0 Tx descriptor FIFO parity error
E1000_ICS_TXD_FIFO_PAR0	queue 0 Tx descriptor FIFO parity error
E1000_ICS_TXD_FIFO_PAR1	queue 1 Tx descriptor FIFO parity error
E1000_ICS_TXD_FIFO_PAR1	queue 1 Tx descriptor FIFO parity error
E1000_ICS_TXD_LOW
E1000_ICS_TXD_LOW
E1000_ICS_TXDW	Transmit desc written back
E1000_ICS_TXDW	Transmit desc written back
E1000_ICS_TXQE	Transmit Queue empty
E1000_ICS_TXQE	Transmit Queue empty
E1000_ICTXATC	Interrupt Cause Tx Absolute Timer Expire Count
E1000_ICTXATC	Interrupt Cause Tx Absolute Timer Expire Count
E1000_ICTXPTC	Interrupt Cause Tx Packet Timer Expire Count
E1000_ICTXPTC	Interrupt Cause Tx Packet Timer Expire Count
E1000_ICTXQEC	Interrupt Cause Tx Queue Empty Count
E1000_ICTXQEC	Interrupt Cause Tx Queue Empty Count
E1000_ICTXQMTC	Interrupt Cause Tx Queue Minimum Threshold Count
E1000_ICTXQMTC	Interrupt Cause Tx Queue Minimum Threshold Count
e1000_id_led_init
e1000_id_led_init
e1000_igp_cable_length
e1000_igp_cable_length
E1000_IMC	Interrupt Mask Clear - WO
E1000_IMC	Interrupt Mask Clear - WO
E1000_IMC_ACK	Receive Ack frame
E1000_IMC_ACK	Receive Ack frame
E1000_IMC_DOCK	Dock/Undock
E1000_IMC_DOCK	Dock/Undock
E1000_IMC_DSW
E1000_IMC_DSW
E1000_IMC_EPRST
E1000_IMC_EPRST
E1000_IMC_GPI_EN0	GP Int 0
E1000_IMC_GPI_EN0	GP Int 0
E1000_IMC_GPI_EN1	GP Int 1
E1000_IMC_GPI_EN1	GP Int 1
E1000_IMC_GPI_EN2	GP Int 2
E1000_IMC_GPI_EN2	GP Int 2
E1000_IMC_GPI_EN3	GP Int 3
E1000_IMC_GPI_EN3	GP Int 3
E1000_IMC_HOST_ARB_PAR	host arb read buffer parity error
E1000_IMC_HOST_ARB_PAR	host arb read buffer parity error
E1000_IMC_LSC	Link Status Change
E1000_IMC_LSC	Link Status Change
E1000_IMC_MDAC	MDIO access complete
E1000_IMC_MDAC	MDIO access complete
E1000_IMC_MNG	Manageability event
E1000_IMC_MNG	Manageability event
E1000_IMC_PB_PAR	packet buffer parity error
E1000_IMC_PB_PAR	packet buffer parity error
E1000_IMC_PHYINT
E1000_IMC_PHYINT
E1000_IMC_RXCFG	RX /c/ ordered set
E1000_IMC_RXCFG	RX /c/ ordered set
E1000_IMC_RXD_FIFO_PAR0	queue 0 Rx descriptor FIFO parity error
E1000_IMC_RXD_FIFO_PAR0	queue 0 Rx descriptor FIFO parity error
E1000_IMC_RXD_FIFO_PAR1	queue 1 Rx descriptor FIFO parity error
E1000_IMC_RXD_FIFO_PAR1	queue 1 Rx descriptor FIFO parity error
E1000_IMC_RXDMT0	rx desc min. threshold
E1000_IMC_RXDMT0	rx desc min. threshold
E1000_IMC_RXO	rx overrun
E1000_IMC_RXO	rx overrun
E1000_IMC_RXSEQ	rx sequence error
E1000_IMC_RXSEQ	rx sequence error
E1000_IMC_RXT0	rx timer intr
E1000_IMC_RXT0	rx timer intr
E1000_IMC_SRPD
E1000_IMC_SRPD
E1000_IMC_TXD_FIFO_PAR0	queue 0 Tx descriptor FIFO parity error
E1000_IMC_TXD_FIFO_PAR0	queue 0 Tx descriptor FIFO parity error
E1000_IMC_TXD_FIFO_PAR1	queue 1 Tx descriptor FIFO parity error
E1000_IMC_TXD_FIFO_PAR1	queue 1 Tx descriptor FIFO parity error
E1000_IMC_TXD_LOW
E1000_IMC_TXD_LOW
E1000_IMC_TXDW	Transmit desc written back
E1000_IMC_TXDW	Transmit desc written back
E1000_IMC_TXQE	Transmit Queue empty
E1000_IMC_TXQE	Transmit Queue empty
E1000_IMS	Interrupt Mask Set - RW
E1000_IMS	Interrupt Mask Set - RW
E1000_IMS_ACK	Receive Ack frame
E1000_IMS_ACK	Receive Ack frame
E1000_IMS_DOCK	Dock/Undock
E1000_IMS_DOCK	Dock/Undock
E1000_IMS_DOUTSYNC	NIC DMA out of sync
E1000_IMS_DOUTSYNC	NIC DMA out of sync
E1000_IMS_DSW
E1000_IMS_DSW
E1000_IMS_EPRST
E1000_IMS_EPRST
E1000_IMS_GPI_EN0	GP Int 0
E1000_IMS_GPI_EN0	GP Int 0
E1000_IMS_GPI_EN1	GP Int 1
E1000_IMS_GPI_EN1	GP Int 1
E1000_IMS_GPI_EN2	GP Int 2
E1000_IMS_GPI_EN2	GP Int 2
E1000_IMS_GPI_EN3	GP Int 3
E1000_IMS_GPI_EN3	GP Int 3
E1000_IMS_HOST_ARB_PAR	host arb read buffer parity error
E1000_IMS_HOST_ARB_PAR	host arb read buffer parity error
E1000_IMS_LSC	Link Status Change
E1000_IMS_LSC	Link Status Change
E1000_IMS_MDAC	MDIO access complete
E1000_IMS_MDAC	MDIO access complete
E1000_IMS_MNG	Manageability event
E1000_IMS_MNG	Manageability event
E1000_IMS_PB_PAR	packet buffer parity error
E1000_IMS_PB_PAR	packet buffer parity error
E1000_IMS_PHYINT
E1000_IMS_PHYINT
E1000_IMS_RXCFG	RX /c/ ordered set
E1000_IMS_RXCFG	RX /c/ ordered set
E1000_IMS_RXD_FIFO_PAR0	queue 0 Rx descriptor FIFO parity error
E1000_IMS_RXD_FIFO_PAR0	queue 0 Rx descriptor FIFO parity error
E1000_IMS_RXD_FIFO_PAR1	queue 1 Rx descriptor FIFO parity error
E1000_IMS_RXD_FIFO_PAR1	queue 1 Rx descriptor FIFO parity error
E1000_IMS_RXDMT0	rx desc min. threshold
E1000_IMS_RXDMT0	rx desc min. threshold
E1000_IMS_RXO	rx overrun
E1000_IMS_RXO	rx overrun
E1000_IMS_RXSEQ	rx sequence error
E1000_IMS_RXSEQ	rx sequence error
E1000_IMS_RXT0	rx timer intr
E1000_IMS_RXT0	rx timer intr
E1000_IMS_SRPD
E1000_IMS_SRPD
E1000_IMS_TXD_FIFO_PAR0	queue 0 Tx descriptor FIFO parity error
E1000_IMS_TXD_FIFO_PAR0	queue 0 Tx descriptor FIFO parity error
E1000_IMS_TXD_FIFO_PAR1	queue 1 Tx descriptor FIFO parity error
E1000_IMS_TXD_FIFO_PAR1	queue 1 Tx descriptor FIFO parity error
E1000_IMS_TXD_LOW
E1000_IMS_TXD_LOW
E1000_IMS_TXDW	Transmit desc written back
E1000_IMS_TXDW	Transmit desc written back
E1000_IMS_TXQE	Transmit Queue empty
E1000_IMS_TXQE	Transmit Queue empty
e1000_init_eeprom_params	Sets up eeprom variables in the hw struct. Must be called after mac_type
e1000_init_eeprom_params	Sets up eeprom variables in the hw struct. Must be called after mac_type
e1000_init_hw	Performs basic configuration of the adapter.
e1000_init_hw	Performs basic configuration of the adapter.
e1000_init_lcd_from_nvm	This function initializes the PHY from the NVM on ICH8 platforms. This
e1000_init_lcd_from_nvm	This function initializes the PHY from the NVM on ICH8 platforms. This
e1000_init_lcd_from_nvm_config_region
e1000_init_lcd_from_nvm_config_region
e1000_init_rx_addrs	Initializes receive address filters.
e1000_init_rx_addrs	Initializes receive address filters.
e1000_initialize_hardware_bits	Initialize a number of hardware-dependent bits
e1000_initialize_hardware_bits	Initialize a number of hardware-dependent bits
e1000_io_write
e1000_io_write
E1000_IP4AT	IPv4 Address Table - RW Array
E1000_IP4AT	IPv4 Address Table - RW Array
E1000_IP4AT_SIZE
E1000_IP4AT_SIZE
E1000_IP4AT_SIZE_ICH8LAN
E1000_IP4AT_SIZE_ICH8LAN
E1000_IP6AT	IPv6 Address Table - RW Array
E1000_IP6AT	IPv6 Address Table - RW Array
E1000_IP6AT_SIZE
E1000_IP6AT_SIZE
E1000_IPAV	IP Address Valid - RW
E1000_IPAV	IP Address Valid - RW
e1000_ipv4_at_entry
e1000_ipv4_at_entry
e1000_ipv6_at_entry
e1000_ipv6_at_entry
e1000_irq	e1000_irq - enable or Disable interrupts
e1000_irq	e1000_irq - enable or Disable interrupts
e1000_irq_disable	e1000_irq_disable - Mask off interrupt generation on the NIC
e1000_irq_disable	e1000_irq_disable - Mask off interrupt generation on the NIC
e1000_irq_enable	e1000_irq_enable - Enable default interrupt generation settings
e1000_irq_enable	e1000_irq_enable - Enable default interrupt generation settings
e1000_irq_force	e1000_irq_force - trigger interrupt
e1000_is_onboard_nvm_eeprom
e1000_is_onboard_nvm_eeprom
E1000_ITR	Interrupt Throttling Rate - RW
E1000_ITR	Interrupt Throttling Rate - RW
E1000_KABGTXD	AFE Band Gap Transmit Ref Data
E1000_KABGTXD	AFE Band Gap Transmit Ref Data
E1000_KABGTXD_BGSQLBIAS
E1000_KABGTXD_BGSQLBIAS
E1000_KUMCTRLSTA	MAC-PHY interface - RW
E1000_KUMCTRLSTA	MAC-PHY interface - RW
E1000_KUMCTRLSTA_DIAG_FELPBK
E1000_KUMCTRLSTA_DIAG_FELPBK
E1000_KUMCTRLSTA_DIAG_NELPBK
E1000_KUMCTRLSTA_DIAG_NELPBK
E1000_KUMCTRLSTA_FIFO_CTRL_RX_B
E1000_KUMCTRLSTA_FIFO_CTRL_RX_B
E1000_KUMCTRLSTA_FIFO_CTRL_TX_B
E1000_KUMCTRLSTA_FIFO_CTRL_TX_B
E1000_KUMCTRLSTA_HD_CTRL_10_100
E1000_KUMCTRLSTA_HD_CTRL_10_100
E1000_KUMCTRLSTA_HD_CTRL_1000_D
E1000_KUMCTRLSTA_HD_CTRL_1000_D
E1000_KUMCTRLSTA_INB_CTRL_DIS_P
E1000_KUMCTRLSTA_INB_CTRL_DIS_P
E1000_KUMCTRLSTA_INB_CTRL_LINK_
E1000_KUMCTRLSTA_INB_CTRL_LINK_
E1000_KUMCTRLSTA_K0S_100_EN
E1000_KUMCTRLSTA_K0S_100_EN
E1000_KUMCTRLSTA_K0S_ENTRY_LATE
E1000_KUMCTRLSTA_K0S_ENTRY_LATE
E1000_KUMCTRLSTA_K0S_GBE_EN
E1000_KUMCTRLSTA_K0S_GBE_EN
E1000_KUMCTRLSTA_MASK
E1000_KUMCTRLSTA_MASK
E1000_KUMCTRLSTA_OFFSET
E1000_KUMCTRLSTA_OFFSET
E1000_KUMCTRLSTA_OFFSET_CTRL
E1000_KUMCTRLSTA_OFFSET_CTRL
E1000_KUMCTRLSTA_OFFSET_DIAG
E1000_KUMCTRLSTA_OFFSET_DIAG
E1000_KUMCTRLSTA_OFFSET_FIFO_CT
E1000_KUMCTRLSTA_OFFSET_FIFO_CT
E1000_KUMCTRLSTA_OFFSET_HD_CTRL
E1000_KUMCTRLSTA_OFFSET_HD_CTRL
E1000_KUMCTRLSTA_OFFSET_INB_CTR
E1000_KUMCTRLSTA_OFFSET_INB_CTR
E1000_KUMCTRLSTA_OFFSET_INB_PAR
E1000_KUMCTRLSTA_OFFSET_INB_PAR
E1000_KUMCTRLSTA_OFFSET_K0S_CTR
E1000_KUMCTRLSTA_OFFSET_K0S_CTR
E1000_KUMCTRLSTA_OFFSET_M2P_MOD
E1000_KUMCTRLSTA_OFFSET_M2P_MOD
E1000_KUMCTRLSTA_OFFSET_M2P_SER
E1000_KUMCTRLSTA_OFFSET_M2P_SER
E1000_KUMCTRLSTA_OFFSET_SHIFT
E1000_KUMCTRLSTA_OFFSET_SHIFT
E1000_KUMCTRLSTA_OFFSET_TIMEOUT
E1000_KUMCTRLSTA_OFFSET_TIMEOUT
E1000_KUMCTRLSTA_REN
E1000_KUMCTRLSTA_REN
e1000_kumeran_lock_loss_workaround
e1000_kumeran_lock_loss_workaround
E1000_LATECOL	Late Collision Count - R/clr
E1000_LATECOL	Late Collision Count - R/clr
e1000_led_off	Turns off the software controllable LED
e1000_led_off	Turns off the software controllable LED
e1000_led_on	Turns on the software controllable LED
e1000_led_on	Turns on the software controllable LED
E1000_LEDCTL	LED Control - RW
E1000_LEDCTL	LED Control - RW
E1000_LEDCTL_LED0_BLINK
E1000_LEDCTL_LED0_BLINK
E1000_LEDCTL_LED0_BLINK_RATE
E1000_LEDCTL_LED0_BLINK_RATE
E1000_LEDCTL_LED0_IVRT
E1000_LEDCTL_LED0_IVRT
E1000_LEDCTL_LED0_MODE_MASK
E1000_LEDCTL_LED0_MODE_MASK
E1000_LEDCTL_LED0_MODE_SHIFT
E1000_LEDCTL_LED0_MODE_SHIFT
E1000_LEDCTL_LED1_BLINK
E1000_LEDCTL_LED1_BLINK
E1000_LEDCTL_LED1_BLINK_RATE
E1000_LEDCTL_LED1_BLINK_RATE
E1000_LEDCTL_LED1_IVRT
E1000_LEDCTL_LED1_IVRT
E1000_LEDCTL_LED1_MODE_MASK
E1000_LEDCTL_LED1_MODE_MASK
E1000_LEDCTL_LED1_MODE_SHIFT
E1000_LEDCTL_LED1_MODE_SHIFT
E1000_LEDCTL_LED2_BLINK
E1000_LEDCTL_LED2_BLINK
E1000_LEDCTL_LED2_BLINK_RATE
E1000_LEDCTL_LED2_BLINK_RATE
E1000_LEDCTL_LED2_IVRT
E1000_LEDCTL_LED2_IVRT
E1000_LEDCTL_LED2_MODE_MASK
E1000_LEDCTL_LED2_MODE_MASK
E1000_LEDCTL_LED2_MODE_SHIFT
E1000_LEDCTL_LED2_MODE_SHIFT
E1000_LEDCTL_LED3_BLINK
E1000_LEDCTL_LED3_BLINK
E1000_LEDCTL_LED3_BLINK_RATE
E1000_LEDCTL_LED3_BLINK_RATE
E1000_LEDCTL_LED3_IVRT
E1000_LEDCTL_LED3_IVRT
E1000_LEDCTL_LED3_MODE_MASK
E1000_LEDCTL_LED3_MODE_MASK
E1000_LEDCTL_LED3_MODE_SHIFT
E1000_LEDCTL_LED3_MODE_SHIFT
E1000_LEDCTL_MODE_ACTIVITY
E1000_LEDCTL_MODE_ACTIVITY
E1000_LEDCTL_MODE_BUS_SIZE
E1000_LEDCTL_MODE_BUS_SIZE
E1000_LEDCTL_MODE_BUS_SPEED
E1000_LEDCTL_MODE_BUS_SPEED
E1000_LEDCTL_MODE_COLLISION
E1000_LEDCTL_MODE_COLLISION
E1000_LEDCTL_MODE_FULL_DUPLEX
E1000_LEDCTL_MODE_FULL_DUPLEX
E1000_LEDCTL_MODE_LED_OFF
E1000_LEDCTL_MODE_LED_OFF
E1000_LEDCTL_MODE_LED_ON
E1000_LEDCTL_MODE_LED_ON
E1000_LEDCTL_MODE_LINK_10
E1000_LEDCTL_MODE_LINK_10
E1000_LEDCTL_MODE_LINK_10_1000
E1000_LEDCTL_MODE_LINK_10_1000
E1000_LEDCTL_MODE_LINK_100
E1000_LEDCTL_MODE_LINK_100
E1000_LEDCTL_MODE_LINK_100_1000
E1000_LEDCTL_MODE_LINK_100_1000
E1000_LEDCTL_MODE_LINK_1000
E1000_LEDCTL_MODE_LINK_1000
E1000_LEDCTL_MODE_LINK_ACTIVITY
E1000_LEDCTL_MODE_LINK_ACTIVITY
E1000_LEDCTL_MODE_LINK_UP
E1000_LEDCTL_MODE_LINK_UP
E1000_LEDCTL_MODE_PAUSED
E1000_LEDCTL_MODE_PAUSED
E1000_LEDCTL_MODE_PCIX_MODE
E1000_LEDCTL_MODE_PCIX_MODE
e1000_lower_ee_clk	Lowers the EEPROM's clock input.
e1000_lower_ee_clk	Lowers the EEPROM's clock input.
e1000_lower_mdi_clk	Lowers the Management Data Clock
e1000_lower_mdi_clk	Lowers the Management Data Clock
e1000_mac_type
e1000_mac_type
E1000_MANC	Management Control - RW
E1000_MANC	Management Control - RW
E1000_MANC_0298_EN	Enable RCMP 0298h Filtering
E1000_MANC_0298_EN	Enable RCMP 0298h Filtering
E1000_MANC_ARP_EN	Enable ARP Request Filtering
E1000_MANC_ARP_EN	Enable ARP Request Filtering
E1000_MANC_ARP_RES_EN	Enable ARP response Filtering
E1000_MANC_ARP_RES_EN	Enable ARP response Filtering
E1000_MANC_ASF_EN	ASF Enabled - RO
E1000_MANC_ASF_EN	ASF Enabled - RO
E1000_MANC_BLK_PHY_RST_ON_IDE	Block phy resets
E1000_MANC_BLK_PHY_RST_ON_IDE	Block phy resets
E1000_MANC_BR_EN	Enable broadcast filtering
E1000_MANC_BR_EN	Enable broadcast filtering
E1000_MANC_EN_IP_ADDR_FILTER	Enable IP address
E1000_MANC_EN_IP_ADDR_FILTER	Enable IP address
E1000_MANC_EN_MAC_ADDR_FILTER	Enable MAC address
E1000_MANC_EN_MAC_ADDR_FILTER	Enable MAC address
E1000_MANC_EN_MNG2HOST	Enable MNG packets to host
E1000_MANC_EN_MNG2HOST	Enable MNG packets to host
E1000_MANC_EN_XSUM_FILTER	Enable checksum filtering
E1000_MANC_EN_XSUM_FILTER	Enable checksum filtering
E1000_MANC_IPV4_EN	Enable IPv4
E1000_MANC_IPV4_EN	Enable IPv4
E1000_MANC_IPV6_EN	Enable IPv6
E1000_MANC_IPV6_EN	Enable IPv6
E1000_MANC_NEIGHBOR_EN	Enable Neighbor Discovery
E1000_MANC_NEIGHBOR_EN	Enable Neighbor Discovery
E1000_MANC_R_ON_FORCE	Reset on Force TCO - RO
E1000_MANC_R_ON_FORCE	Reset on Force TCO - RO
E1000_MANC_RCV_ALL	Receive All Enabled
E1000_MANC_RCV_ALL	Receive All Enabled
E1000_MANC_RCV_TCO_EN	Receive TCO Packets Enabled
E1000_MANC_RCV_TCO_EN	Receive TCO Packets Enabled
E1000_MANC_REPORT_STATUS	Status Reporting Enabled
E1000_MANC_REPORT_STATUS	Status Reporting Enabled
E1000_MANC_RMCP_EN	Enable RCMP 026Fh Filtering
E1000_MANC_RMCP_EN	Enable RCMP 026Fh Filtering
E1000_MANC_SMB_CLK_IN	SMBus Clock In
E1000_MANC_SMB_CLK_IN	SMBus Clock In
E1000_MANC_SMB_CLK_OUT	SMBus Clock Out
E1000_MANC_SMB_CLK_OUT	SMBus Clock Out
E1000_MANC_SMB_CLK_OUT_SHIFT	SMBus Clock Out Shift
E1000_MANC_SMB_CLK_OUT_SHIFT	SMBus Clock Out Shift
E1000_MANC_SMB_DATA_IN	SMBus Data In
E1000_MANC_SMB_DATA_IN	SMBus Data In
E1000_MANC_SMB_DATA_OUT	SMBus Data Out
E1000_MANC_SMB_DATA_OUT	SMBus Data Out
E1000_MANC_SMB_DATA_OUT_SHIFT	SMBus Data Out Shift
E1000_MANC_SMB_DATA_OUT_SHIFT	SMBus Data Out Shift
E1000_MANC_SMB_GNT	SMBus Grant
E1000_MANC_SMB_GNT	SMBus Grant
E1000_MANC_SMB_REQ	SMBus Request
E1000_MANC_SMB_REQ	SMBus Request
E1000_MANC_SMBUS_EN	SMBus Enabled - RO
E1000_MANC_SMBUS_EN	SMBus Enabled - RO
E1000_MANC_SNAP_EN	Accept LLC/SNAP
E1000_MANC_SNAP_EN	Accept LLC/SNAP
E1000_MANC_TCO_RESET	TCO Reset Occurred
E1000_MANC_TCO_RESET	TCO Reset Occurred
E1000_MANC2H	Managment Control To Host - RW
E1000_MANC2H	Managment Control To Host - RW
E1000_MASTER_SLAVE
E1000_MASTER_SLAVE
E1000_MAX_DSP_RESETS
E1000_MAX_DSP_RESETS
E1000_MC_TBL_SIZE	Multicast Filter Table (4096 bits)
E1000_MC_TBL_SIZE	Multicast Filter Table (4096 bits)
E1000_MC_TBL_SIZE_ICH8LAN
E1000_MC_TBL_SIZE_ICH8LAN
E1000_MCC	Multiple Collision Count - R/clr
E1000_MCC	Multiple Collision Count - R/clr
E1000_MDALIGN
E1000_MDALIGN
E1000_MDIC	MDI Control - RW
E1000_MDIC	MDI Control - RW
E1000_MDIC_DATA_MASK
E1000_MDIC_DATA_MASK
E1000_MDIC_ERROR
E1000_MDIC_ERROR
E1000_MDIC_INT_EN
E1000_MDIC_INT_EN
E1000_MDIC_OP_READ
E1000_MDIC_OP_READ
E1000_MDIC_OP_WRITE
E1000_MDIC_OP_WRITE
E1000_MDIC_PHY_MASK
E1000_MDIC_PHY_MASK
E1000_MDIC_PHY_SHIFT
E1000_MDIC_PHY_SHIFT
E1000_MDIC_READY
E1000_MDIC_READY
E1000_MDIC_REG_MASK
E1000_MDIC_REG_MASK
E1000_MDIC_REG_SHIFT
E1000_MDIC_REG_SHIFT
E1000_MDPHYA	PHY address - RW
E1000_MDPHYA	PHY address - RW
e1000_media_type
e1000_media_type
E1000_MGTPDC	Management Packets Dropped Count - R/clr
E1000_MGTPDC	Management Packets Dropped Count - R/clr
E1000_MGTPRC	Management Packets RX Count - R/clr
E1000_MGTPRC	Management Packets RX Count - R/clr
E1000_MGTPTC	Management Packets TX Count - R/clr
E1000_MGTPTC	Management Packets TX Count - R/clr
E1000_MNG_DHCP_COMMAND_TIMEOUT	Time in ms to process MNG command
E1000_MNG_DHCP_COMMAND_TIMEOUT	Time in ms to process MNG command
E1000_MNG_DHCP_COOKIE_LENGTH	Cookie length
E1000_MNG_DHCP_COOKIE_LENGTH	Cookie length
E1000_MNG_DHCP_COOKIE_OFFSET	Cookie offset
E1000_MNG_DHCP_COOKIE_OFFSET	Cookie offset
E1000_MNG_DHCP_COOKIE_STATUS_PA	DHCP parsing enabled
E1000_MNG_DHCP_COOKIE_STATUS_PA	DHCP parsing enabled
E1000_MNG_DHCP_COOKIE_STATUS_VL	DHCP parsing enabled
E1000_MNG_DHCP_COOKIE_STATUS_VL	DHCP parsing enabled
E1000_MNG_DHCP_TX_PAYLOAD_CMD
E1000_MNG_DHCP_TX_PAYLOAD_CMD
e1000_mng_enable_host_if	This function checks whether the HOST IF is enabled for command operaton
e1000_mng_enable_host_if	This function checks whether the HOST IF is enabled for command operaton
e1000_mng_host_if_write	This function writes the buffer content at the offset given on the host if.
e1000_mng_host_if_write	This function writes the buffer content at the offset given on the host if.
E1000_MNG_IAMT_MODE
E1000_MNG_IAMT_MODE
E1000_MNG_ICH_IAMT_MODE
E1000_MNG_ICH_IAMT_MODE
e1000_mng_mode
e1000_mng_mode
e1000_mng_write_cmd_header	This function writes the command header after does the checksum calculation.
e1000_mng_write_cmd_header	This function writes the command header after does the checksum calculation.
e1000_mng_write_commit	This function indicates to ARC that a new command is pending which completes
e1000_mng_write_commit	This function indicates to ARC that a new command is pending which completes
e1000_mng_write_dhcp_info	This function writes the dhcp info .
e1000_mng_write_dhcp_info	This function writes the dhcp info .
E1000_MNG2HOST_PORT_623
E1000_MNG2HOST_PORT_623
E1000_MNG2HOST_PORT_664
E1000_MNG2HOST_PORT_664
E1000_MPC	Missed Packet Count - R/clr
E1000_MPC	Missed Packet Count - R/clr
E1000_MPRC	Multicast Packets RX Count - R/clr
E1000_MPRC	Multicast Packets RX Count - R/clr
E1000_MPTC	Multicast Packets TX Count - R/clr
E1000_MPTC	Multicast Packets TX Count - R/clr
E1000_MRQC	Multiple Receive Control - RW
E1000_MRQC	Multiple Receive Control - RW
E1000_MRQC_ENABLE_MASK
E1000_MRQC_ENABLE_MASK
E1000_MRQC_ENABLE_RSS_2Q
E1000_MRQC_ENABLE_RSS_2Q
E1000_MRQC_ENABLE_RSS_INT
E1000_MRQC_ENABLE_RSS_INT
E1000_MRQC_ENABLE_VMDQ
E1000_MRQC_ENABLE_VMDQ
E1000_MRQC_RSS_FIELD_IPV4
E1000_MRQC_RSS_FIELD_IPV4
E1000_MRQC_RSS_FIELD_IPV4_TCP
E1000_MRQC_RSS_FIELD_IPV4_TCP
E1000_MRQC_RSS_FIELD_IPV6
E1000_MRQC_RSS_FIELD_IPV6
E1000_MRQC_RSS_FIELD_IPV6_EX
E1000_MRQC_RSS_FIELD_IPV6_EX
E1000_MRQC_RSS_FIELD_IPV6_TCP
E1000_MRQC_RSS_FIELD_IPV6_TCP
E1000_MRQC_RSS_FIELD_IPV6_TCP_E
E1000_MRQC_RSS_FIELD_IPV6_TCP_E
E1000_MRQC_RSS_FIELD_MASK
E1000_MRQC_RSS_FIELD_MASK
e1000_ms_type
e1000_ms_type
E1000_MTA	Multicast Table Array - RW Array
E1000_MTA	Multicast Table Array - RW Array
e1000_mta_set	Sets the bit in the multicast table corresponding to the hash value.
e1000_mta_set	Sets the bit in the multicast table corresponding to the hash value.
E1000_NUM_MTA_REGISTERS
E1000_NUM_MTA_REGISTERS
E1000_NUM_MTA_REGISTERS_ICH8LAN
E1000_NUM_MTA_REGISTERS_ICH8LAN
E1000_NUM_UNICAST	Unicast filter entries
E1000_NUM_UNICAST	Unicast filter entries
E1000_NUM_UNICAST_ICH8LAN
E1000_NUM_UNICAST_ICH8LAN
e1000_open	e1000_open - Called when a network interface is made active
e1000_open	e1000_open - Called when a network interface is made active
e1000_osdep.h
e1000_osdep.h
E1000_PBA	Packet Buffer Allocation - RW
E1000_PBA	Packet Buffer Allocation - RW
E1000_PBA_12K	12KB, default Rx allocation
E1000_PBA_12K	12KB, default Rx allocation
E1000_PBA_16K	16KB, default TX allocation
E1000_PBA_16K	16KB, default TX allocation
E1000_PBA_20K
E1000_PBA_20K
E1000_PBA_22K
E1000_PBA_22K
E1000_PBA_24K
E1000_PBA_24K
E1000_PBA_30K
E1000_PBA_30K
E1000_PBA_32K
E1000_PBA_32K
E1000_PBA_34K
E1000_PBA_34K
E1000_PBA_38K
E1000_PBA_38K
E1000_PBA_40K
E1000_PBA_40K
E1000_PBA_48K	48KB, default RX allocation
E1000_PBA_48K	48KB, default RX allocation
E1000_PBA_64K	64KB
E1000_PBA_64K	64KB
E1000_PBA_8K	8KB, default Rx allocation
E1000_PBA_8K	8KB, default Rx allocation
E1000_PBA_BYTES_SHIFT
E1000_PBA_BYTES_SHIFT
E1000_PBA_TX_MASK
E1000_PBA_TX_MASK
E1000_PBS	Packet Buffer Size
E1000_PBS	Packet Buffer Size
E1000_PBS_16K
E1000_PBS_16K
e1000_pci_clear_mwi
e1000_pci_clear_mwi
e1000_pci_set_mwi
e1000_pci_set_mwi
E1000_PHY_ADDRESS
E1000_PHY_ADDRESS
E1000_PHY_CTRL	PHY Control Register in CSR
E1000_PHY_CTRL	PHY Control Register in CSR
E1000_PHY_CTRL_B2B_EN
E1000_PHY_CTRL_B2B_EN
E1000_PHY_CTRL_D0A_LPLU
E1000_PHY_CTRL_D0A_LPLU
E1000_PHY_CTRL_GBE_DISABLE
E1000_PHY_CTRL_GBE_DISABLE
E1000_PHY_CTRL_NOND0A_GBE_DISAB
E1000_PHY_CTRL_NOND0A_GBE_DISAB
E1000_PHY_CTRL_NOND0A_LPLU
E1000_PHY_CTRL_NOND0A_LPLU
E1000_PHY_CTRL_SPD_EN
E1000_PHY_CTRL_SPD_EN
e1000_phy_force_speed_duplex	Force PHY speed and duplex settings to hw->forced_speed_duplex
e1000_phy_force_speed_duplex	Force PHY speed and duplex settings to hw->forced_speed_duplex
e1000_phy_get_info	Get PHY information from various PHY registers
e1000_phy_get_info	Get PHY information from various PHY registers
e1000_phy_hw_reset	Returns the PHY to the power-on reset state
e1000_phy_hw_reset	Returns the PHY to the power-on reset state
e1000_phy_ife_get_info	Get PHY information from various PHY registers for ife PHY only.
e1000_phy_ife_get_info	Get PHY information from various PHY registers for ife PHY only.
e1000_phy_igp_get_info	Get PHY information from various PHY registers for igp PHY only.
e1000_phy_igp_get_info	Get PHY information from various PHY registers for igp PHY only.
e1000_phy_info
e1000_phy_info
e1000_phy_init_script	IGP phy init script - initializes the GbE PHY
e1000_phy_init_script	IGP phy init script - initializes the GbE PHY
e1000_phy_m88_get_info	Get PHY information from various PHY registers fot m88 PHY only.
e1000_phy_m88_get_info	Get PHY information from various PHY registers fot m88 PHY only.
e1000_phy_powerdown_workaround
e1000_phy_powerdown_workaround
e1000_phy_reset	Resets the PHY
e1000_phy_reset	Resets the PHY
e1000_phy_reset_dsp	Resets the PHY's DSP
e1000_phy_reset_dsp	Resets the PHY's DSP
e1000_phy_setup_autoneg	Configures PHY autoneg and flow control advertisement settings
e1000_phy_setup_autoneg	Configures PHY autoneg and flow control advertisement settings
e1000_phy_stats
e1000_phy_stats
e1000_phy_type
e1000_phy_type
e1000_polarity_reversal
e1000_polarity_reversal
e1000_polarity_reversal_workaround
e1000_polarity_reversal_workaround
e1000_poll	e1000_poll - Poll for received packets
e1000_poll	e1000_poll - Poll for received packets
e1000_poll_eerd_eewr_done	Polls the status bit (bit 1) of the EERD to determine when the read is done.
e1000_poll_eerd_eewr_done	Polls the status bit (bit 1) of the EERD to determine when the read is done.
E1000_PRC1023	Packets RX (512-1023 bytes) - R/clr
E1000_PRC1023	Packets RX (512-1023 bytes) - R/clr
E1000_PRC127	Packets RX (65-127 bytes) - R/clr
E1000_PRC127	Packets RX (65-127 bytes) - R/clr
E1000_PRC1522	Packets RX (1024-1522 bytes) - R/clr
E1000_PRC1522	Packets RX (1024-1522 bytes) - R/clr
E1000_PRC255	Packets RX (128-255 bytes) - R/clr
E1000_PRC255	Packets RX (128-255 bytes) - R/clr
E1000_PRC511	Packets RX (255-511 bytes) - R/clr
E1000_PRC511	Packets RX (255-511 bytes) - R/clr
E1000_PRC64	Packets RX (64 bytes) - R/clr
E1000_PRC64	Packets RX (64 bytes) - R/clr
e1000_probe	e1000_probe - Initial configuration of e1000 NIC
e1000_probe	e1000_probe - Initial configuration of e1000 NIC
E1000_PSRCTL	Packet Split Receive Control - RW
E1000_PSRCTL	Packet Split Receive Control - RW
E1000_PSRCTL_BSIZE0_MASK
E1000_PSRCTL_BSIZE0_MASK
E1000_PSRCTL_BSIZE0_SHIFT	Shift _right_ 7
E1000_PSRCTL_BSIZE0_SHIFT	Shift _right_ 7
E1000_PSRCTL_BSIZE1_MASK
E1000_PSRCTL_BSIZE1_MASK
E1000_PSRCTL_BSIZE1_SHIFT	Shift _right_ 2
E1000_PSRCTL_BSIZE1_SHIFT	Shift _right_ 2
E1000_PSRCTL_BSIZE2_MASK
E1000_PSRCTL_BSIZE2_MASK
E1000_PSRCTL_BSIZE2_SHIFT	Shift _left_ 6
E1000_PSRCTL_BSIZE2_SHIFT	Shift _left_ 6
E1000_PSRCTL_BSIZE3_MASK
E1000_PSRCTL_BSIZE3_MASK
E1000_PSRCTL_BSIZE3_SHIFT	Shift _left_ 14
E1000_PSRCTL_BSIZE3_SHIFT	Shift _left_ 14
E1000_PTC1023	Packets TX (512-1023 bytes) - R/clr
E1000_PTC1023	Packets TX (512-1023 bytes) - R/clr
E1000_PTC127	Packets TX (65-127 bytes) - R/clr
E1000_PTC127	Packets TX (65-127 bytes) - R/clr
E1000_PTC1522	Packets TX (1024-1522 Bytes) - R/clr
E1000_PTC1522	Packets TX (1024-1522 Bytes) - R/clr
E1000_PTC255	Packets TX (128-255 bytes) - R/clr
E1000_PTC255	Packets TX (128-255 bytes) - R/clr
E1000_PTC511	Packets TX (256-511 bytes) - R/clr
E1000_PTC511	Packets TX (256-511 bytes) - R/clr
E1000_PTC64	Packets TX (64 bytes) - R/clr
E1000_PTC64	Packets TX (64 bytes) - R/clr
e1000_put_hw_eeprom_semaphore	This function clears HW semaphore bits.
e1000_put_hw_eeprom_semaphore	This function clears HW semaphore bits.
E1000_RA	Receive Address - RW Array
E1000_RA	Receive Address - RW Array
E1000_RADV	RX Interrupt Absolute Delay Timer - RW
E1000_RADV	RX Interrupt Absolute Delay Timer - RW
E1000_RAH_AV	Receive descriptor valid
E1000_RAH_AV	Receive descriptor valid
E1000_RAH_POOL_1
E1000_RAH_POOL_1
E1000_RAID	Receive Ack Interrupt Delay - RW
E1000_RAID	Receive Ack Interrupt Delay - RW
e1000_raise_ee_clk	Raises the EEPROM's clock input.
e1000_raise_ee_clk	Raises the EEPROM's clock input.
e1000_raise_mdi_clk	Raises the Management Data Clock
e1000_raise_mdi_clk	Raises the Management Data Clock
e1000_rar
e1000_rar
E1000_RAR_ENTRIES
E1000_RAR_ENTRIES
E1000_RAR_ENTRIES_ICH8LAN
E1000_RAR_ENTRIES_ICH8LAN
e1000_rar_set	Puts an ethernet address into a receive address register.
e1000_rar_set	Puts an ethernet address into a receive address register.
E1000_RCTL	RX Control - RW
E1000_RCTL	RX Control - RW
E1000_RCTL_BAM	broadcast enable
E1000_RCTL_BAM	broadcast enable
E1000_RCTL_BSEX	Buffer size extension
E1000_RCTL_BSEX	Buffer size extension
E1000_RCTL_CFI	canonical form indicator
E1000_RCTL_CFI	canonical form indicator
E1000_RCTL_CFIEN	canonical form enable
E1000_RCTL_CFIEN	canonical form enable
E1000_RCTL_DPF	discard pause frames
E1000_RCTL_DPF	discard pause frames
E1000_RCTL_DTYP_MASK	Descriptor type mask
E1000_RCTL_DTYP_MASK	Descriptor type mask
E1000_RCTL_DTYP_PS	Packet Split descriptor
E1000_RCTL_DTYP_PS	Packet Split descriptor
E1000_RCTL_EN	enable
E1000_RCTL_EN	enable
E1000_RCTL_FLXBUF_MASK	Flexible buffer size
E1000_RCTL_FLXBUF_MASK	Flexible buffer size
E1000_RCTL_FLXBUF_SHIFT	Flexible buffer shift
E1000_RCTL_FLXBUF_SHIFT	Flexible buffer shift
E1000_RCTL_LBM_MAC	MAC loopback mode
E1000_RCTL_LBM_MAC	MAC loopback mode
E1000_RCTL_LBM_NO	no loopback mode
E1000_RCTL_LBM_NO	no loopback mode
E1000_RCTL_LBM_SLP	serial link loopback mode
E1000_RCTL_LBM_SLP	serial link loopback mode
E1000_RCTL_LBM_TCVR	tcvr loopback mode
E1000_RCTL_LBM_TCVR	tcvr loopback mode
E1000_RCTL_LPE	long packet enable
E1000_RCTL_LPE	long packet enable
E1000_RCTL_MDR	multicast desc ring 0
E1000_RCTL_MDR	multicast desc ring 0
E1000_RCTL_MO_0	multicast offset 11:0
E1000_RCTL_MO_0	multicast offset 11:0
E1000_RCTL_MO_1	multicast offset 12:1
E1000_RCTL_MO_1	multicast offset 12:1
E1000_RCTL_MO_2	multicast offset 13:2
E1000_RCTL_MO_2	multicast offset 13:2
E1000_RCTL_MO_3	multicast offset 15:4
E1000_RCTL_MO_3	multicast offset 15:4
E1000_RCTL_MO_SHIFT	multicast offset shift
E1000_RCTL_MO_SHIFT	multicast offset shift
E1000_RCTL_MPE	multicast promiscuous enab
E1000_RCTL_MPE	multicast promiscuous enab
E1000_RCTL_PMCF	pass MAC control frames
E1000_RCTL_PMCF	pass MAC control frames
E1000_RCTL_RDMTS_EIGTH	rx desc min threshold size
E1000_RCTL_RDMTS_EIGTH	rx desc min threshold size
E1000_RCTL_RDMTS_HALF	rx desc min threshold size
E1000_RCTL_RDMTS_HALF	rx desc min threshold size
E1000_RCTL_RDMTS_QUAT	rx desc min threshold size
E1000_RCTL_RDMTS_QUAT	rx desc min threshold size
E1000_RCTL_RST	Software reset
E1000_RCTL_RST	Software reset
E1000_RCTL_SBP	store bad packet
E1000_RCTL_SBP	store bad packet
E1000_RCTL_SECRC	Strip Ethernet CRC
E1000_RCTL_SECRC	Strip Ethernet CRC
E1000_RCTL_SZ_1024	rx buffer size 1024
E1000_RCTL_SZ_1024	rx buffer size 1024
E1000_RCTL_SZ_16384	rx buffer size 16384
E1000_RCTL_SZ_16384	rx buffer size 16384
E1000_RCTL_SZ_2048	rx buffer size 2048
E1000_RCTL_SZ_2048	rx buffer size 2048
E1000_RCTL_SZ_256	rx buffer size 256
E1000_RCTL_SZ_256	rx buffer size 256
E1000_RCTL_SZ_4096	rx buffer size 4096
E1000_RCTL_SZ_4096	rx buffer size 4096
E1000_RCTL_SZ_512	rx buffer size 512
E1000_RCTL_SZ_512	rx buffer size 512
E1000_RCTL_SZ_8192	rx buffer size 8192
E1000_RCTL_SZ_8192	rx buffer size 8192
E1000_RCTL_UPE	unicast promiscuous enable
E1000_RCTL_UPE	unicast promiscuous enable
E1000_RCTL_VFE	vlan filter enable
E1000_RCTL_VFE	vlan filter enable
E1000_RDBAH	RX Descriptor Base Address High - RW
E1000_RDBAH	RX Descriptor Base Address High - RW
E1000_RDBAH0	RX Desc Base Address High (0) - RW
E1000_RDBAH0	RX Desc Base Address High (0) - RW
E1000_RDBAH1	RX Descriptor Base Address High (1) - RW
E1000_RDBAH1	RX Descriptor Base Address High (1) - RW
E1000_RDBAL	RX Descriptor Base Address Low - RW
E1000_RDBAL	RX Descriptor Base Address Low - RW
E1000_RDBAL0	RX Desc Base Address Low (0) - RW
E1000_RDBAL0	RX Desc Base Address Low (0) - RW
E1000_RDBAL1	RX Descriptor Base Address Low (1) - RW
E1000_RDBAL1	RX Descriptor Base Address Low (1) - RW
E1000_RDH	RX Descriptor Head - RW
E1000_RDH	RX Descriptor Head - RW
E1000_RDH_RDH	receive descriptor head
E1000_RDH_RDH	receive descriptor head
E1000_RDH0	RX Desc Head (0) - RW
E1000_RDH0	RX Desc Head (0) - RW
E1000_RDH1	RX Descriptor Head (1) - RW
E1000_RDH1	RX Descriptor Head (1) - RW
E1000_RDLEN	RX Descriptor Length - RW
E1000_RDLEN	RX Descriptor Length - RW
E1000_RDLEN_LEN	descriptor length
E1000_RDLEN_LEN	descriptor length
E1000_RDLEN0	RX Desc Length (0) - RW
E1000_RDLEN0	RX Desc Length (0) - RW
E1000_RDLEN1	RX Descriptor Length (1) - RW
E1000_RDLEN1	RX Descriptor Length (1) - RW
E1000_RDT	RX Descriptor Tail - RW
E1000_RDT	RX Descriptor Tail - RW
E1000_RDT_DELAY	Delay timer (1=1024us)
E1000_RDT_DELAY	Delay timer (1=1024us)
E1000_RDT_FPDB	Flush descriptor block
E1000_RDT_FPDB	Flush descriptor block
E1000_RDT_RDT	receive descriptor tail
E1000_RDT_RDT	receive descriptor tail
E1000_RDT0	RX Desc Tail (0) - RW
E1000_RDT0	RX Desc Tail (0) - RW
E1000_RDT1	RX Descriptor Tail (1) - RW
E1000_RDT1	RX Descriptor Tail (1) - RW
E1000_RDTR	RX Delay Timer - RW
E1000_RDTR	RX Delay Timer - RW
E1000_RDTR0	RX Delay Timer (0) - RW
E1000_RDTR0	RX Delay Timer (0) - RW
E1000_RDTR1	RX Delay Timer (1) - RW
E1000_RDTR1	RX Delay Timer (1) - RW
e1000_read_eeprom	Reads a 16 bit word from the EEPROM.
e1000_read_eeprom	Reads a 16 bit word from the EEPROM.
e1000_read_eeprom_eerd	Reads a 16 bit word from the EEPROM using the EERD register.
e1000_read_eeprom_eerd	Reads a 16 bit word from the EEPROM using the EERD register.
e1000_read_eeprom_ich8	Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
e1000_read_eeprom_ich8	Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
E1000_READ_ICH_FLASH_REG(a, reg)
E1000_READ_ICH_FLASH_REG(a, reg)
E1000_READ_ICH_FLASH_REG16(a, reg)
E1000_READ_ICH_FLASH_REG16(a, reg)
e1000_read_ich8_byte	Reads a single byte from the NVM using the ICH8 flash access registers.
e1000_read_ich8_byte	Reads a single byte from the NVM using the ICH8 flash access registers.
e1000_read_ich8_data	Reads a byte or word from the NVM using the ICH8 flash access registers.
e1000_read_ich8_data	Reads a byte or word from the NVM using the ICH8 flash access registers.
e1000_read_ich8_word	Reads a word from the NVM using the ICH8 flash access registers.
e1000_read_ich8_word	Reads a word from the NVM using the ICH8 flash access registers.
e1000_read_kmrn_reg
e1000_read_kmrn_reg
e1000_read_mac_addr	Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
e1000_read_mac_addr	Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
e1000_read_pci_cfg
e1000_read_pci_cfg
e1000_read_pcie_cap_reg
e1000_read_pcie_cap_reg
e1000_read_phy_reg	Reads the value from a PHY register, if the value is on a specific non zero
e1000_read_phy_reg	Reads the value from a PHY register, if the value is on a specific non zero
e1000_read_phy_reg_ex
e1000_read_phy_reg_ex
E1000_READ_REG(a, reg)
E1000_READ_REG(a, reg)
E1000_READ_REG_ARRAY(a, reg, offset)
E1000_READ_REG_ARRAY(a, reg, offset)
E1000_READ_REG_ARRAY_BYTE(a, reg, offset)
E1000_READ_REG_ARRAY_BYTE(a, reg, offset)
E1000_READ_REG_ARRAY_DWORD
E1000_READ_REG_ARRAY_DWORD
E1000_READ_REG_ARRAY_WORD(a, reg, offset)
E1000_READ_REG_ARRAY_WORD(a, reg, offset)
E1000_READ_REG_IO(a, reg)
E1000_READ_REG_IO(a, reg)
e1000_refill_rx_ring	e1000_refill_rx_ring - allocate Rx io_buffers
e1000_release_eeprom	Terminates a command by inverting the EEPROM's chip select pin
e1000_release_eeprom	Terminates a command by inverting the EEPROM's chip select pin
e1000_release_software_flag	Release software semaphore FLAG bit (SWFLAG).
e1000_release_software_flag	Release software semaphore FLAG bit (SWFLAG).
e1000_release_software_semaphore	Release semaphore bit (SMBI).
e1000_release_software_semaphore	Release semaphore bit (SMBI).
e1000_remove	e1000_remove - Device Removal Routine
e1000_remove	e1000_remove - Device Removal Routine
e1000_reset	e1000_reset - Put e1000 NIC in known initial state
e1000_reset	e1000_reset - Put e1000 NIC in known initial state
e1000_reset_adaptive	Resets Adaptive IFS to its default state.
e1000_reset_adaptive	Resets Adaptive IFS to its default state.
e1000_reset_hw	Reset the transmit and receive units; mask and clear all interrupts.
e1000_reset_hw	Reset the transmit and receive units; mask and clear all interrupts.
E1000_RETA	Redirection Table - RW Array
E1000_RETA	Redirection Table - RW Array
e1000_rev_polarity
e1000_rev_polarity
E1000_REVISION_0
E1000_REVISION_0
E1000_REVISION_1
E1000_REVISION_1
E1000_REVISION_2
E1000_REVISION_2
E1000_REVISION_3
E1000_REVISION_3
E1000_RFC	RX Fragment Count - R/clr
E1000_RFC	RX Fragment Count - R/clr
E1000_RFCTL	Receive Filter Control
E1000_RFCTL	Receive Filter Control
E1000_RFCTL_ACK_DIS
E1000_RFCTL_ACK_DIS
E1000_RFCTL_ACKD_DIS
E1000_RFCTL_ACKD_DIS
E1000_RFCTL_EXTEN
E1000_RFCTL_EXTEN
E1000_RFCTL_IPFRSP_DIS
E1000_RFCTL_IPFRSP_DIS
E1000_RFCTL_IPV6_DIS
E1000_RFCTL_IPV6_DIS
E1000_RFCTL_IPV6_EX_DIS
E1000_RFCTL_IPV6_EX_DIS
E1000_RFCTL_IPV6_XSUM_DIS
E1000_RFCTL_IPV6_XSUM_DIS
E1000_RFCTL_ISCSI_DIS
E1000_RFCTL_ISCSI_DIS
E1000_RFCTL_ISCSI_DWC_MASK
E1000_RFCTL_ISCSI_DWC_MASK
E1000_RFCTL_ISCSI_DWC_SHIFT
E1000_RFCTL_ISCSI_DWC_SHIFT
E1000_RFCTL_NEW_IPV6_EXT_DIS
E1000_RFCTL_NEW_IPV6_EXT_DIS
E1000_RFCTL_NFS_VER_MASK
E1000_RFCTL_NFS_VER_MASK
E1000_RFCTL_NFS_VER_SHIFT
E1000_RFCTL_NFS_VER_SHIFT
E1000_RFCTL_NFSR_DIS
E1000_RFCTL_NFSR_DIS
E1000_RFCTL_NFSW_DIS
E1000_RFCTL_NFSW_DIS
E1000_RJC	RX Jabber Count - R/clr
E1000_RJC	RX Jabber Count - R/clr
E1000_RLEC	Receive Length Error Count - R/clr
E1000_RLEC	Receive Length Error Count - R/clr
E1000_RNBC	RX No Buffers Count - R/clr
E1000_RNBC	RX No Buffers Count - R/clr
E1000_ROC	RX Oversize Count - R/clr
E1000_ROC	RX Oversize Count - R/clr
E1000_RSRPD	RX Small Packet Detect - RW
E1000_RSRPD	RX Small Packet Detect - RW
E1000_RSSIM	RSS Interrupt Mask
E1000_RSSIM	RSS Interrupt Mask
E1000_RSSIR	RSS Interrupt Request
E1000_RSSIR	RSS Interrupt Request
E1000_RSSRK	RSS Random Key - RW Array
E1000_RSSRK	RSS Random Key - RW Array
E1000_RUC	RX Undersize Count - R/clr
E1000_RUC	RX Undersize Count - R/clr
E1000_RX_BUFFER_WRITE	Must be power of 2
E1000_RX_BUFFER_WRITE	Must be power of 2
e1000_rx_desc
e1000_rx_desc
E1000_RX_DESC(R, i)
E1000_RX_DESC(R, i)
E1000_RX_DESC_EXT(R, i)
E1000_RX_DESC_EXT(R, i)
e1000_rx_desc_extended
e1000_rx_desc_extended
e1000_rx_desc_packet_split
e1000_rx_desc_packet_split
E1000_RX_DESC_PS(R, i)
E1000_RX_DESC_PS(R, i)
e1000_rx_ring
e1000_rx_ring
E1000_RXBUFFER_1024
E1000_RXBUFFER_1024
E1000_RXBUFFER_128	Used for packet split
E1000_RXBUFFER_128	Used for packet split
E1000_RXBUFFER_16384
E1000_RXBUFFER_16384
E1000_RXBUFFER_2048
E1000_RXBUFFER_2048
E1000_RXBUFFER_256	Used for packet split
E1000_RXBUFFER_256	Used for packet split
E1000_RXBUFFER_4096
E1000_RXBUFFER_4096
E1000_RXBUFFER_512
E1000_RXBUFFER_512
E1000_RXBUFFER_8192
E1000_RXBUFFER_8192
E1000_RXCSUM	RX Checksum Control - RW
E1000_RXCSUM	RX Checksum Control - RW
E1000_RXCSUM_IPOFL	IPv4 checksum offload
E1000_RXCSUM_IPOFL	IPv4 checksum offload
E1000_RXCSUM_IPPCSE	IP payload checksum enable
E1000_RXCSUM_IPPCSE	IP payload checksum enable
E1000_RXCSUM_IPV6OFL	IPv6 checksum offload
E1000_RXCSUM_IPV6OFL	IPv6 checksum offload
E1000_RXCSUM_PCSD	packet checksum disabled
E1000_RXCSUM_PCSD	packet checksum disabled
E1000_RXCSUM_PCSS_MASK	Packet Checksum Start
E1000_RXCSUM_PCSS_MASK	Packet Checksum Start
E1000_RXCSUM_TUOFL	TCP / UDP checksum offload
E1000_RXCSUM_TUOFL	TCP / UDP checksum offload
E1000_RXCW	RX Configuration Word - RO
E1000_RXCW	RX Configuration Word - RO
E1000_RXCW_ANC	Auto-neg complete
E1000_RXCW_ANC	Auto-neg complete
E1000_RXCW_C	Receive config
E1000_RXCW_C	Receive config
E1000_RXCW_CC	Receive config change
E1000_RXCW_CC	Receive config change
E1000_RXCW_CW	RxConfigWord mask
E1000_RXCW_CW	RxConfigWord mask
E1000_RXCW_IV	Receive config invalid
E1000_RXCW_IV	Receive config invalid
E1000_RXCW_NC	Receive config no carrier
E1000_RXCW_NC	Receive config no carrier
E1000_RXCW_SYNCH	Receive config synch
E1000_RXCW_SYNCH	Receive config synch
E1000_RXD_ERR_CE	CRC Error
E1000_RXD_ERR_CE	CRC Error
E1000_RXD_ERR_CXE	Carrier Extension Error
E1000_RXD_ERR_CXE	Carrier Extension Error
E1000_RXD_ERR_FRAME_ERR_MASK
E1000_RXD_ERR_FRAME_ERR_MASK
E1000_RXD_ERR_IPE	IP Checksum Error
E1000_RXD_ERR_IPE	IP Checksum Error
E1000_RXD_ERR_RXE	Rx Data Error
E1000_RXD_ERR_RXE	Rx Data Error
E1000_RXD_ERR_SE	Symbol Error
E1000_RXD_ERR_SE	Symbol Error
E1000_RXD_ERR_SEQ	Sequence Error
E1000_RXD_ERR_SEQ	Sequence Error
E1000_RXD_ERR_TCPE	TCP/UDP Checksum Error
E1000_RXD_ERR_TCPE	TCP/UDP Checksum Error
E1000_RXD_SPC_CFI_MASK	CFI is bit 12
E1000_RXD_SPC_CFI_MASK	CFI is bit 12
E1000_RXD_SPC_CFI_SHIFT
E1000_RXD_SPC_CFI_SHIFT
E1000_RXD_SPC_PRI_MASK	Priority is in upper 3 bits
E1000_RXD_SPC_PRI_MASK	Priority is in upper 3 bits
E1000_RXD_SPC_PRI_SHIFT
E1000_RXD_SPC_PRI_SHIFT
E1000_RXD_SPC_VLAN_MASK	VLAN ID is in lower 12 bits
E1000_RXD_SPC_VLAN_MASK	VLAN ID is in lower 12 bits
E1000_RXD_STAT_ACK	ACK Packet indication
E1000_RXD_STAT_ACK	ACK Packet indication
E1000_RXD_STAT_DD	Descriptor Done
E1000_RXD_STAT_DD	Descriptor Done
E1000_RXD_STAT_EOP	End of Packet
E1000_RXD_STAT_EOP	End of Packet
E1000_RXD_STAT_IPCS	IP xsum calculated
E1000_RXD_STAT_IPCS	IP xsum calculated
E1000_RXD_STAT_IPIDV	IP identification valid
E1000_RXD_STAT_IPIDV	IP identification valid
E1000_RXD_STAT_IXSM	Ignore checksum
E1000_RXD_STAT_IXSM	Ignore checksum
E1000_RXD_STAT_PIF	passed in-exact filter
E1000_RXD_STAT_PIF	passed in-exact filter
E1000_RXD_STAT_TCPCS	TCP xsum calculated
E1000_RXD_STAT_TCPCS	TCP xsum calculated
E1000_RXD_STAT_UDPCS	UDP xsum caculated
E1000_RXD_STAT_UDPCS	UDP xsum caculated
E1000_RXD_STAT_UDPV	Valid UDP checksum
E1000_RXD_STAT_UDPV	Valid UDP checksum
E1000_RXD_STAT_VP	IEEE VLAN Packet
E1000_RXD_STAT_VP	IEEE VLAN Packet
E1000_RXDCTL	RX Descriptor Control queue 0 - RW
E1000_RXDCTL	RX Descriptor Control queue 0 - RW
E1000_RXDCTL_GRAN	RXDCTL Granularity
E1000_RXDCTL_GRAN	RXDCTL Granularity
E1000_RXDCTL_HTHRESH	RXDCTL Host Threshold
E1000_RXDCTL_HTHRESH	RXDCTL Host Threshold
E1000_RXDCTL_PTHRESH	RXDCTL Prefetch Threshold
E1000_RXDCTL_PTHRESH	RXDCTL Prefetch Threshold
E1000_RXDCTL_QUEUE_ENABLE	Enable specific Rx Queue
E1000_RXDCTL_QUEUE_ENABLE	Enable specific Rx Queue
E1000_RXDCTL_WTHRESH	RXDCTL Writeback Threshold
E1000_RXDCTL_WTHRESH	RXDCTL Writeback Threshold
E1000_RXDCTL1	RX Descriptor Control queue 1 - RW
E1000_RXDCTL1	RX Descriptor Control queue 1 - RW
E1000_RXDEXT_ERR_FRAME_ERR_MASK
E1000_RXDEXT_ERR_FRAME_ERR_MASK
E1000_RXDEXT_STATERR_CE
E1000_RXDEXT_STATERR_CE
E1000_RXDEXT_STATERR_CXE
E1000_RXDEXT_STATERR_CXE
E1000_RXDEXT_STATERR_IPE
E1000_RXDEXT_STATERR_IPE
E1000_RXDEXT_STATERR_RXE
E1000_RXDEXT_STATERR_RXE
E1000_RXDEXT_STATERR_SE
E1000_RXDEXT_STATERR_SE
E1000_RXDEXT_STATERR_SEQ
E1000_RXDEXT_STATERR_SEQ
E1000_RXDEXT_STATERR_TCPE
E1000_RXDEXT_STATERR_TCPE
E1000_RXDPS_HDRSTAT_HDRLEN_MASK
E1000_RXDPS_HDRSTAT_HDRLEN_MASK
E1000_RXDPS_HDRSTAT_HDRSP
E1000_RXDPS_HDRSTAT_HDRSP
E1000_RXERRC	Receive Error Count - R/clr
E1000_RXERRC	Receive Error Count - R/clr
E1000_SCC	Single Collision Count - R/clr
E1000_SCC	Single Collision Count - R/clr
E1000_SCTL	SerDes Control - RW
E1000_SCTL	SerDes Control - RW
E1000_SEC	Sequence Error Count - R/clr
E1000_SEC	Sequence Error Count - R/clr
e1000_set_d0_lplu_state	This function sets the lplu d0 state according to the active flag. When
e1000_set_d0_lplu_state	This function sets the lplu d0 state according to the active flag. When
e1000_set_d3_lplu_state	This function sets the lplu state according to the active flag. When
e1000_set_d3_lplu_state	This function sets the lplu state according to the active flag. When
e1000_set_mac_type	Set the mac type member in the hw struct.
e1000_set_mac_type	Set the mac type member in the hw struct.
e1000_set_media_type	Set media type and TBI compatibility.
e1000_set_media_type	Set media type and TBI compatibility.
e1000_set_pci_ex_no_snoop	Configure PCI-Ex no-snoop
e1000_set_pci_ex_no_snoop	Configure PCI-Ex no-snoop
e1000_set_pci_express_master_disable	Disables PCI-Express master access.
e1000_set_pci_express_master_disable	Disables PCI-Express master access.
e1000_set_phy_mode	Set PHY to class A mode
e1000_set_phy_mode	Set PHY to class A mode
e1000_set_phy_type	Set the phy type member in the hw struct.
e1000_set_phy_type	Set the phy type member in the hw struct.
e1000_set_vco_speed	Change VCO speed register to improve Bit Error Rate performance of SERDES.
e1000_set_vco_speed	Change VCO speed register to improve Bit Error Rate performance of SERDES.
e1000_setup_copper_link	Detects which PHY is present and setup the speed and duplex
e1000_setup_copper_link	Detects which PHY is present and setup the speed and duplex
e1000_setup_fiber_serdes_link	Sets up link for a fiber based or serdes based adapter
e1000_setup_fiber_serdes_link	Sets up link for a fiber based or serdes based adapter
e1000_setup_led	Prepares SW controlable LED for use and saves the current state of the LED.
e1000_setup_led	Prepares SW controlable LED for use and saves the current state of the LED.
e1000_setup_link	Configures flow control and link settings.
e1000_setup_link	Configures flow control and link settings.
e1000_setup_rx_resources	e1000_setup_rx_resources - allocate Rx resources (Descriptors)
e1000_setup_rx_resources	e1000_setup_rx_resources - allocate Rx resources (Descriptors)
e1000_setup_tx_resources	e1000_setup_tx_resources - allocate Tx resources (Descriptors)
e1000_setup_tx_resources	e1000_setup_tx_resources - allocate Tx resources (Descriptors)
e1000_shadow_ram
e1000_shadow_ram
E1000_SHADOW_RAM_WORDS
E1000_SHADOW_RAM_WORDS
e1000_shift_in_ee_bits	Shift data bits in from the EEPROM
e1000_shift_in_ee_bits	Shift data bits in from the EEPROM
e1000_shift_in_mdi_bits	Shifts data bits in from the PHY
e1000_shift_in_mdi_bits	Shifts data bits in from the PHY
e1000_shift_out_ee_bits	Shift data bits out to the EEPROM.
e1000_shift_out_ee_bits	Shift data bits out to the EEPROM.
e1000_shift_out_mdi_bits	Shifts data bits out to the PHY
e1000_shift_out_mdi_bits	Shifts data bits out to the PHY
e1000_smart_speed
e1000_smart_speed
E1000_SMARTSPEED_DOWNSHIFT
E1000_SMARTSPEED_DOWNSHIFT
E1000_SMARTSPEED_MAX
E1000_SMARTSPEED_MAX
e1000_speed_duplex_type
e1000_speed_duplex_type
e1000_spi_eeprom_ready	Reads a 16 bit word from the EEPROM.
e1000_spi_eeprom_ready	Reads a 16 bit word from the EEPROM.
e1000_standby_eeprom	Returns EEPROM to a "standby" state
e1000_standby_eeprom	Returns EEPROM to a "standby" state
e1000_state_t
e1000_state_t
E1000_STATUS	Device Status - RO
E1000_STATUS	Device Status - RO
E1000_STATUS_ASDV	Auto speed detect value
E1000_STATUS_ASDV	Auto speed detect value
E1000_STATUS_BMC_CRYPTO	BMC crypto disabled
E1000_STATUS_BMC_CRYPTO	BMC crypto disabled
E1000_STATUS_BMC_LITE	BMC external code execution disabled
E1000_STATUS_BMC_LITE	BMC external code execution disabled
E1000_STATUS_BMC_SKU_0	BMC USB redirect disabled
E1000_STATUS_BMC_SKU_0	BMC USB redirect disabled
E1000_STATUS_BMC_SKU_1	BMC SRAM disabled
E1000_STATUS_BMC_SKU_1	BMC SRAM disabled
E1000_STATUS_BMC_SKU_2	BMC SDRAM disabled
E1000_STATUS_BMC_SKU_2	BMC SDRAM disabled
E1000_STATUS_BUS64	In 64 bit slot
E1000_STATUS_BUS64	In 64 bit slot
E1000_STATUS_DOCK_CI	Change in Dock/Undock state. Clear on write '0'.
E1000_STATUS_DOCK_CI	Change in Dock/Undock state. Clear on write '0'.
E1000_STATUS_FD	Full duplex.0=half,1=full
E1000_STATUS_FD	Full duplex.0=half,1=full
E1000_STATUS_FUNC_0	Function 0
E1000_STATUS_FUNC_0	Function 0
E1000_STATUS_FUNC_1	Function 1
E1000_STATUS_FUNC_1	Function 1
E1000_STATUS_FUNC_MASK	PCI Function Mask
E1000_STATUS_FUNC_MASK	PCI Function Mask
E1000_STATUS_FUNC_SHIFT
E1000_STATUS_FUNC_SHIFT
E1000_STATUS_FUSE_8
E1000_STATUS_FUSE_8
E1000_STATUS_FUSE_9
E1000_STATUS_FUSE_9
E1000_STATUS_GIO_MASTER_ENABLE	Status of Master requests.
E1000_STATUS_GIO_MASTER_ENABLE	Status of Master requests.
E1000_STATUS_LAN_INIT_DONE	Lan Init Completion
E1000_STATUS_LAN_INIT_DONE	Lan Init Completion
E1000_STATUS_LU	Link up.0=no,1=link
E1000_STATUS_LU	Link up.0=no,1=link
E1000_STATUS_MTXCKOK	MTX clock running OK
E1000_STATUS_MTXCKOK	MTX clock running OK
E1000_STATUS_PCI66	In 66Mhz slot
E1000_STATUS_PCI66	In 66Mhz slot
E1000_STATUS_PCIX_MODE	PCI-X mode
E1000_STATUS_PCIX_MODE	PCI-X mode
E1000_STATUS_PCIX_SPEED	PCI-X bus speed
E1000_STATUS_PCIX_SPEED	PCI-X bus speed
E1000_STATUS_PCIX_SPEED_100	PCI-X bus speed 66-100 MHz
E1000_STATUS_PCIX_SPEED_100	PCI-X bus speed 66-100 MHz
E1000_STATUS_PCIX_SPEED_133	PCI-X bus speed 100-133 MHz
E1000_STATUS_PCIX_SPEED_133	PCI-X bus speed 100-133 MHz
E1000_STATUS_PCIX_SPEED_66	PCI-X bus speed 50-66 MHz
E1000_STATUS_PCIX_SPEED_66	PCI-X bus speed 50-66 MHz
E1000_STATUS_RGMII_ENABLE	RGMII disabled
E1000_STATUS_RGMII_ENABLE	RGMII disabled
E1000_STATUS_SERDES0_DIS	SERDES disabled on port 0
E1000_STATUS_SERDES0_DIS	SERDES disabled on port 0
E1000_STATUS_SERDES1_DIS	SERDES disabled on port 1
E1000_STATUS_SERDES1_DIS	SERDES disabled on port 1
E1000_STATUS_SPEED_10	Speed 10Mb/s
E1000_STATUS_SPEED_10	Speed 10Mb/s
E1000_STATUS_SPEED_100	Speed 100Mb/s
E1000_STATUS_SPEED_100	Speed 100Mb/s
E1000_STATUS_SPEED_1000	Speed 1000Mb/s
E1000_STATUS_SPEED_1000	Speed 1000Mb/s
E1000_STATUS_SPEED_MASK
E1000_STATUS_SPEED_MASK
E1000_STATUS_TBIMODE	TBI mode
E1000_STATUS_TBIMODE	TBI mode
E1000_STATUS_TXOFF	transmission paused
E1000_STATUS_TXOFF	transmission paused
E1000_STM_OPCODE
E1000_STM_OPCODE
E1000_SUCCESS
E1000_SUCCESS
E1000_SW_FW_SYNC	Software-Firmware Synchronization - RW
E1000_SW_FW_SYNC	Software-Firmware Synchronization - RW
e1000_sw_init	e1000_sw_init - Initialize general software structures (struct e1000_adapter)
e1000_sw_init	e1000_sw_init - Initialize general software structures (struct e1000_adapter)
E1000_SWFW_EEP_SM
E1000_SWFW_EEP_SM
E1000_SWFW_MAC_CSR_SM
E1000_SWFW_MAC_CSR_SM
E1000_SWFW_PHY0_SM
E1000_SWFW_PHY0_SM
E1000_SWFW_PHY1_SM
E1000_SWFW_PHY1_SM
e1000_swfw_sync_acquire
e1000_swfw_sync_acquire
e1000_swfw_sync_release
e1000_swfw_sync_release
E1000_SWSM	SW Semaphore
E1000_SWSM	SW Semaphore
E1000_SWSM_DRV_LOAD	Driver Loaded Bit
E1000_SWSM_DRV_LOAD	Driver Loaded Bit
E1000_SWSM_SMBI	Driver Semaphore bit
E1000_SWSM_SMBI	Driver Semaphore bit
E1000_SWSM_SWESMBI	FW Semaphore bit
E1000_SWSM_SWESMBI	FW Semaphore bit
E1000_SWSM_WMNG	Wake MNG Clock
E1000_SWSM_WMNG	Wake MNG Clock
E1000_SYMERRS	Symbol Error Count - R/clr
E1000_SYMERRS	Symbol Error Count - R/clr
E1000_TADV	TX Interrupt Absolute Delay Val - RW
E1000_TADV	TX Interrupt Absolute Delay Val - RW
E1000_TARC0	TX Arbitration Count (0)
E1000_TARC0	TX Arbitration Count (0)
E1000_TARC1	TX Arbitration Count (1)
E1000_TARC1	TX Arbitration Count (1)
e1000_tbi_adjust_stats	Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
e1000_tbi_adjust_stats	Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
E1000_TBT	TX Burst Timer - RW
E1000_TBT	TX Burst Timer - RW
E1000_TCTL	TX Control - RW
E1000_TCTL	TX Control - RW
E1000_TCTL_BCE	busy check enable
E1000_TCTL_BCE	busy check enable
E1000_TCTL_COLD	collision distance
E1000_TCTL_COLD	collision distance
E1000_TCTL_CT	collision threshold
E1000_TCTL_CT	collision threshold
E1000_TCTL_EN	enable tx
E1000_TCTL_EN	enable tx
E1000_TCTL_EXT	Extended TX Control - RW
E1000_TCTL_EXT	Extended TX Control - RW
E1000_TCTL_EXT_BST_MASK	Backoff Slot Time
E1000_TCTL_EXT_BST_MASK	Backoff Slot Time
E1000_TCTL_EXT_GCEX_MASK	Gigabit Carry Extend Padding
E1000_TCTL_EXT_GCEX_MASK	Gigabit Carry Extend Padding
E1000_TCTL_MULR	Multiple request support
E1000_TCTL_MULR	Multiple request support
E1000_TCTL_NRTU	No Re-transmit on underrun
E1000_TCTL_NRTU	No Re-transmit on underrun
E1000_TCTL_PBE	Packet Burst Enable
E1000_TCTL_PBE	Packet Burst Enable
E1000_TCTL_PSP	pad short packets
E1000_TCTL_PSP	pad short packets
E1000_TCTL_RST	software reset
E1000_TCTL_RST	software reset
E1000_TCTL_RTLC	Re-transmit on late collision
E1000_TCTL_RTLC	Re-transmit on late collision
E1000_TCTL_SWXOFF	SW Xoff transmission
E1000_TCTL_SWXOFF	SW Xoff transmission
E1000_TDBAH	TX Descriptor Base Address High - RW
E1000_TDBAH	TX Descriptor Base Address High - RW
E1000_TDBAH1	TX Desc Base Address High (1) - RW
E1000_TDBAH1	TX Desc Base Address High (1) - RW
E1000_TDBAL	TX Descriptor Base Address Low - RW
E1000_TDBAL	TX Descriptor Base Address Low - RW
E1000_TDBAL1	TX Desc Base Address Low (1) - RW
E1000_TDBAL1	TX Desc Base Address Low (1) - RW
E1000_TDFH	TX Data FIFO Head - RW
E1000_TDFH	TX Data FIFO Head - RW
E1000_TDFHS	TX Data FIFO Head Saved - RW
E1000_TDFHS	TX Data FIFO Head Saved - RW
E1000_TDFPC	TX Data FIFO Packet Count - RW
E1000_TDFPC	TX Data FIFO Packet Count - RW
E1000_TDFT	TX Data FIFO Tail - RW
E1000_TDFT	TX Data FIFO Tail - RW
E1000_TDFTS	TX Data FIFO Tail Saved - RW
E1000_TDFTS	TX Data FIFO Tail Saved - RW
E1000_TDH	TX Descriptor Head - RW
E1000_TDH	TX Descriptor Head - RW
E1000_TDH1	TX Desc Head (1) - RW
E1000_TDH1	TX Desc Head (1) - RW
E1000_TDLEN	TX Descriptor Length - RW
E1000_TDLEN	TX Descriptor Length - RW
E1000_TDLEN1	TX Desc Length (1) - RW
E1000_TDLEN1	TX Desc Length (1) - RW
E1000_TDT	TX Descripotr Tail - RW
E1000_TDT	TX Descripotr Tail - RW
E1000_TDT1	TX Desc Tail (1) - RW
E1000_TDT1	TX Desc Tail (1) - RW
E1000_TIDV	TX Interrupt Delay Value - RW
E1000_TIDV	TX Interrupt Delay Value - RW
E1000_TIPG	TX Inter-packet gap -RW
E1000_TIPG	TX Inter-packet gap -RW
E1000_TIPG_IPGR1_MASK
E1000_TIPG_IPGR1_MASK
E1000_TIPG_IPGR1_SHIFT
E1000_TIPG_IPGR1_SHIFT
E1000_TIPG_IPGR2_MASK
E1000_TIPG_IPGR2_MASK
E1000_TIPG_IPGR2_SHIFT
E1000_TIPG_IPGR2_SHIFT
E1000_TIPG_IPGT_MASK
E1000_TIPG_IPGT_MASK
E1000_TNCRS	TX-No CRS - R/clr
E1000_TNCRS	TX-No CRS - R/clr
E1000_TORH	Total Octets RX High - R/clr
E1000_TORH	Total Octets RX High - R/clr
E1000_TORL	Total Octets RX Low - R/clr
E1000_TORL	Total Octets RX Low - R/clr
E1000_TOTH	Total Octets TX High - R/clr
E1000_TOTH	Total Octets TX High - R/clr
E1000_TOTL	Total Octets TX Low - R/clr
E1000_TOTL	Total Octets TX Low - R/clr
E1000_TPR	Total Packets RX - R/clr
E1000_TPR	Total Packets RX - R/clr
E1000_TPT	Total Packets TX - R/clr
E1000_TPT	Total Packets TX - R/clr
e1000_transmit	e1000_transmit - Transmit a packet
e1000_transmit	e1000_transmit - Transmit a packet
E1000_TSCTC	TCP Segmentation Context TX - R/clr
E1000_TSCTC	TCP Segmentation Context TX - R/clr
E1000_TSCTFC	TCP Segmentation Context TX Fail - R/clr
E1000_TSCTFC	TCP Segmentation Context TX Fail - R/clr
E1000_TSPMT	TCP Segmentation PAD & Min Threshold - RW
E1000_TSPMT	TCP Segmentation PAD & Min Threshold - RW
E1000_TX_BUFFER_SIZE
E1000_TX_BUFFER_SIZE
e1000_tx_desc
e1000_tx_desc
E1000_TX_DESC(R, i)
E1000_TX_DESC(R, i)
E1000_TX_HEAD_ADDR_SHIFT
E1000_TX_HEAD_ADDR_SHIFT
E1000_TX_QUEUE_WAKE
E1000_TX_QUEUE_WAKE
e1000_tx_ring
e1000_tx_ring
E1000_TXCW	TX Configuration Word - RW
E1000_TXCW	TX Configuration Word - RW
E1000_TXCW_ANE	Auto-neg enable
E1000_TXCW_ANE	Auto-neg enable
E1000_TXCW_ASM_DIR	TXCW astm pause direction
E1000_TXCW_ASM_DIR	TXCW astm pause direction
E1000_TXCW_CW	TxConfigWord mask
E1000_TXCW_CW	TxConfigWord mask
E1000_TXCW_FD	TXCW full duplex
E1000_TXCW_FD	TXCW full duplex
E1000_TXCW_HD	TXCW half duplex
E1000_TXCW_HD	TXCW half duplex
E1000_TXCW_NP	TXCW next page
E1000_TXCW_NP	TXCW next page
E1000_TXCW_PAUSE	TXCW sym pause request
E1000_TXCW_PAUSE	TXCW sym pause request
E1000_TXCW_PAUSE_MASK	TXCW pause request mask
E1000_TXCW_PAUSE_MASK	TXCW pause request mask
E1000_TXCW_RF	TXCW remote fault
E1000_TXCW_RF	TXCW remote fault
E1000_TXCW_TXC	Transmit Config control
E1000_TXCW_TXC	Transmit Config control
E1000_TXD_CMD_DEXT	Descriptor extension (0 = legacy)
E1000_TXD_CMD_DEXT	Descriptor extension (0 = legacy)
E1000_TXD_CMD_EOP	End of Packet
E1000_TXD_CMD_EOP	End of Packet
E1000_TXD_CMD_IC	Insert Checksum
E1000_TXD_CMD_IC	Insert Checksum
E1000_TXD_CMD_IDE	Enable Tidv register
E1000_TXD_CMD_IDE	Enable Tidv register
E1000_TXD_CMD_IFCS	Insert FCS (Ethernet CRC)
E1000_TXD_CMD_IFCS	Insert FCS (Ethernet CRC)
E1000_TXD_CMD_IP	IP packet
E1000_TXD_CMD_IP	IP packet
E1000_TXD_CMD_RPS	Report Packet Sent
E1000_TXD_CMD_RPS	Report Packet Sent
E1000_TXD_CMD_RS	Report Status
E1000_TXD_CMD_RS	Report Status
E1000_TXD_CMD_TCP	TCP packet
E1000_TXD_CMD_TCP	TCP packet
E1000_TXD_CMD_TSE	TCP Seg enable
E1000_TXD_CMD_TSE	TCP Seg enable
E1000_TXD_CMD_VLE	Add VLAN tag
E1000_TXD_CMD_VLE	Add VLAN tag
E1000_TXD_DTYP_C	Context Descriptor
E1000_TXD_DTYP_C	Context Descriptor
E1000_TXD_DTYP_D	Data Descriptor
E1000_TXD_DTYP_D	Data Descriptor
E1000_TXD_POPTS_IXSM	Insert IP checksum
E1000_TXD_POPTS_IXSM	Insert IP checksum
E1000_TXD_POPTS_TXSM	Insert TCP/UDP checksum
E1000_TXD_POPTS_TXSM	Insert TCP/UDP checksum
E1000_TXD_STAT_DD	Descriptor Done
E1000_TXD_STAT_DD	Descriptor Done
E1000_TXD_STAT_EC	Excess Collisions
E1000_TXD_STAT_EC	Excess Collisions
E1000_TXD_STAT_LC	Late Collisions
E1000_TXD_STAT_LC	Late Collisions
E1000_TXD_STAT_TC	Tx Underrun
E1000_TXD_STAT_TC	Tx Underrun
E1000_TXD_STAT_TU	Transmit underrun
E1000_TXD_STAT_TU	Transmit underrun
E1000_TXDCTL	TX Descriptor Control - RW
E1000_TXDCTL	TX Descriptor Control - RW
E1000_TXDCTL_COUNT_DESC	Enable the counting of desc.
E1000_TXDCTL_COUNT_DESC	Enable the counting of desc.
E1000_TXDCTL_FULL_TX_DESC_WB	GRAN=1, WTHRESH=1
E1000_TXDCTL_FULL_TX_DESC_WB	GRAN=1, WTHRESH=1
E1000_TXDCTL_GRAN	TXDCTL Granularity
E1000_TXDCTL_GRAN	TXDCTL Granularity
E1000_TXDCTL_HTHRESH	TXDCTL Host Threshold
E1000_TXDCTL_HTHRESH	TXDCTL Host Threshold
E1000_TXDCTL_LWTHRESH	TXDCTL Low Threshold
E1000_TXDCTL_LWTHRESH	TXDCTL Low Threshold
E1000_TXDCTL_PTHRESH	TXDCTL Prefetch Threshold
E1000_TXDCTL_PTHRESH	TXDCTL Prefetch Threshold
E1000_TXDCTL_QUEUE_ENABLE	Enable specific Tx Queue
E1000_TXDCTL_QUEUE_ENABLE	Enable specific Tx Queue
E1000_TXDCTL_WTHRESH	TXDCTL Writeback Threshold
E1000_TXDCTL_WTHRESH	TXDCTL Writeback Threshold
E1000_TXDCTL1	TX Descriptor Control (1) - RW
E1000_TXDCTL1	TX Descriptor Control (1) - RW
E1000_TXDMAC	TX DMA Control - RW
E1000_TXDMAC	TX DMA Control - RW
E1000_TXDMAC_DPP
E1000_TXDMAC_DPP
e1000_update_adaptive	Called during the callback/watchdog routine to update IFS value based on
e1000_update_adaptive	Called during the callback/watchdog routine to update IFS value based on
e1000_update_eeprom_checksum	Calculates the EEPROM checksum and writes it to the EEPROM
e1000_update_eeprom_checksum	Calculates the EEPROM checksum and writes it to the EEPROM
e1000_validate_eeprom_checksum	Verifies that the EEPROM has a valid checksum
e1000_validate_eeprom_checksum	Verifies that the EEPROM has a valid checksum
e1000_validate_mdi_setting
e1000_validate_mdi_setting
e1000_verify_write_ich8_byte	Writes a single byte to the NVM using the ICH8 flash access registers.
e1000_verify_write_ich8_byte	Writes a single byte to the NVM using the ICH8 flash access registers.
E1000_VET	VLAN Ether Type - RW
E1000_VET	VLAN Ether Type - RW
E1000_VFTA	VLAN Filter Table Array - RW Array
E1000_VFTA	VLAN Filter Table Array - RW Array
E1000_VFTA_ENTRY_BIT_SHIFT_MASK
E1000_VFTA_ENTRY_BIT_SHIFT_MASK
E1000_VFTA_ENTRY_MASK
E1000_VFTA_ENTRY_MASK
E1000_VFTA_ENTRY_SHIFT
E1000_VFTA_ENTRY_SHIFT
E1000_VLAN_FILTER_TBL_SIZE	VLAN Filter Table (4096 bits)
E1000_VLAN_FILTER_TBL_SIZE	VLAN Filter Table (4096 bits)
e1000_wait_autoneg	Blocks until autoneg completes or times out (~4.5 seconds)
e1000_wait_autoneg	Blocks until autoneg completes or times out (~4.5 seconds)
E1000_WAKEUP_IP_ADDRESS_COUNT_M
E1000_WAKEUP_IP_ADDRESS_COUNT_M
e1000_write_eeprom	Parent function for writing words to the different EEPROM types.
e1000_write_eeprom	Parent function for writing words to the different EEPROM types.
e1000_write_eeprom_eewr	Writes a 16 bit word from the EEPROM using the EEWR register.
e1000_write_eeprom_eewr	Writes a 16 bit word from the EEPROM using the EEWR register.
e1000_write_eeprom_ich8	Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
e1000_write_eeprom_ich8	Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
e1000_write_eeprom_microwire	Writes a 16 bit word to a given offset in a Microwire EEPROM.
e1000_write_eeprom_microwire	Writes a 16 bit word to a given offset in a Microwire EEPROM.
e1000_write_eeprom_spi	Writes a 16 bit word to a given offset in an SPI EEPROM.
e1000_write_eeprom_spi	Writes a 16 bit word to a given offset in an SPI EEPROM.
E1000_WRITE_FLUSH(a)
E1000_WRITE_FLUSH(a)
E1000_WRITE_ICH_FLASH_REG(a, reg, value)
E1000_WRITE_ICH_FLASH_REG(a, reg, value)
E1000_WRITE_ICH_FLASH_REG16(a, reg, value)
E1000_WRITE_ICH_FLASH_REG16(a, reg, value)
e1000_write_ich8_byte	Writes a single byte to the NVM using the ICH8 flash access registers.
e1000_write_ich8_byte	Writes a single byte to the NVM using the ICH8 flash access registers.
e1000_write_ich8_data	Writes One /two bytes to the NVM using the ICH8 flash access registers.
e1000_write_ich8_data	Writes One /two bytes to the NVM using the ICH8 flash access registers.
e1000_write_kmrn_reg
e1000_write_kmrn_reg
e1000_write_pci_cfg
e1000_write_pci_cfg
e1000_write_phy_reg	Writes a value to a PHY register
e1000_write_phy_reg	Writes a value to a PHY register
e1000_write_phy_reg_ex
e1000_write_phy_reg_ex
E1000_WRITE_REG(a, reg, value)
E1000_WRITE_REG(a, reg, value)
E1000_WRITE_REG_ARRAY(a, reg, offset, value)
E1000_WRITE_REG_ARRAY(a, reg, offset, value)
E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value)
E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value)
E1000_WRITE_REG_ARRAY_DWORD
E1000_WRITE_REG_ARRAY_DWORD
E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value)
E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value)
e1000_write_reg_io	Writes a value to one of the devices registers using port I/O (as opposed to
e1000_write_reg_io	Writes a value to one of the devices registers using port I/O (as opposed to
E1000_WRITE_REG_IO(a, reg, val)
E1000_WRITE_REG_IO(a, reg, val)
e1000_write_vfta	Writes a value to the specified offset in the VLAN filter table.
e1000_write_vfta	Writes a value to the specified offset in the VLAN filter table.
E1000_WUC	Wakeup Control - RW
E1000_WUC	Wakeup Control - RW
E1000_WUC_APME	APM Enable
E1000_WUC_APME	APM Enable
E1000_WUC_APMPME	Assert PME on APM Wakeup
E1000_WUC_APMPME	Assert PME on APM Wakeup
E1000_WUC_PME_EN	PME Enable
E1000_WUC_PME_EN	PME Enable
E1000_WUC_PME_STATUS	PME Status
E1000_WUC_PME_STATUS	PME Status
E1000_WUC_SPM	Enable SPM
E1000_WUC_SPM	Enable SPM
E1000_WUFC	Wakeup Filter Control - RW
E1000_WUFC	Wakeup Filter Control - RW
E1000_WUFC_ALL_FILTERS	Mask for all wakeup filters
E1000_WUFC_ALL_FILTERS	Mask for all wakeup filters
E1000_WUFC_ARP	ARP Request Packet Wakeup Enable
E1000_WUFC_ARP	ARP Request Packet Wakeup Enable
E1000_WUFC_BC	Broadcast Wakeup Enable
E1000_WUFC_BC	Broadcast Wakeup Enable
E1000_WUFC_EX	Directed Exact Wakeup Enable
E1000_WUFC_EX	Directed Exact Wakeup Enable
E1000_WUFC_FLX_FILTERS	Mask for the 4 flexible filters
E1000_WUFC_FLX_FILTERS	Mask for the 4 flexible filters
E1000_WUFC_FLX_OFFSET	Offset to the Flexible Filters bits
E1000_WUFC_FLX_OFFSET	Offset to the Flexible Filters bits
E1000_WUFC_FLX0	Flexible Filter 0 Enable
E1000_WUFC_FLX0	Flexible Filter 0 Enable
E1000_WUFC_FLX1	Flexible Filter 1 Enable
E1000_WUFC_FLX1	Flexible Filter 1 Enable
E1000_WUFC_FLX2	Flexible Filter 2 Enable
E1000_WUFC_FLX2	Flexible Filter 2 Enable
E1000_WUFC_FLX3	Flexible Filter 3 Enable
E1000_WUFC_FLX3	Flexible Filter 3 Enable
E1000_WUFC_IGNORE_TCO	Ignore WakeOn TCO packets
E1000_WUFC_IGNORE_TCO	Ignore WakeOn TCO packets
E1000_WUFC_IPV4	Directed IPv4 Packet Wakeup Enable
E1000_WUFC_IPV4	Directed IPv4 Packet Wakeup Enable
E1000_WUFC_IPV6	Directed IPv6 Packet Wakeup Enable
E1000_WUFC_IPV6	Directed IPv6 Packet Wakeup Enable
E1000_WUFC_LNKC	Link Status Change Wakeup Enable
E1000_WUFC_LNKC	Link Status Change Wakeup Enable
E1000_WUFC_MAG	Magic Packet Wakeup Enable
E1000_WUFC_MAG	Magic Packet Wakeup Enable
E1000_WUFC_MC	Directed Multicast Wakeup Enable
E1000_WUFC_MC	Directed Multicast Wakeup Enable
E1000_WUPL	Wakeup Packet Length - RW
E1000_WUPL	Wakeup Packet Length - RW
E1000_WUPL_LENGTH_MASK	Only the lower 12 bits are valid
E1000_WUPL_LENGTH_MASK	Only the lower 12 bits are valid
E1000_WUPM	Wakeup Packet Memory - RO A
E1000_WUPM	Wakeup Packet Memory - RO A
E1000_WUS	Wakeup Status - RO
E1000_WUS	Wakeup Status - RO
E1000_WUS_ARP	ARP Request Packet Received
E1000_WUS_ARP	ARP Request Packet Received
E1000_WUS_BC	Broadcast Received
E1000_WUS_BC	Broadcast Received
E1000_WUS_EX	Directed Exact Received
E1000_WUS_EX	Directed Exact Received
E1000_WUS_FLX_FILTERS	Mask for the 4 flexible filters
E1000_WUS_FLX_FILTERS	Mask for the 4 flexible filters
E1000_WUS_FLX0	Flexible Filter 0 Match
E1000_WUS_FLX0	Flexible Filter 0 Match
E1000_WUS_FLX1	Flexible Filter 1 Match
E1000_WUS_FLX1	Flexible Filter 1 Match
E1000_WUS_FLX2	Flexible Filter 2 Match
E1000_WUS_FLX2	Flexible Filter 2 Match
E1000_WUS_FLX3	Flexible Filter 3 Match
E1000_WUS_FLX3	Flexible Filter 3 Match
E1000_WUS_IPV4	Directed IPv4 Packet Wakeup Received
E1000_WUS_IPV4	Directed IPv4 Packet Wakeup Received
E1000_WUS_IPV6	Directed IPv6 Packet Wakeup Received
E1000_WUS_IPV6	Directed IPv6 Packet Wakeup Received
E1000_WUS_LNKC	Link Status Changed
E1000_WUS_LNKC	Link Status Changed
E1000_WUS_MAG	Magic Packet Received
E1000_WUS_MAG	Magic Packet Received
E1000_WUS_MC	Directed Multicast Received
E1000_WUS_MC	Directed Multicast Received
E1000_XOFFRXC	XOFF RX Count - R/clr
E1000_XOFFRXC	XOFF RX Count - R/clr
E1000_XOFFTXC	XOFF TX Count - R/clr
E1000_XOFFTXC	XOFF TX Count - R/clr
E1000_XONRXC	XON RX Count - R/clr
E1000_XONRXC	XON RX Count - R/clr
E1000_XONTXC	XON TX Count - R/clr
E1000_XONTXC	XON TX Count - R/clr
E2BIG
E80211_REASON( reas )
E80211_STATUS( stat )
E820_ATTR_ENABLED
E820_ATTR_NONVOLATILE
E820_ATTR_UNKNOWN
e820_entry
e820_entry
E820_MIN_SIZE
E820_TYPE_ACPI	*< ACPI reclaim memory
E820_TYPE_ACPI	*< ACPI reclaim memory
E820_TYPE_NVS	*< ACPI NVS memory
E820_TYPE_NVS	*< ACPI NVS memory
E820_TYPE_RAM	*< Normal memory
E820_TYPE_RAM	*< Normal memory
E820_TYPE_RESERVED	*< Reserved and unavailable
E820_TYPE_RSVD	*< Reserved and unavailable
e820buf
e820map
EACCES
EADDRINUSE
EADDRNOTAVAIL
EAFNOSUPPORT
EAGAIN
EALREADY
EarlyTxThld	0x3F means NO early transmit
EarlyTxThld	0x3F means NO early transmit
EBADF
EBADMSG
ebinfo
ebpdriver_t
ebpstatus_t
EBUSY
EBUSY
EBUSY
ECANCELED
ECHILD
echo
echo_exec	The "echo" command
echo_exec	The "echo" command
ecollect_free	Collect free blocks
ECONNABORTED
ECONNREFUSED
ECONNRESET
EDEADLK
EDESTADDRREQ
edging.c
edit_box
edit_box_flags
edit_setting	Edit setting widget
edit_string	Edit editable string
edit_string	Edit editable string
edit_string
editbox.c
editbox.h
EDITBOX_COL
EDITBOX_MIN_CHARS
EDITBOX_WIDTH
editstring.c
editstring.c
editstring.h
EDOM
EDQUOT
ee_addr_CRC_8	CRC over last thee Bytes
ee_addr_CRC_8	CRC over last thee Bytes
ee_addr_id	Word offset for Card ID
ee_addr_id	Word offset for Card ID
ee_addr_SN	Serial Number
ee_addr_SN	Serial Number
ee_addr_vendor	Word offset for EISA Vendor ID
ee_addr_vendor	Word offset for EISA Vendor ID
EE_ALLOW_FDX
EE_ALLOW_FDX
ee_AltReady	Alternate Ready, 0=normal
ee_AltReady	Alternate Ready, 0=normal
EE_AUTO_NEG_CNF_MASK
EE_AUTO_NEG_CNF_MASK
EE_AUTO_NEG_ENABLE
EE_AUTO_NEG_ENABLE
ee_AutoIO
ee_AutoIO
ee_AutoNeg	Auto Negotiation enabled?
ee_AutoNeg	Auto Negotiation enabled?
ee_AutoPort	Auto Port Selection 1= Disabled
ee_AutoPort	Auto Port Selection 1= Disabled
ee_BNC_TPE	0=TPE
ee_BNC_TPE	0=TPE
ee_BoardID	Manucaturer Board ID, reserved
ee_BoardID	Manucaturer Board ID, reserved
ee_BoardMask
ee_BoardMask
ee_BootType	00=None, 01=IPX, 10=ODI, 11=NDIS
ee_BootType	00=None, 01=IPX, 10=ODI, 11=NDIS
ee_BootTypeMask
ee_BootTypeMask
ee_BusWidth	8/16 bit
ee_BusWidth	8/16 bit
ee_Checksum	initial and final value for adding checksum
ee_Checksum	initial and final value for adding checksum
ee_CP	Concurrent Processing
ee_CP	Concurrent Processing
ee_CPMask
ee_CPMask
EE_CS	EEPROM chip select.
EE_CS	EEPROM chip select.
EE_CS	EEPROM chip select.
EE_CS	EEPROM chip select
EE_CS	EEPROM chip select.
EE_CS	EEPROM chip select
EE_CS	EEPROM chip select.
EE_CS	EEPROM chip select.
EE_CS	EEPROM chip select
EE_CS	EEPROM chip select.
EE_CS	EEPROM chip select.
EE_CS	EEPROM chip select
EE_DATA_READ	EEPROM chip data out.
EE_DATA_READ	EEPROM chip data out.
EE_DATA_READ	EEPROM chip data out.
EE_DATA_READ	EEPROM chip data out.
EE_DATA_READ	EEPROM chip data out.
EE_DATA_READ	EEPROM chip data out.
EE_DATA_READ	EEPROM chip data out.
EE_DATA_READ	EEPROM chip data out.
EE_DATA_WRITE	EEPROM chip data in.
EE_DATA_WRITE	EEPROM chip data in.
EE_DATA_WRITE	EEPROM chip data in.
EE_DATA_WRITE	EEPROM chip data in.
EE_DATA_WRITE	EEPROM chip data in.
EE_DATA_WRITE	EEPROM chip data in.
EE_DATA_WRITE	EEPROM chip data in.
EE_DATA_WRITE	EEPROM chip data in.
EE_DI	Data in
EE_DI	Data in
EE_DI	Data in
EE_DI	Data in
EE_DO	Data out
EE_DO	Data out
EE_DO	Data out
EE_DO	Data out
ee_Duplex
ee_Duplex
EE_ENB
EE_ENB
EE_ENB
EE_ENB
EE_ENB
EE_ENB
EE_ENB
EE_ENB
EE_ERASE_CMD
EE_ERASE_CMD
EE_ERASE_CMD
EE_ERASE_CMD
EE_ERASE_CMD
EE_ERASE_CMD
ee_Flash	Flash there?
ee_Flash	Flash there?
ee_FlashAddr	Flash Address
ee_FlashAddr	Flash Address
ee_FlashMask	Mask
ee_FlashMask	Mask
ee_FlashSock	Presence of Flash Socket 0= Present
ee_FlashSock	Presence of Flash Socket 0= Present
EE_FORCE_FDX
EE_FORCE_FDX
ee_FX_INT2IRQ	the _only_ mapping allowed for FX chips
ee_FX_INT2IRQ	the _only_ mapping allowed for FX chips
ee_IA0	bit start for individual Addr Byte 5
ee_IA0	bit start for individual Addr Byte 5
ee_IA1	bit start for individual Addr Byte 5
ee_IA1	bit start for individual Addr Byte 5
ee_IA2	bit start for individual Addr Byte 5
ee_IA2	bit start for individual Addr Byte 5
ee_IA3	bit start for individual Addr Byte 5
ee_IA3	bit start for individual Addr Byte 5
ee_IA4	bit start for individual Addr Byte 5
ee_IA4	bit start for individual Addr Byte 5
ee_IA5	bit start for individual Addr Byte 5
ee_IA5	bit start for individual Addr Byte 5
ee_id_eepro10p0	ID for eepro/10+
ee_id_eepro10p0	ID for eepro/10+
ee_id_eepro10p1
ee_id_eepro10p1
ee_INT_TO_IRQ	int to IRQ Mapping = 0x1EB8 for Pro/10+
ee_INT_TO_IRQ	int to IRQ Mapping = 0x1EB8 for Pro/10+
ee_IntMask
ee_IntMask
ee_IntSel	Interrupt
ee_IntSel	Interrupt
ee_IO0	IO Address LSB
ee_IO0	IO Address LSB
ee_IO0Mask	...
ee_IO0Mask	...
ee_IO1	IO MSB
ee_IO1	IO MSB
ee_Jabber	Jabber prevention 0= enabled
ee_Jabber	Jabber prevention 0= enabled
ee_LI	Link Integrity 0= enabled
ee_LI	Link Integrity 0= enabled
EE_M0	Mode select bit 0
EE_M0	Mode select bit 0
EE_M1	Mode select bit 1
EE_M1	Mode select bit 1
EE_MAC
EE_MAC
EE_MAC
EE_MAC
EE_NLP_ENABLE
EE_NLP_ENABLE
ee_NumConn	Number of Connections 0= One or Two
ee_NumConn	Number of Connections 0= One or Two
ee_PC	Polarity Correction 0= enabled
ee_PC	Polarity Correction 0= enabled
ee_PnP	Plug 'n Play enable bit
ee_PnP	Plug 'n Play enable bit
ee_PortAUI
ee_PortAUI
ee_PortBNC
ee_PortBNC
ee_PortTPE
ee_PortTPE
ee_PowerMgt	0= disabled
ee_PowerMgt	0= disabled
ee_PROM	Flash EPROM / PROM 0=Flash
ee_PROM	Flash EPROM / PROM 0=Flash
EE_READ_CMD
EE_READ_CMD
EE_READ_CMD
EE_READ_CMD
EE_READ_CMD
EE_READ_CMD
EE_READ_CMD
EE_READ_CMD
EE_READ_CMD
EE_REG
EE_REG
ee_reserved0	=0!
ee_reserved0	=0!
ee_reserved1	.. 12 =0!
ee_reserved1	.. 12 =0!
ee_reserved2	=0!
ee_reserved2	=0!
EE_SHIFT_CLK	EEPROM shift clock.
EE_SHIFT_CLK	EEPROM shift clock.
EE_SHIFT_CLK	EEPROM shift clock.
EE_SHIFT_CLK	EEPROM shift clock.
EE_SHIFT_CLK	EEPROM shift clock.
EE_SHIFT_CLK	EEPROM shift clock.
EE_SHIFT_CLK	EEPROM shift clock.
EE_SHIFT_CLK	EEPROM shift clock.
ee_SIZE	total EEprom Size
ee_SIZE	total EEprom Size
EE_SIZE_64
EE_SIZE_64
EE_SK	EEPROM shift clock
EE_SK	EEPROM shift clock
EE_SK	EEPROM shift clock
EE_SK	EEPROM shift clock
ee_SMOUT	SMout Pin Control 0= Input
ee_SMOUT	SMout Pin Control 0= Input
ee_StepMask
ee_StepMask
ee_Stepping	Stepping info
ee_Stepping	Stepping info
ee_TPE_AUI	PortSelection 1=TPE
ee_TPE_AUI	PortSelection 1=TPE
ee_vendor_intel0	Vendor ID Intel
ee_vendor_intel0	Vendor ID Intel
ee_vendor_intel1
ee_vendor_intel1
ee_Word1	Word 1?
ee_Word1	Word 1?
EE_WRITE_0
EE_WRITE_0
EE_WRITE_0
EE_WRITE_0
EE_WRITE_0
EE_WRITE_0
EE_WRITE_0
EE_WRITE_1
EE_WRITE_1
EE_WRITE_1
EE_WRITE_1
EE_WRITE_1
EE_WRITE_1
EE_WRITE_1
EE_WRITE_CMD
EE_WRITE_CMD
EE_WRITE_CMD
EE_WRITE_CMD
EE_WRITE_CMD
EE_WRITE_CMD
EE_Write0
EE_Write0
EE_Write1
EE_Write1
EECS
EECS
EECSR_AUTOLD	eeprom content reload
EECSR_AUTOLD	eeprom content reload
EECSR_CS	eeprom CS pin
EECSR_CS	eeprom CS pin
EECSR_DI	eeprom DI pin
EECSR_DI	eeprom DI pin
EECSR_DO	eeprom DO pin
EECSR_DO	eeprom DO pin
EECSR_DPM	eeprom direct programming
EECSR_DPM	eeprom direct programming
EECSR_DPM	eeprom direct programming
EECSR_DPM	eeprom direct programming
EECSR_ECK	eeprom CK pin
EECSR_ECK	eeprom CK pin
EECSR_ECS	eeprom CS pin
EECSR_ECS	eeprom CS pin
EECSR_EDI	eeprom DI pin
EECSR_EDI	eeprom DI pin
EECSR_EDO	eeprom DO pin
EECSR_EDO	eeprom DO pin
EECSR_EEPR	eeprom programed status, 73h means programed
EECSR_EEPR	eeprom programed status, 73h means programed
EECSR_EMBP	eeprom embeded programming
EECSR_EMBP	eeprom embeded programming
EECSR_EMBP	eeprom embeded programming
EECSR_EMBP	eeprom embeded programming
EECSR_RELOAD	eeprom content reload
EECSR_RELOAD	eeprom content reload
EECSR_SK	eeprom SK pin
EECSR_SK	eeprom SK pin
EEDI
EEDI
EEDO
EEDO
eepro.c
eepro.c
eepro_clear_int(ioaddr)
eepro_clear_int(ioaddr)
eepro_dis_rx(ioaddr)
eepro_dis_rx(ioaddr)
eepro_disable	DISABLE - Turn off ethernet interface
eepro_disable	DISABLE - Turn off ethernet interface
eepro_en_rx(ioaddr)
eepro_en_rx(ioaddr)
eepro_full_reset(ioaddr)
eepro_full_reset(ioaddr)
eepro_irq	DISABLE - Enable, Disable, or Force interrupts
eepro_irq	DISABLE - Enable, Disable, or Force interrupts
eepro_poll	POLL - Wait for a frame
eepro_poll	POLL - Wait for a frame
eepro_probe	PROBE - Look for an adapter, this routine's visible to the outside
eepro_probe	PROBE - Look for an adapter, this routine's visible to the outside
eepro_probe1
eepro_probe1
eepro_reset	RESET - Reset adapter
eepro_reset	RESET - Reset adapter
eepro_sel_reset(ioaddr)
eepro_sel_reset(ioaddr)
eepro_sw2bank0(ioaddr)
eepro_sw2bank0(ioaddr)
eepro_sw2bank1(ioaddr)
eepro_sw2bank1(ioaddr)
eepro_sw2bank2(ioaddr)
eepro_sw2bank2(ioaddr)
eepro_transmit	TRANSMIT - Transmit a frame
eepro_transmit	TRANSMIT - Transmit a frame
eepro100.c
eepro100.c
eepro100.h
eepro100_bufs __shared
eepro100_disable
eepro100_irq
eepro100_poll
eepro100_probe
eepro100_transmit
eeprom
eeprom
eeprom.h
eeprom.h
EEPROM_A8_OPCODE_SPI	opcode bit-3 = address bit-8
EEPROM_A8_OPCODE_SPI	opcode bit-3 = address bit-8
EEPROM_ADDR_ADDR_MASK
EEPROM_ADDR_ADDR_MASK
EEPROM_ADDR_ADDR_SHIFT
EEPROM_ADDR_ADDR_SHIFT
EEPROM_ADDR_CFG	Base addr
EEPROM_ADDR_CFG	Base addr
EEPROM_ADDR_CFG	Base addr
EEPROM_ADDR_CFG	Base addr
EEPROM_ADDR_CLKPERD_SHIFT
EEPROM_ADDR_CLKPERD_SHIFT
EEPROM_ADDR_COMPLETE
EEPROM_ADDR_COMPLETE
EEPROM_ADDR_DEVID_MASK
EEPROM_ADDR_DEVID_MASK
EEPROM_ADDR_DEVID_SHIFT
EEPROM_ADDR_DEVID_SHIFT
EEPROM_ADDR_FSM_RESET
EEPROM_ADDR_FSM_RESET
EEPROM_ADDR_MAC_0
EEPROM_ADDR_MDIO_REGISTER
EEPROM_ADDR_READ
EEPROM_ADDR_READ
EEPROM_ADDR_START
EEPROM_ADDR_START
EEPROM_ADDR_WRITE
EEPROM_ADDR_WRITE
EEPROM_ADDRLEN
EEPROM_ADDRLEN
EEPROM_ADDRLEN
EEPROM_ADDRLEN
EEPROM_ALT_MAC_ADDR_PTR
EEPROM_BUSY
EEPROM_BUSY
EEPROM_BUSY
EEPROM_BUSY
EEPROM_CFG
EEPROM_CFG
EEPROM_CHECKSUM_REG
EEPROM_CHECKSUM_REG
EEPROM_CHIP_SIZE
EEPROM_CHIP_SIZE
EEPROM_CMD_ERASE	Erase: Address required (5 bits)
EEPROM_CMD_ERASE	Erase: Address required (5 bits)
EEPROM_CMD_ERASE	Erase: Address required (5 bits)
EEPROM_CMD_ERASE	Erase: Address required (5 bits)
EEPROM_CMD_EWEN	Erase/Write Enable: No data required
EEPROM_CMD_EWEN	Erase/Write Enable: No data required
EEPROM_CMD_EWEN	Erase/Write Enable: No data required
EEPROM_CMD_EWEN	Erase/Write Enable: No data required
EEPROM_CMD_RD	Read: Address required (5 bits)
EEPROM_CMD_RD	Read: Address required (5 bits)
EEPROM_CMD_RD	Read: Address required (5 bits)
EEPROM_CMD_RD	Read: Address required (5 bits)
EEPROM_CMD_WR	Write: Address required (5 bits)
EEPROM_CMD_WR	Write: Address required (5 bits)
EEPROM_CMD_WR	Write: Address required (5 bits)
EEPROM_CMD_WR	Write: Address required (5 bits)
EEPROM_Cmds
EEPROM_Cmds
EEPROM_Cmds
EEPROM_Cmds
EEPROM_COMPAT
EEPROM_COMPAT
EEPROM_Ctrl_Bits
EEPROM_Ctrl_Bits
EEPROM_Ctrl_Bits
EEPROM_Ctrl_Bits
EEPROM_DEFAULT_CLOCK_PERIOD
EEPROM_DEFAULT_CLOCK_PERIOD
eeprom_delay()
eeprom_delay()
eeprom_delay()
eeprom_delay()
eeprom_delay()
eeprom_delay()
eeprom_delay()
eeprom_delay()
eeprom_delay(ee_addr)
eeprom_delay(ee_addr)
eeprom_delay(ee_addr)
eeprom_delay(ee_addr)
eeprom_delay(n)
eeprom_delay(n)
EEPROM_ERASE_OPCODE_MICROWIRE	EEPROM erase opcode
EEPROM_ERASE_OPCODE_MICROWIRE	EEPROM erase opcode
EEPROM_ERASE256_OPCODE_SPI	EEPROM ERASE 256B
EEPROM_ERASE256_OPCODE_SPI	EEPROM ERASE 256B
EEPROM_ERASE4K_OPCODE_SPI	EEPROM ERASE 4KB
EEPROM_ERASE4K_OPCODE_SPI	EEPROM ERASE 4KB
EEPROM_ERASE64K_OPCODE_SPI	EEPROM ERASE 64KB
EEPROM_ERASE64K_OPCODE_SPI	EEPROM ERASE 64KB
EEPROM_EWDS_OPCODE_MICROWIRE	EEPROM erast/write disable
EEPROM_EWDS_OPCODE_MICROWIRE	EEPROM erast/write disable
EEPROM_EWEN_OPCODE_MICROWIRE	EEPROM erase/write enable
EEPROM_EWEN_OPCODE_MICROWIRE	EEPROM erase/write enable
EEPROM_FLASH_VERSION
EEPROM_FLASH_VERSION
EEPROM_ID_LED_SETTINGS
EEPROM_ID_LED_SETTINGS
EEPROM_INIT_3GIO_3
EEPROM_INIT_3GIO_3
EEPROM_INIT_CONTROL1_REG
EEPROM_INIT_CONTROL1_REG
EEPROM_INIT_CONTROL2_REG
EEPROM_INIT_CONTROL2_REG
EEPROM_INIT_CONTROL3_PORT_A
EEPROM_INIT_CONTROL3_PORT_A
EEPROM_INIT_CONTROL3_PORT_B
EEPROM_INIT_CONTROL3_PORT_B
EEPROM_MAX_RETRY_SPI	Max wait of 5ms, for RDY signal
EEPROM_MAX_RETRY_SPI	Max wait of 5ms, for RDY signal
EEPROM_MFG_ID	0x6d50
EEPROM_MFG_ID	0x6d50
EEPROM_MFG_ID	0x6d50
EEPROM_MFG_ID	0x6d50
EEPROM_NODE_ADDR_0	Word
EEPROM_NODE_ADDR_0	Word
EEPROM_NODE_ADDR_0	Word
EEPROM_NODE_ADDR_0	Word
EEPROM_NODE_ADDR_1	Word
EEPROM_NODE_ADDR_1	Word
EEPROM_NODE_ADDR_1	Word
EEPROM_NODE_ADDR_1	Word
EEPROM_NODE_ADDR_2	Word
EEPROM_NODE_ADDR_2	Word
EEPROM_NODE_ADDR_2	Word
EEPROM_NODE_ADDR_2	Word
EEPROM_NODE_ADDRESS_BYTE_0
EEPROM_NODE_ADDRESS_BYTE_0
EEPROM_OEM_ADDR_0	Word
EEPROM_OEM_ADDR_0	Word
EEPROM_OEM_ADDR_1	Word
EEPROM_OEM_ADDR_1	Word
EEPROM_OEM_ADDR_2	Word
EEPROM_OEM_ADDR_2	Word
EEPROM_OK
EEPROM_OK
EEPROM_PBA_BYTE_1
EEPROM_PBA_BYTE_1
EEPROM_PHY_CLASS_A
EEPROM_PHY_CLASS_A
EEPROM_PHY_CLASS_WORD
EEPROM_PHY_CLASS_WORD
EEPROM_PRESENT
EEPROM_PRESENT
EEPROM_PROD_ID	0x9[0-f]50
EEPROM_PROD_ID	0x9[0-f]50
EEPROM_PROD_ID	0x9[0-f]50
EEPROM_PROD_ID	0x9[0-f]50
EEPROM_RDSR_OPCODE_SPI	EEPROM read Status register
EEPROM_RDSR_OPCODE_SPI	EEPROM read Status register
eeprom_rdy	3Com 595 - specific routines
eeprom_rdy	3Com 509 - specific routines
eeprom_rdy	3Com 595 - specific routines
eeprom_rdy	3Com 509 - specific routines
eeprom_read
eeprom_read
eeprom_read
eeprom_read
EEPROM_READ_CMD
EEPROM_READ_CMD
EEPROM_READ_OPCODE_MICROWIRE	EEPROM read opcode
EEPROM_READ_OPCODE_MICROWIRE	EEPROM read opcode
EEPROM_READ_OPCODE_SPI	EEPROM read opcode
EEPROM_READ_OPCODE_SPI	EEPROM read opcode
EEPROM_REG_10
EEPROM_REG_10
EEPROM_REG_PRO
EEPROM_REG_PRO
EEPROM_RESERVED_WORD
EEPROM_RESERVED_WORD
EEPROM_RESOURCE_CFG	IRQ. Bits 12-15
EEPROM_RESOURCE_CFG	IRQ. Bits 12-15
EEPROM_RESOURCE_CFG	IRQ. Bits 12-15
EEPROM_RESOURCE_CFG	IRQ. Bits 12-15
EEPROM_SA_OFFSET
EEPROM_SA_OFFSET
EEPROM_SERDES_AMPLITUDE	For SERDES output amplitude adjustment.
EEPROM_SERDES_AMPLITUDE	For SERDES output amplitude adjustment.
EEPROM_SERDES_AMPLITUDE_MASK
EEPROM_SERDES_AMPLITUDE_MASK
EEPROM_SIZE	1 << EEPROM_ADDRLEN
EEPROM_SIZE
EEPROM_SIZE	2 << EEPROM_ADDRLEN
EEPROM_SIZE	1 << EEPROM_ADDRLEN
EEPROM_SIZE
EEPROM_SIZE	2 << EEPROM_ADDRLEN
EEPROM_SIZE_MASK
EEPROM_SIZE_MASK
EEPROM_SIZE_SHIFT
EEPROM_SIZE_SHIFT
EEPROM_SOFT_INFO_2	Software information 2
EEPROM_SOFT_INFO_2	Software information 2
EEPROM_STATUS_BP0_SPI
EEPROM_STATUS_BP0_SPI
EEPROM_STATUS_BP1_SPI
EEPROM_STATUS_BP1_SPI
EEPROM_STATUS_RDY_SPI
EEPROM_STATUS_RDY_SPI
EEPROM_STATUS_WEN_SPI
EEPROM_STATUS_WEN_SPI
EEPROM_STATUS_WPEN_SPI
EEPROM_STATUS_WPEN_SPI
EEPROM_SUM
EEPROM_SUM
EEPROM_SWDEF_PINS_CTRL_PORT_0
EEPROM_SWDEF_PINS_CTRL_PORT_0
EEPROM_SWDEF_PINS_CTRL_PORT_1
EEPROM_SWDEF_PINS_CTRL_PORT_1
EEPROM_TIMEOUT
EEPROM_TIMEOUT
EEPROM_TST_MODE
EEPROM_TST_MODE
EEPROM_VERSION
EEPROM_VERSION
EEPROM_WORD_SIZE_SHIFT
EEPROM_WORD_SIZE_SHIFT
EEPROM_WORD0A_66MHZ
EEPROM_WORD0A_66MHZ
EEPROM_WORD0A_FD
EEPROM_WORD0A_FD
EEPROM_WORD0A_ILOS
EEPROM_WORD0A_ILOS
EEPROM_WORD0A_LRST
EEPROM_WORD0A_LRST
EEPROM_WORD0A_SWDPIO
EEPROM_WORD0A_SWDPIO
EEPROM_WORD0F_ANE
EEPROM_WORD0F_ANE
EEPROM_WORD0F_ASM_DIR
EEPROM_WORD0F_ASM_DIR
EEPROM_WORD0F_LPLU
EEPROM_WORD0F_LPLU
EEPROM_WORD0F_PAUSE
EEPROM_WORD0F_PAUSE
EEPROM_WORD0F_PAUSE_MASK
EEPROM_WORD0F_PAUSE_MASK
EEPROM_WORD0F_SWPDIO_EXT
EEPROM_WORD0F_SWPDIO_EXT
EEPROM_WORD1020_GIGA_DISABLE
EEPROM_WORD1020_GIGA_DISABLE
EEPROM_WORD1020_GIGA_DISABLE_NO
EEPROM_WORD1020_GIGA_DISABLE_NO
EEPROM_WORD1A_ASPM_MASK
EEPROM_WORD1A_ASPM_MASK
EEPROM_WRDI_OPCODE_SPI	EEPROM reset Write Enable latch
EEPROM_WRDI_OPCODE_SPI	EEPROM reset Write Enable latch
EEPROM_WREN_OPCODE_SPI	EEPROM set Write Enable latch
EEPROM_WREN_OPCODE_SPI	EEPROM set Write Enable latch
EEPROM_WRITE_CMD
EEPROM_WRITE_CMD
EEPROM_WRITE_DIS
EEPROM_WRITE_DIS
EEPROM_WRITE_EN
EEPROM_WRITE_EN
EEPROM_WRITE_OPCODE_MICROWIRE	EEPROM write opcode
EEPROM_WRITE_OPCODE_MICROWIRE	EEPROM write opcode
EEPROM_WRITE_OPCODE_SPI	EEPROM write opcode
EEPROM_WRITE_OPCODE_SPI	EEPROM write opcode
EEPROM_WRSR_OPCODE_SPI	EEPROM write Status register
EEPROM_WRSR_OPCODE_SPI	EEPROM write Status register
EEPROMSIZE
EEPROMSIZE
EEPROMSIZE
EEPROMSIZE
EERSV_BOOT_BEV
EERSV_BOOT_BEV
EERSV_BOOT_INT18
EERSV_BOOT_INT18
EERSV_BOOT_INT19
EERSV_BOOT_INT19
EERSV_BOOT_LOCAL
EERSV_BOOT_LOCAL
EERSV_BOOT_MASK
EERSV_BOOT_MASK
EERSV_BOOT_RPL	Boot method selection for VT6110
EERSV_BOOT_RPL	Boot method selection for VT6110
EESK
EESK
EEVER_NUMBER
EEVER_NUMBER
EEXIST
efab_alloc_resources
efab_alloc_resources
efab_board_operations
efab_board_operations
efab_board_type
efab_board_type
EFAB_BUF_ALIGN
EFAB_BUF_ALIGN
EFAB_BYTE
EFAB_BYTE
efab_close
efab_close
EFAB_DMA_MASK(mask)
EFAB_DMA_MASK(mask)
EFAB_DMA_MAX_MASK
EFAB_DMA_MAX_MASK
EFAB_DMA_TYPE_WIDTH( width )
EFAB_DMA_TYPE_WIDTH( width )
EFAB_DUMMY_FIELD_LBN
EFAB_DUMMY_FIELD_LBN
EFAB_DUMMY_FIELD_WIDTH
EFAB_DUMMY_FIELD_WIDTH
efab_dword
efab_dword
EFAB_DWORD_0_LBN
EFAB_DWORD_0_LBN
EFAB_DWORD_0_WIDTH
EFAB_DWORD_0_WIDTH
EFAB_DWORD_1_LBN
EFAB_DWORD_1_LBN
EFAB_DWORD_1_WIDTH
EFAB_DWORD_1_WIDTH
EFAB_DWORD_2_LBN
EFAB_DWORD_2_LBN
EFAB_DWORD_2_WIDTH
EFAB_DWORD_2_WIDTH
EFAB_DWORD_3_LBN
EFAB_DWORD_3_LBN
EFAB_DWORD_3_WIDTH
EFAB_DWORD_3_WIDTH
EFAB_DWORD_FIELD( dword, field )
EFAB_DWORD_FIELD( dword, field )
EFAB_DWORD_FMT
EFAB_DWORD_FMT
EFAB_DWORD_IS_ALL_ONES( dword )
EFAB_DWORD_IS_ALL_ONES( dword )
EFAB_DWORD_IS_ZERO( dword )
EFAB_DWORD_IS_ZERO( dword )
EFAB_DWORD_VAL(dword)
EFAB_DWORD_VAL(dword)
EFAB_ERR(...)
EFAB_ERR(...)
efab_ev_queue
efab_ev_queue
EFAB_EVQ_SIZE
EFAB_EVQ_SIZE
EFAB_EXTRACT_DWORD( dword, low, high )
EFAB_EXTRACT_DWORD( dword, low, high )
EFAB_EXTRACT_NATIVE( native_element, min ,max ,low ,high )
EFAB_EXTRACT_NATIVE( native_element, min ,max ,low ,high )
EFAB_EXTRACT_OWORD32( oword, low, high )
EFAB_EXTRACT_OWORD32( oword, low, high )
EFAB_EXTRACT_OWORD64( oword, low, high )
EFAB_EXTRACT_OWORD64( oword, low, high )
EFAB_EXTRACT_QWORD32( qword, low, high )
EFAB_EXTRACT_QWORD32( qword, low, high )
EFAB_EXTRACT_QWORD64( qword, low, high )
EFAB_EXTRACT_QWORD64( qword, low, high )
EFAB_EXTRACT32( element, min, max, low, high )
EFAB_EXTRACT32( element, min, max, low, high )
EFAB_EXTRACT64( element, min, max, low, high )
EFAB_EXTRACT64( element, min, max, low, high )
efab_fill_rx_queue	Software receive interface
efab_fill_rx_queue	Software receive interface
efab_free_resources	Software open/close
efab_free_resources	Software open/close
EFAB_HIGH_BIT(field)
EFAB_HIGH_BIT(field)
efab_init_mac
efab_init_mac
EFAB_INPLACE_MASK32( min, max, field )
EFAB_INPLACE_MASK32( min, max, field )
EFAB_INPLACE_MASK64( min, max, field )
EFAB_INPLACE_MASK64( min, max, field )
EFAB_INSERT_FIELD_NATIVE( min, max, field, value )
EFAB_INSERT_FIELD_NATIVE( min, max, field, value )
EFAB_INSERT_FIELD32( ... )
EFAB_INSERT_FIELD32( ... )
EFAB_INSERT_FIELD64( ... )
EFAB_INSERT_FIELD64( ... )
EFAB_INSERT_FIELDS_NATIVE( min, max, \ field1, value1, \ field2, value2, \ field3, value3, \ field4, value4, \ field
EFAB_INSERT_FIELDS_NATIVE( min, max, \ field1, value1, \ field2, value2, \ field3, value3, \ field4, value4, \ field
EFAB_INSERT_FIELDS32( ... )
EFAB_INSERT_FIELDS32( ... )
EFAB_INSERT_FIELDS64( ... )
EFAB_INSERT_FIELDS64( ... )
EFAB_INSERT_NATIVE( min, max, low, high, value )
EFAB_INSERT_NATIVE( min, max, low, high, value )
EFAB_INSERT_NATIVE32( min, max, low, high, value )
EFAB_INSERT_NATIVE32( min, max, low, high, value )
EFAB_INSERT_NATIVE64( min, max, low, high, value )
EFAB_INSERT_NATIVE64( min, max, low, high, value )
efab_irq
efab_irq
EFAB_LOG(...)
EFAB_LOG(...)
EFAB_LOW_BIT( field )
EFAB_LOW_BIT( field )
efab_mac_operations
efab_mac_operations
EFAB_MASK32( field )
EFAB_MASK32( field )
EFAB_MASK64( field )
EFAB_MASK64( field )
EFAB_MAX_FRAME_LEN(mtu)	FCS
EFAB_MAX_FRAME_LEN(mtu)	FCS
efab_nic
efab_nic
EFAB_NUM_RX_DESC
EFAB_NUM_RX_DESC
efab_open
efab_open
efab_oword
efab_oword
EFAB_OWORD_FIELD
EFAB_OWORD_FIELD
EFAB_OWORD_FIELD
EFAB_OWORD_FIELD
EFAB_OWORD_FIELD32( oword, field )
EFAB_OWORD_FIELD32( oword, field )
EFAB_OWORD_FIELD64( oword, field )
EFAB_OWORD_FIELD64( oword, field )
EFAB_OWORD_FMT
EFAB_OWORD_FMT
EFAB_OWORD_IS_ALL_ONES
EFAB_OWORD_IS_ALL_ONES
EFAB_OWORD_IS_ALL_ONES
EFAB_OWORD_IS_ALL_ONES
EFAB_OWORD_IS_ALL_ONES32( oword )
EFAB_OWORD_IS_ALL_ONES32( oword )
EFAB_OWORD_IS_ALL_ONES64( oword )
EFAB_OWORD_IS_ALL_ONES64( oword )
EFAB_OWORD_IS_ZERO
EFAB_OWORD_IS_ZERO
EFAB_OWORD_IS_ZERO
EFAB_OWORD_IS_ZERO
EFAB_OWORD_IS_ZERO32( oword )
EFAB_OWORD_IS_ZERO32( oword )
EFAB_OWORD_IS_ZERO64( oword )
EFAB_OWORD_IS_ZERO64( oword )
EFAB_OWORD_VAL(oword)
EFAB_OWORD_VAL(oword)
efab_phy_operations
efab_phy_operations
efab_poll	Software (polling) interrupt handler
efab_poll	Software (polling) interrupt handler
EFAB_POPULATE_DWORD( dword, ... )
EFAB_POPULATE_DWORD( dword, ... )
EFAB_POPULATE_DWORD_1( dword, ... )
EFAB_POPULATE_DWORD_1( dword, ... )
EFAB_POPULATE_DWORD_10
EFAB_POPULATE_DWORD_10
EFAB_POPULATE_DWORD_2( dword, ... )
EFAB_POPULATE_DWORD_2( dword, ... )
EFAB_POPULATE_DWORD_3( dword, ... )
EFAB_POPULATE_DWORD_3( dword, ... )
EFAB_POPULATE_DWORD_4( dword, ... )
EFAB_POPULATE_DWORD_4( dword, ... )
EFAB_POPULATE_DWORD_5( dword, ... )
EFAB_POPULATE_DWORD_5( dword, ... )
EFAB_POPULATE_DWORD_6( dword, ... )
EFAB_POPULATE_DWORD_6( dword, ... )
EFAB_POPULATE_DWORD_7( dword, ... )
EFAB_POPULATE_DWORD_7( dword, ... )
EFAB_POPULATE_DWORD_8( dword, ... )
EFAB_POPULATE_DWORD_8( dword, ... )
EFAB_POPULATE_DWORD_9( dword, ... )
EFAB_POPULATE_DWORD_9( dword, ... )
EFAB_POPULATE_OWORD
EFAB_POPULATE_OWORD
EFAB_POPULATE_OWORD
EFAB_POPULATE_OWORD
EFAB_POPULATE_OWORD_1( oword, ... )
EFAB_POPULATE_OWORD_1( oword, ... )
EFAB_POPULATE_OWORD_10
EFAB_POPULATE_OWORD_10
EFAB_POPULATE_OWORD_2( oword, ... )
EFAB_POPULATE_OWORD_2( oword, ... )
EFAB_POPULATE_OWORD_3( oword, ... )
EFAB_POPULATE_OWORD_3( oword, ... )
EFAB_POPULATE_OWORD_4( oword, ... )
EFAB_POPULATE_OWORD_4( oword, ... )
EFAB_POPULATE_OWORD_5( oword, ... )
EFAB_POPULATE_OWORD_5( oword, ... )
EFAB_POPULATE_OWORD_6( oword, ... )
EFAB_POPULATE_OWORD_6( oword, ... )
EFAB_POPULATE_OWORD_7( oword, ... )
EFAB_POPULATE_OWORD_7( oword, ... )
EFAB_POPULATE_OWORD_8( oword, ... )
EFAB_POPULATE_OWORD_8( oword, ... )
EFAB_POPULATE_OWORD_9( oword, ... )
EFAB_POPULATE_OWORD_9( oword, ... )
EFAB_POPULATE_OWORD32( oword, ... )
EFAB_POPULATE_OWORD32( oword, ... )
EFAB_POPULATE_OWORD64( oword, ... )
EFAB_POPULATE_OWORD64( oword, ... )
EFAB_POPULATE_QWORD
EFAB_POPULATE_QWORD
EFAB_POPULATE_QWORD
EFAB_POPULATE_QWORD
EFAB_POPULATE_QWORD_1( qword, ... )
EFAB_POPULATE_QWORD_1( qword, ... )
EFAB_POPULATE_QWORD_10
EFAB_POPULATE_QWORD_10
EFAB_POPULATE_QWORD_2( qword, ... )
EFAB_POPULATE_QWORD_2( qword, ... )
EFAB_POPULATE_QWORD_3( qword, ... )
EFAB_POPULATE_QWORD_3( qword, ... )
EFAB_POPULATE_QWORD_4( qword, ... )
EFAB_POPULATE_QWORD_4( qword, ... )
EFAB_POPULATE_QWORD_5( qword, ... )
EFAB_POPULATE_QWORD_5( qword, ... )
EFAB_POPULATE_QWORD_6( qword, ... )
EFAB_POPULATE_QWORD_6( qword, ... )
EFAB_POPULATE_QWORD_7( qword, ... )
EFAB_POPULATE_QWORD_7( qword, ... )
EFAB_POPULATE_QWORD_8( qword, ... )
EFAB_POPULATE_QWORD_8( qword, ... )
EFAB_POPULATE_QWORD_9( qword, ... )
EFAB_POPULATE_QWORD_9( qword, ... )
EFAB_POPULATE_QWORD32( qword, ... )
EFAB_POPULATE_QWORD32( qword, ... )
EFAB_POPULATE_QWORD64( qword, ... )
EFAB_POPULATE_QWORD64( qword, ... )
efab_probe
efab_probe
efab_qword
efab_qword
EFAB_QWORD_FIELD
EFAB_QWORD_FIELD
EFAB_QWORD_FIELD
EFAB_QWORD_FIELD
EFAB_QWORD_FIELD32( qword, field )
EFAB_QWORD_FIELD32( qword, field )
EFAB_QWORD_FIELD64( qword, field )
EFAB_QWORD_FIELD64( qword, field )
EFAB_QWORD_FMT
EFAB_QWORD_FMT
EFAB_QWORD_IS_ALL_ONES
EFAB_QWORD_IS_ALL_ONES
EFAB_QWORD_IS_ALL_ONES
EFAB_QWORD_IS_ALL_ONES
EFAB_QWORD_IS_ALL_ONES32( qword )
EFAB_QWORD_IS_ALL_ONES32( qword )
EFAB_QWORD_IS_ALL_ONES64( qword )
EFAB_QWORD_IS_ALL_ONES64( qword )
EFAB_QWORD_IS_ZERO
EFAB_QWORD_IS_ZERO
EFAB_QWORD_IS_ZERO
EFAB_QWORD_IS_ZERO
EFAB_QWORD_IS_ZERO32( qword )
EFAB_QWORD_IS_ZERO32( qword )
EFAB_QWORD_IS_ZERO64( qword )
EFAB_QWORD_IS_ZERO64( qword )
EFAB_QWORD_VAL(qword)
EFAB_QWORD_VAL(qword)
efab_receive
efab_receive
EFAB_REGDUMP(...)
EFAB_REGDUMP(...)
efab_remove
efab_remove
EFAB_RX_BUF_SIZE
EFAB_RX_BUF_SIZE
efab_rx_queue
efab_rx_queue
EFAB_RXD_SIZE
EFAB_RXD_SIZE
EFAB_SET_DWORD( dword )
EFAB_SET_DWORD( dword )
EFAB_SET_DWORD_FIELD( dword, field, value )
EFAB_SET_DWORD_FIELD( dword, field, value )
EFAB_SET_OWORD( oword )
EFAB_SET_OWORD( oword )
EFAB_SET_OWORD_FIELD
EFAB_SET_OWORD_FIELD
EFAB_SET_OWORD_FIELD
EFAB_SET_OWORD_FIELD
EFAB_SET_OWORD_FIELD_VER(efab, reg, field, val)
EFAB_SET_OWORD_FIELD_VER(efab, reg, field, val)
EFAB_SET_OWORD_FIELD32( oword, field, value )
EFAB_SET_OWORD_FIELD32( oword, field, value )
EFAB_SET_OWORD_FIELD64( oword, field, value )
EFAB_SET_OWORD_FIELD64( oword, field, value )
EFAB_SET_QWORD( qword )
EFAB_SET_QWORD( qword )
EFAB_SET_QWORD_FIELD
EFAB_SET_QWORD_FIELD
EFAB_SET_QWORD_FIELD
EFAB_SET_QWORD_FIELD
EFAB_SET_QWORD_FIELD32( qword, field, value )
EFAB_SET_QWORD_FIELD32( qword, field, value )
EFAB_SET_QWORD_FIELD64( qword, field, value )
EFAB_SET_QWORD_FIELD64( qword, field, value )
efab_special_buffer
efab_special_buffer
EFAB_TRACE(...)
EFAB_TRACE(...)
efab_transmit	Software transmit interface
efab_transmit	Software transmit interface
efab_transmit_done
efab_transmit_done
efab_tx_queue
efab_tx_queue
EFAB_TXD_SIZE
EFAB_TXD_SIZE
EFAB_VAL(field,attribute)
EFAB_VAL(field,attribute)
EFAB_WIDTH( field )
EFAB_WIDTH( field )
EFAB_ZERO_DWORD( dword )
EFAB_ZERO_DWORD( dword )
EFAB_ZERO_OWORD( oword )
EFAB_ZERO_OWORD( oword )
EFAB_ZERO_QWORD( qword )
EFAB_ZERO_QWORD( qword )
EFAULT
EFBIG
efi.h
efi.h
efi.h
EFI_1_02_SYSTEM_TABLE_REVISION
EFI_1_10_SYSTEM_TABLE_REVISION
EFI_2_00_SYSTEM_TABLE_REVISION
EFI_2_10_SYSTEM_TABLE_REVISION
EFI_ABORTED
EFI_ACCESS_DENIED
EFI_AFFECTED_BY_CAPS_LOCK
EFI_AFFECTED_BY_NUM_LOCK
EFI_AFFECTED_BY_STANDARD_SHIFT
EFI_ALLOCATE_TYPE
EFI_ALREADY_STARTED
EFI_ALT_GR_MODIFIER
EFI_AUTH_STATUS_ALL
EFI_AUTH_STATUS_IMAGE_SIGNED
EFI_AUTH_STATUS_NOT_TESTED
EFI_AUTH_STATUS_PLATFORM_OVERRI
EFI_AUTH_STATUS_TEST_FAILED
EFI_BACKGROUND_BLACK
EFI_BACKGROUND_BLUE
EFI_BACKGROUND_BROWN
EFI_BACKGROUND_CYAN
EFI_BACKGROUND_GREEN
EFI_BACKGROUND_LIGHTGRAY
EFI_BACKGROUND_MAGENTA
EFI_BACKGROUND_RED
EFI_BAD_BUFFER_SIZE
EFI_BLACK
EFI_BLUE
EFI_BOOT_OPTION_SUPPORT_APP
EFI_BOOT_OPTION_SUPPORT_COUNT
EFI_BOOT_OPTION_SUPPORT_KEY
EFI_BOOT_SERVICES
EFI_BOOT_SERVICES_REVISION
EFI_BOOT_SERVICES_SIGNATURE
EFI_BREAK_MODIFIER
EFI_BRIGHT
EFI_BROWN
EFI_BUFFER_TOO_SMALL
EFI_CALIBRATE_DELAY_MS
EFI_CAPS_LOCK_MODIFIER
EFI_CAPSULE_BLOCK_DESCRIPTOR
EFI_CAPSULE_HEADER
EFI_CAPSULE_TABLE
EFI_CERT_TYPE_RSA2048_SHA256_GU
EFI_COMMON_SECTION_HEADER
EFI_COMPONENT_NAME2_PROTOCOL_GU
EFI_COMPRESSION_SECTION
efi_config_table
EFI_CONFIG_TABLES
EFI_CONFIGURATION_TABLE
efi_console.c
EFI_CPU_ARCH_PROTOCOL_GUID
EFI_CPU_FLUSH_TYPE
EFI_CPU_INIT_TYPE
EFI_CPU_IO_PROTOCOL_ACCESS
EFI_CPU_IO_PROTOCOL_GUID
EFI_CPU_IO_PROTOCOL_WIDTH
EFI_CRC_ERROR
efi_currticks	Get current system time in ticks
EFI_CYAN
EFI_DARKGRAY
EFI_DEBUG_CODE
EFI_DEBUG_SUPPORT_PROTOCOL_GUID
EFI_DELETE_MODIFIER
EFI_DEP_AFTER
EFI_DEP_AND
EFI_DEP_BEFORE
EFI_DEP_END
EFI_DEP_FALSE
EFI_DEP_NOT
EFI_DEP_OR
EFI_DEP_PUSH
EFI_DEP_SOR
EFI_DEP_TRUE
EFI_DEV_PATH
EFI_DEV_PATH_PTR
EFI_DEVICE_ERROR
EFI_DEVICE_PATH_PROTOCOL
EFI_DEVICE_PATH_PROTOCOL_GUID
EFI_DOWN_ARROW_MODIFIER
EFI_DRIVER_BINDING_PROTOCOL_GUI
EFI_END_MODIFIER
EFI_END_OF_FILE
EFI_END_OF_MEDIA
EFI_ERROR(A)
EFI_ERROR_CODE
EFI_ERROR_MAJOR
EFI_ERROR_MINOR
EFI_ERROR_UNCONTAINED
EFI_ERROR_UNRECOVERED
EFI_FFS_FILE_HEADER
EFI_FFS_INTEGRITY_CHECK
EFI_FIELD_OFFSET(TYPE,Field)
efi_file_align	Align section within PE file
EFI_FILE_ALIGN
EFI_FILE_DATA_VALID
EFI_FILE_DELETED
EFI_FILE_HEADER_CONSTRUCTION
EFI_FILE_HEADER_INVALID
EFI_FILE_HEADER_VALID
EFI_FILE_MARKED_FOR_UPDATE
efi_find_smbios	Find SMBIOS
efi_find_table	Look up EFI configuration table
EFI_FIRMWARE_VOLUME_EXT_ENTRY
EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE
EFI_FIRMWARE_VOLUME_EXT_HEADER
EFI_FIRMWARE_VOLUME_HEADER
EFI_FREEFORM_SUBTYPE_GUID_SECTION
EFI_FUNCTION_KEY_EIGHT_MODIFIER
EFI_FUNCTION_KEY_ELEVEN_MODIFIE
EFI_FUNCTION_KEY_FIVE_MODIFIER
EFI_FUNCTION_KEY_FOUR_MODIFIER
EFI_FUNCTION_KEY_NINE_MODIFIER
EFI_FUNCTION_KEY_ONE_MODIFIER
EFI_FUNCTION_KEY_SEVEN_MODIFIER
EFI_FUNCTION_KEY_SIX_MODIFIER
EFI_FUNCTION_KEY_TEN_MODIFIER
EFI_FUNCTION_KEY_THREE_MODIFIER
EFI_FUNCTION_KEY_TWELVE_MODIFIE
EFI_FUNCTION_KEY_TWO_MODIFIER
EFI_FV_BLOCK_MAP_ENTRY
EFI_FV_EXT_TYPE_OEM_TYPE
EFI_FV_FILE_ATTRIB_ALIGNMENT
EFI_FV_FILE_ATTRIB_FIXED
EFI_FV_FILE_ATTRIB_MEMORY_MAPPE
EFI_FV_FILETYPE_ALL
EFI_FV_FILETYPE_APPLICATION
EFI_FV_FILETYPE_COMBINED_PEIM_D
EFI_FV_FILETYPE_DEBUG_MAX
EFI_FV_FILETYPE_DEBUG_MIN
EFI_FV_FILETYPE_DRIVER
EFI_FV_FILETYPE_DXE_CORE
EFI_FV_FILETYPE_FFS_MAX
EFI_FV_FILETYPE_FFS_MIN
EFI_FV_FILETYPE_FFS_PAD
EFI_FV_FILETYPE_FIRMWARE_VOLUME
EFI_FV_FILETYPE_FREEFORM
EFI_FV_FILETYPE_OEM_MAX
EFI_FV_FILETYPE_OEM_MIN
EFI_FV_FILETYPE_PEI_CORE
EFI_FV_FILETYPE_PEIM
EFI_FV_FILETYPE_RAW
EFI_FV_FILETYPE_SECURITY_CORE
EFI_FVB2_ALIGNMENT
EFI_FVB2_ALIGNMENT_1
EFI_FVB2_ALIGNMENT_128
EFI_FVB2_ALIGNMENT_128K
EFI_FVB2_ALIGNMENT_128M
EFI_FVB2_ALIGNMENT_16
EFI_FVB2_ALIGNMENT_16K
EFI_FVB2_ALIGNMENT_16M
EFI_FVB2_ALIGNMENT_1G
EFI_FVB2_ALIGNMENT_1K
EFI_FVB2_ALIGNMENT_1M
EFI_FVB2_ALIGNMENT_2
EFI_FVB2_ALIGNMENT_256
EFI_FVB2_ALIGNMENT_256K
EFI_FVB2_ALIGNMENT_256M
EFI_FVB2_ALIGNMENT_2G
EFI_FVB2_ALIGNMENT_2K
EFI_FVB2_ALIGNMENT_2M
EFI_FVB2_ALIGNMENT_32
EFI_FVB2_ALIGNMENT_32K
EFI_FVB2_ALIGNMENT_32M
EFI_FVB2_ALIGNMENT_4
EFI_FVB2_ALIGNMENT_4K
EFI_FVB2_ALIGNMENT_4M
EFI_FVB2_ALIGNMENT_512
EFI_FVB2_ALIGNMENT_512M
EFI_FVB2_ALIGNMENT_64
EFI_FVB2_ALIGNMENT_64K
EFI_FVB2_ALIGNMENT_64M
EFI_FVB2_ALIGNMENT_8
EFI_FVB2_ALIGNMENT_8K
EFI_FVB2_ALIGNMENT_8M
EFI_FVB2_ALIGNMNET_512K
EFI_FVB2_ERASE_POLARITY
EFI_FVB2_LOCK_CAP
EFI_FVB2_LOCK_STATUS
EFI_FVB2_MEMORY_MAPPED
EFI_FVB2_READ_DISABLED_CAP
EFI_FVB2_READ_ENABLED_CAP
EFI_FVB2_READ_LOCK_CAP
EFI_FVB2_READ_LOCK_STATUS
EFI_FVB2_READ_STATUS
EFI_FVB2_STICKY_WRITE
EFI_FVB2_WRITE_DISABLED_CAP
EFI_FVB2_WRITE_ENABLED_CAP
EFI_FVB2_WRITE_LOCK_CAP
EFI_FVB2_WRITE_LOCK_STATUS
EFI_FVB2_WRITE_STATUS
EFI_FVH_REVISION
EFI_FVH_SIGNATURE
EFI_FX_SAVE_STATE_IA32
EFI_FX_SAVE_STATE_X64
EFI_GCD_ALLOCATE_TYPE
EFI_GCD_IO_SPACE_DESCRIPTOR
EFI_GCD_IO_TYPE
EFI_GCD_MEMORY_SPACE_DESCRIPTOR
EFI_GCD_MEMORY_TYPE
efi_getchar	Get character from EFI console
EFI_GLYPH_HEIGHT
EFI_GLYPH_NON_SPACING
EFI_GLYPH_WIDE
EFI_GLYPH_WIDTH
EFI_GREEN
EFI_GUID_DEFINED_SECTION
EFI_GUIDED_SECTION_AUTH_STATUS_
EFI_GUIDED_SECTION_PROCESSING_R
efi_handle_cup	Handle ANSI CUP (cursor position)
efi_handle_ed	Handle ANSI ED (erase in page)
efi_handle_sgr	Handle ANSI SGR (set graphics rendition)
EFI_HII_DATE
EFI_HII_DEFAULT_CLASS_FIRMWARE_
EFI_HII_DEFAULT_CLASS_FIRMWARE_
EFI_HII_DEFAULT_CLASS_HARDWARE_
EFI_HII_DEFAULT_CLASS_HARDWARE_
EFI_HII_DEFAULT_CLASS_MANUFACTU
EFI_HII_DEFAULT_CLASS_PLATFORM_
EFI_HII_DEFAULT_CLASS_PLATFORM_
EFI_HII_DEFAULT_CLASS_SAFE
EFI_HII_DEFAULT_CLASS_STANDARD
EFI_HII_FONT_STYLE_BOLD
EFI_HII_FONT_STYLE_DBL_UNDER
EFI_HII_FONT_STYLE_EMBOSS
EFI_HII_FONT_STYLE_ITALIC
EFI_HII_FONT_STYLE_NORMAL
EFI_HII_FONT_STYLE_OUTLINE
EFI_HII_FONT_STYLE_SHADOW
EFI_HII_FONT_STYLE_UNDERLINE
EFI_HII_GIBT_DEFAULTS
EFI_HII_GIBT_DUPLICATE
EFI_HII_GIBT_END
EFI_HII_GIBT_EXT1
EFI_HII_GIBT_EXT2
EFI_HII_GIBT_EXT4
EFI_HII_GIBT_GLYPH
EFI_HII_GIBT_GLYPH_DEFAULT
EFI_HII_GIBT_GLYPHS
EFI_HII_GIBT_GLYPHS_DEFAULT
EFI_HII_GIBT_SKIP1
EFI_HII_GIBT_SKIP2
EFI_HII_IIBT_DUPLICATE
EFI_HII_IIBT_END
EFI_HII_IIBT_EXT1
EFI_HII_IIBT_EXT2
EFI_HII_IIBT_EXT4
EFI_HII_IIBT_IMAGE_1BIT
EFI_HII_IIBT_IMAGE_1BIT_TRANS
EFI_HII_IIBT_IMAGE_24BIT
EFI_HII_IIBT_IMAGE_24BIT_TRANS
EFI_HII_IIBT_IMAGE_4BIT
EFI_HII_IIBT_IMAGE_4BIT_TRANS
EFI_HII_IIBT_IMAGE_8BIT
EFI_HII_IIBT_IMAGE_8BIT_TRANS
EFI_HII_IIBT_IMAGE_JPEG
EFI_HII_IIBT_SKIP1
EFI_HII_IIBT_SKIP2
EFI_HII_KEYBOARD_LAYOUT
EFI_HII_KEYBOARD_PACKAGE_HDR
EFI_HII_PACKAGE_DEVICE_PATH
EFI_HII_PACKAGE_END
EFI_HII_PACKAGE_FONTS
EFI_HII_PACKAGE_FORMS
EFI_HII_PACKAGE_HEADER
EFI_HII_PACKAGE_IMAGES
EFI_HII_PACKAGE_KEYBOARD_LAYOUT
EFI_HII_PACKAGE_LIST_HEADER
EFI_HII_PACKAGE_SIMPLE_FONTS
EFI_HII_PACKAGE_STRINGS
EFI_HII_PACKAGE_TYPE_ALL
EFI_HII_PACKAGE_TYPE_GUID
EFI_HII_PACKAGE_TYPE_SYSTEM_BEG
EFI_HII_PACKAGE_TYPE_SYSTEM_END
EFI_HII_SIBT_DUPLICATE
EFI_HII_SIBT_END
EFI_HII_SIBT_EXT1
EFI_HII_SIBT_EXT2
EFI_HII_SIBT_EXT4
EFI_HII_SIBT_FONT
EFI_HII_SIBT_SKIP1
EFI_HII_SIBT_SKIP2
EFI_HII_SIBT_STRING_SCSU
EFI_HII_SIBT_STRING_SCSU_FONT
EFI_HII_SIBT_STRING_UCS2
EFI_HII_SIBT_STRING_UCS2_FONT
EFI_HII_SIBT_STRINGS_SCSU
EFI_HII_SIBT_STRINGS_SCSU_FONT
EFI_HII_SIBT_STRINGS_UCS2
EFI_HII_SIBT_STRINGS_UCS2_FONT
EFI_HII_STRING_BLOCK
EFI_HII_TIME
EFI_HOB_CPU
EFI_HOB_FIRMWARE_VOLUME
EFI_HOB_FIRMWARE_VOLUME2
EFI_HOB_GENERIC_HEADER
EFI_HOB_GUID_TYPE
EFI_HOB_HANDOFF_INFO_TABLE
EFI_HOB_HANDOFF_TABLE_VERSION
EFI_HOB_MEMORY_ALLOCATION
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE
EFI_HOB_MEMORY_ALLOCATION_HEADER
EFI_HOB_MEMORY_ALLOCATION_MODULE
EFI_HOB_MEMORY_ALLOCATION_STACK
EFI_HOB_MEMORY_POOL
EFI_HOB_RESOURCE_DESCRIPTOR
EFI_HOB_TYPE_CPU
EFI_HOB_TYPE_END_OF_HOB_LIST
EFI_HOB_TYPE_FV
EFI_HOB_TYPE_FV2
EFI_HOB_TYPE_GUID_EXTENSION
EFI_HOB_TYPE_HANDOFF
EFI_HOB_TYPE_LOAD_PEIM
EFI_HOB_TYPE_MEMORY_ALLOCATION
EFI_HOB_TYPE_MEMORY_POOL
EFI_HOB_TYPE_RESOURCE_DESCRIPTO
EFI_HOB_TYPE_UNUSED
EFI_HOME_MODIFIER
EFI_ICMP_ERROR
EFI_IFR_ACTION_OP
EFI_IFR_ADD_OP
EFI_IFR_AND_OP
EFI_IFR_BITWISE_AND_OP
EFI_IFR_BITWISE_NOT_OP
EFI_IFR_BITWISE_OR_OP
EFI_IFR_CATENATE_OP
EFI_IFR_CHECKBOX_DEFAULT
EFI_IFR_CHECKBOX_DEFAULT_MFG
EFI_IFR_CHECKBOX_OP
EFI_IFR_CONDITIONAL_OP
EFI_IFR_DATE_OP
EFI_IFR_DEFAULT_OP
EFI_IFR_DEFAULTSTORE_OP
EFI_IFR_DISABLE_IF_OP
EFI_IFR_DISPLAY
EFI_IFR_DISPLAY_INT_DEC
EFI_IFR_DISPLAY_UINT_DEC
EFI_IFR_DISPLAY_UINT_HEX
EFI_IFR_DIVIDE_OP
EFI_IFR_DUP_OP
EFI_IFR_END_OP
EFI_IFR_EQ_ID_ID_OP
EFI_IFR_EQ_ID_LIST_OP
EFI_IFR_EQ_ID_VAL_OP
EFI_IFR_EQUAL_OP
EFI_IFR_FALSE_OP
EFI_IFR_FF_CASE_INSENSITIVE
EFI_IFR_FF_CASE_SENSITIVE
EFI_IFR_FIND_OP
EFI_IFR_FLAG_CALLBACK
EFI_IFR_FLAG_OPTIONS_ONLY
EFI_IFR_FLAG_READ_ONLY
EFI_IFR_FLAG_RESET_REQUIRED
EFI_IFR_FLAGS_FIRST_MATCHING
EFI_IFR_FLAGS_FIRST_NON_MATCHIN
EFI_IFR_FLAGS_HORIZONTAL
EFI_IFR_FORM_OP
EFI_IFR_FORM_SET_OP
EFI_IFR_GRAY_OUT_IF_OP
EFI_IFR_GREATER_EQUAL_OP
EFI_IFR_GREATER_THAN_OP
EFI_IFR_GUID_OP
EFI_IFR_IMAGE_OP
EFI_IFR_INCONSISTENT_IF_OP
EFI_IFR_LENGTH_OP
EFI_IFR_LESS_EQUAL_OP
EFI_IFR_LESS_THAN_OP
EFI_IFR_LOCKED_OP
EFI_IFR_MATCH_OP
EFI_IFR_MID_OP
EFI_IFR_MODULO_OP
EFI_IFR_MULTIPLY_OP
EFI_IFR_NO_EMPTY_SET
EFI_IFR_NO_SUBMIT_IF_OP
EFI_IFR_NOT_EQUAL_OP
EFI_IFR_NOT_OP
EFI_IFR_NUMERIC_OP
EFI_IFR_NUMERIC_SIZE
EFI_IFR_NUMERIC_SIZE_1
EFI_IFR_NUMERIC_SIZE_2
EFI_IFR_NUMERIC_SIZE_4
EFI_IFR_NUMERIC_SIZE_8
EFI_IFR_ONE_OF_OP
EFI_IFR_ONE_OF_OPTION_OP
EFI_IFR_ONE_OP
EFI_IFR_ONES_OP
EFI_IFR_OPTION_DEFAULT
EFI_IFR_OPTION_DEFAULT_MFG
EFI_IFR_OR_OP
EFI_IFR_ORDERED_LIST_OP
EFI_IFR_PASSWORD_OP
EFI_IFR_QUESTION_REF1_OP
EFI_IFR_QUESTION_REF2_OP
EFI_IFR_QUESTION_REF3_OP
EFI_IFR_REF_OP
EFI_IFR_REFRESH_OP
EFI_IFR_RESET_BUTTON_OP
EFI_IFR_RULE_OP
EFI_IFR_RULE_REF_OP
EFI_IFR_SHIFT_LEFT_OP
EFI_IFR_SHIFT_RIGHT_OP
EFI_IFR_SPAN_OP
EFI_IFR_STRING_ASCII
EFI_IFR_STRING_LOWERCASE_HEX
EFI_IFR_STRING_MULTI_LINE
EFI_IFR_STRING_OP
EFI_IFR_STRING_REF1_OP
EFI_IFR_STRING_REF2_OP
EFI_IFR_STRING_SIGNED_DEC
EFI_IFR_STRING_UNICODE
EFI_IFR_STRING_UNSIGNED_DEC
EFI_IFR_STRING_UPPERCASE_HEX
EFI_IFR_SUBTITLE_OP
EFI_IFR_SUBTRACT_OP
EFI_IFR_SUPPRESS_IF_OP
EFI_IFR_TEXT_OP
EFI_IFR_THIS_OP
EFI_IFR_TIME_OP
EFI_IFR_TO_BOOLEAN_OP
EFI_IFR_TO_LOWER_OP
EFI_IFR_TO_STRING_OP
EFI_IFR_TO_UINT_OP
EFI_IFR_TO_UPPER_OP
EFI_IFR_TOKEN_OP
EFI_IFR_TRUE_OP
EFI_IFR_TYPE_BOOLEAN
EFI_IFR_TYPE_DATE
EFI_IFR_TYPE_NUM_SIZE_16
EFI_IFR_TYPE_NUM_SIZE_32
EFI_IFR_TYPE_NUM_SIZE_64
EFI_IFR_TYPE_NUM_SIZE_8
EFI_IFR_TYPE_OTHER
EFI_IFR_TYPE_STRING
EFI_IFR_TYPE_TIME
EFI_IFR_TYPE_VALUE
EFI_IFR_UINT16_OP
EFI_IFR_UINT32_OP
EFI_IFR_UINT64_OP
EFI_IFR_UINT8_OP
EFI_IFR_UNDEFINED_OP
EFI_IFR_UNIQUE_SET
EFI_IFR_VALUE_OP
EFI_IFR_VARSTORE_DEVICE_OP
EFI_IFR_VARSTORE_EFI_OP
EFI_IFR_VARSTORE_NAME_VALUE_OP
EFI_IFR_VARSTORE_OP
EFI_IFR_VERSION_OP
EFI_IFR_ZERO_OP
efi_image.c
EFI_IMAGE_ARCHIVE_END
EFI_IMAGE_ARCHIVE_LINKER_MEMBER
EFI_IMAGE_ARCHIVE_LONGNAMES_MEM
EFI_IMAGE_ARCHIVE_MEMBER_HEADER
EFI_IMAGE_ARCHIVE_PAD
EFI_IMAGE_ARCHIVE_START
EFI_IMAGE_ARCHIVE_START_SIZE
EFI_IMAGE_BASE_RELOCATION
EFI_IMAGE_COMDAT_SELECT_ANY
EFI_IMAGE_COMDAT_SELECT_ASSOCIA
EFI_IMAGE_COMDAT_SELECT_EXACT_M
EFI_IMAGE_COMDAT_SELECT_NODUPLI
EFI_IMAGE_COMDAT_SELECT_SAME_SI
EFI_IMAGE_DATA_DIRECTORY
EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY
EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY
EFI_IMAGE_DEBUG_DIRECTORY_ENTRY
EFI_IMAGE_DEBUG_TYPE_CODEVIEW	< The Visual C++ debug information
EFI_IMAGE_DIRECTORY_ENTRY_BASER
EFI_IMAGE_DIRECTORY_ENTRY_COPYR
EFI_IMAGE_DIRECTORY_ENTRY_DEBUG
EFI_IMAGE_DIRECTORY_ENTRY_EXCEP
EFI_IMAGE_DIRECTORY_ENTRY_EXPOR
EFI_IMAGE_DIRECTORY_ENTRY_GLOBA
EFI_IMAGE_DIRECTORY_ENTRY_IMPOR
EFI_IMAGE_DIRECTORY_ENTRY_LOAD_
EFI_IMAGE_DIRECTORY_ENTRY_RESOU
EFI_IMAGE_DIRECTORY_ENTRY_SECUR
EFI_IMAGE_DIRECTORY_ENTRY_TLS
EFI_IMAGE_DOS_HEADER
EFI_IMAGE_DOS_SIGNATURE
efi_image_exec	Execute EFI image
EFI_IMAGE_EXPORT_DIRECTORY
EFI_IMAGE_FILE_32BIT_MACHINE	< 0x0100 32 bit word machine.
EFI_IMAGE_FILE_BYTES_REVERSED_H	< 0x8000 Bytes of machine word are reversed.
EFI_IMAGE_FILE_BYTES_REVERSED_L	< 0x0080 Bytes of machine word are reversed.
EFI_IMAGE_FILE_DEBUG_STRIPPED	< 0x0200 Debugging info stripped from file in .DBG file
EFI_IMAGE_FILE_DLL	< 0x2000 File is a DLL.
EFI_IMAGE_FILE_EXECUTABLE_IMAGE	< 0x0002 File is executable (i.e. no unresolved externel references).
EFI_IMAGE_FILE_HEADER
EFI_IMAGE_FILE_LINE_NUMS_STRIPP	< 0x0004 Line nunbers stripped from file.
EFI_IMAGE_FILE_LOCAL_SYMS_STRIP	< 0x0008 Local symbols stripped from file.
EFI_IMAGE_FILE_MACHINE_I386	< Intel 386.
EFI_IMAGE_FILE_MACHINE_POWERPC	< IBM* PowerPC Little-Endian
EFI_IMAGE_FILE_MACHINE_R3000	< MIPS* little-endian, 0540 big-endian
EFI_IMAGE_FILE_MACHINE_R4000	< MIPS* little-endian
EFI_IMAGE_FILE_MACHINE_UNKNOWN	< Any machine type
EFI_IMAGE_FILE_RELOCS_STRIPPED	< 0x0001 Relocation info stripped from file.
EFI_IMAGE_FILE_SYSTEM	< 0x1000 System File.
EFI_IMAGE_FIRST_SECTION(ntheader)
efi_image_handle
EFI_IMAGE_IMPORT_BY_NAME
EFI_IMAGE_IMPORT_DESCRIPTOR
EFI_IMAGE_LINENUMBER
efi_image_load	Load EFI image into memory
EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine)
EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine)
EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine)
EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine)
EFI_IMAGE_MACHINE_EBC
EFI_IMAGE_MACHINE_IA32
EFI_IMAGE_MACHINE_IA64
EFI_IMAGE_MACHINE_IPF
EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine)
EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine)
EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine)
EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine)
EFI_IMAGE_MACHINE_X64
EFI_IMAGE_N_BTMASK
EFI_IMAGE_N_BTSHFT
EFI_IMAGE_N_TMASK
EFI_IMAGE_N_TMASK1
EFI_IMAGE_N_TMASK2
EFI_IMAGE_N_TSHIFT
EFI_IMAGE_NT_HEADERS32
EFI_IMAGE_NT_HEADERS64
EFI_IMAGE_NT_OPTIONAL_HDR32_MAG
EFI_IMAGE_NT_OPTIONAL_HDR64_MAG
EFI_IMAGE_NT_SIGNATURE
EFI_IMAGE_NUMBER_OF_DIRECTORY_E
EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION
EFI_IMAGE_OPTIONAL_HEADER_UNION
EFI_IMAGE_OPTIONAL_HEADER32
EFI_IMAGE_OPTIONAL_HEADER64
EFI_IMAGE_ORDINAL(Ordinal)
EFI_IMAGE_ORDINAL_FLAG	< Flag for PE32
EFI_IMAGE_OS2_SIGNATURE
EFI_IMAGE_OS2_SIGNATURE_LE
EFI_IMAGE_REL_BASED_ABSOLUTE
EFI_IMAGE_REL_BASED_DIR64
EFI_IMAGE_REL_BASED_HIGH
EFI_IMAGE_REL_BASED_HIGHADJ
EFI_IMAGE_REL_BASED_HIGHLOW
EFI_IMAGE_REL_BASED_IA64_IMM64
EFI_IMAGE_REL_BASED_LOW
EFI_IMAGE_REL_BASED_MIPS_JMPADD
EFI_IMAGE_REL_I386_ABSOLUTE	< Reference is absolute, no relocation is necessary
EFI_IMAGE_REL_I386_DIR16	< Direct 16-bit reference to the symbols virtual address
EFI_IMAGE_REL_I386_DIR32	< Direct 32-bit reference to the symbols virtual address
EFI_IMAGE_REL_I386_DIR32NB	< Direct 32-bit reference to the symbols virtual address, base not included
EFI_IMAGE_REL_I386_REL16	< PC-relative 16-bit reference to the symbols virtual address
EFI_IMAGE_REL_I386_REL32	< PC-relative 32-bit reference to the symbols virtual address
EFI_IMAGE_REL_I386_SECREL
EFI_IMAGE_REL_I386_SECTION
EFI_IMAGE_REL_I386_SEG12	< Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address
EFI_IMAGE_RELOCATION
EFI_IMAGE_ROM_OPTIONAL_HDR_MAGI
EFI_IMAGE_SCN_ALIGN_16BYTES	< 0x00500000
EFI_IMAGE_SCN_ALIGN_1BYTES	< 0x00100000
EFI_IMAGE_SCN_ALIGN_2BYTES	< 0x00200000
EFI_IMAGE_SCN_ALIGN_32BYTES	< 0x00600000
EFI_IMAGE_SCN_ALIGN_4BYTES	< 0x00300000
EFI_IMAGE_SCN_ALIGN_64BYTES	< 0x00700000
EFI_IMAGE_SCN_ALIGN_8BYTES	< 0x00400000
EFI_IMAGE_SCN_CNT_CODE	< 0x00000020
EFI_IMAGE_SCN_CNT_INITIALIZED_D	< 0x00000040
EFI_IMAGE_SCN_CNT_UNINITIALIZED	< 0x00000080
EFI_IMAGE_SCN_LNK_COMDAT	< 0x00001000
EFI_IMAGE_SCN_LNK_INFO	< 0x00000200 ///< Section contains comments or some other type of information.
EFI_IMAGE_SCN_LNK_OTHER	< 0x00000100 ///< Reserved.
EFI_IMAGE_SCN_LNK_REMOVE	< 0x00000800 ///< Section contents will not become part of image.
EFI_IMAGE_SCN_MEM_DISCARDABLE	< 0x02000000
EFI_IMAGE_SCN_MEM_EXECUTE	< 0x20000000
EFI_IMAGE_SCN_MEM_NOT_CACHED	< 0x04000000
EFI_IMAGE_SCN_MEM_NOT_PAGED	< 0x08000000
EFI_IMAGE_SCN_MEM_READ	< 0x40000000
EFI_IMAGE_SCN_MEM_SHARED	< 0x10000000
EFI_IMAGE_SCN_MEM_WRITE	< 0x80000000
EFI_IMAGE_SCN_TYPE_NO_PAD	< 0x00000008 ///< Reserved.
EFI_IMAGE_SECTION_HEADER
EFI_IMAGE_SIZEOF_ARCHIVE_MEMBER
EFI_IMAGE_SIZEOF_BASE_RELOCATIO
EFI_IMAGE_SIZEOF_FILE_HEADER
EFI_IMAGE_SIZEOF_LINENUMBER
EFI_IMAGE_SIZEOF_NT_OPTIONAL32_
EFI_IMAGE_SIZEOF_NT_OPTIONAL64_
EFI_IMAGE_SIZEOF_RELOCATION
EFI_IMAGE_SIZEOF_SECTION_HEADER
EFI_IMAGE_SIZEOF_SHORT_NAME
EFI_IMAGE_SIZEOF_SYMBOL
EFI_IMAGE_SNAP_BY_ORDINAL(Ordinal)
EFI_IMAGE_SUBSYSTEM_EFI_APPLICA
EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SE
EFI_IMAGE_SUBSYSTEM_EFI_EFI_ROM
EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME
EFI_IMAGE_SUBSYSTEM_NATIVE
EFI_IMAGE_SUBSYSTEM_OS2_CUI
EFI_IMAGE_SUBSYSTEM_POSIX_CUI
EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME	< defined PI Specification, 1.0
EFI_IMAGE_SUBSYSTEM_UNKNOWN
EFI_IMAGE_SUBSYSTEM_WINDOWS_CUI
EFI_IMAGE_SUBSYSTEM_WINDOWS_GUI
EFI_IMAGE_SYM_ABSOLUTE	< Symbol is an absolute value.
EFI_IMAGE_SYM_CLASS_ARGUMENT
EFI_IMAGE_SYM_CLASS_AUTOMATIC
EFI_IMAGE_SYM_CLASS_BIT_FIELD
EFI_IMAGE_SYM_CLASS_BLOCK
EFI_IMAGE_SYM_CLASS_END_OF_FUNC
EFI_IMAGE_SYM_CLASS_END_OF_STRU
EFI_IMAGE_SYM_CLASS_ENUM_TAG
EFI_IMAGE_SYM_CLASS_EXTERNAL
EFI_IMAGE_SYM_CLASS_EXTERNAL_DE
EFI_IMAGE_SYM_CLASS_FILE
EFI_IMAGE_SYM_CLASS_FUNCTION
EFI_IMAGE_SYM_CLASS_LABEL
EFI_IMAGE_SYM_CLASS_MEMBER_OF_E
EFI_IMAGE_SYM_CLASS_MEMBER_OF_S
EFI_IMAGE_SYM_CLASS_MEMBER_OF_U
EFI_IMAGE_SYM_CLASS_NULL
EFI_IMAGE_SYM_CLASS_REGISTER
EFI_IMAGE_SYM_CLASS_REGISTER_PA
EFI_IMAGE_SYM_CLASS_SECTION
EFI_IMAGE_SYM_CLASS_STATIC
EFI_IMAGE_SYM_CLASS_STRUCT_TAG
EFI_IMAGE_SYM_CLASS_TYPE_DEFINI
EFI_IMAGE_SYM_CLASS_UNDEFINED_L
EFI_IMAGE_SYM_CLASS_UNDEFINED_S
EFI_IMAGE_SYM_CLASS_UNION_TAG
EFI_IMAGE_SYM_CLASS_WEAK_EXTERN
EFI_IMAGE_SYM_DEBUG	< Symbol is a special debug item.
EFI_IMAGE_SYM_DTYPE_ARRAY
EFI_IMAGE_SYM_DTYPE_FUNCTION
EFI_IMAGE_SYM_DTYPE_NULL	< no derived type.
EFI_IMAGE_SYM_DTYPE_POINTER
EFI_IMAGE_SYM_TYPE_BYTE
EFI_IMAGE_SYM_TYPE_CHAR	< type character.
EFI_IMAGE_SYM_TYPE_DOUBLE
EFI_IMAGE_SYM_TYPE_DWORD
EFI_IMAGE_SYM_TYPE_ENUM	< enumeration.
EFI_IMAGE_SYM_TYPE_FLOAT
EFI_IMAGE_SYM_TYPE_INT
EFI_IMAGE_SYM_TYPE_LONG
EFI_IMAGE_SYM_TYPE_MOE	< member of enumeration.
EFI_IMAGE_SYM_TYPE_NULL	< no type.
EFI_IMAGE_SYM_TYPE_SHORT	< type short integer.
EFI_IMAGE_SYM_TYPE_STRUCT
EFI_IMAGE_SYM_TYPE_UINT
EFI_IMAGE_SYM_TYPE_UNION
EFI_IMAGE_SYM_TYPE_VOID	< no valid type.
EFI_IMAGE_SYM_TYPE_WORD
EFI_IMAGE_SYM_UNDEFINED	< Symbol is undefined or is common.
EFI_IMAGE_THUNK_DATA
EFI_IMAGE_WEAK_EXTERN_SEARCH_AL
EFI_IMAGE_WEAK_EXTERN_SEARCH_LI
EFI_IMAGE_WEAK_EXTERN_SEARCH_NO
EFI_INCOMPATIBLE_VERSION
efi_init	Initialise EFI environment
efi_init.c
EFI_INPUT_KEY
EFI_INSERT_MODIFIER
EFI_INSTRUCTION_SET_ARCHITECTURE
EFI_INTERFACE_TYPE
EFI_INVALID_LANGUAGE
EFI_INVALID_PARAMETER
efi_io.c
efi_io.h
efi_iodelay	Wait for I/O-mapped operation to complete
efi_ioread	Read from device
efi_ioreads	String read from device
efi_iowrite	Write to device
efi_iowrites	String write to device
EFI_IP_ADDRESS
EFI_IPv4_ADDRESS
EFI_IPv6_ADDRESS
efi_iskey	Check for character ready to read from EFI console
EFI_KEY
EFI_KEY_CODE_COUNT
EFI_KEY_DESCRIPTOR
EFI_KEY_OPTION
EFI_KEY_OPTION_ALT
EFI_KEY_OPTION_CONTROL
EFI_KEY_OPTION_LOGO
EFI_KEY_OPTION_MENU
EFI_KEY_OPTION_SHIFT
EFI_KEY_OPTION_SYSREQ
EFI_LEFT_ALT_MODIFIER
EFI_LEFT_ARROW_MODIFIER
EFI_LEFT_CONTROL_MODIFIER
EFI_LEFT_LOGO_MODIFIER
EFI_LEFT_SHIFT_MODIFIER
EFI_LEGACY_EXPANSION_ROM_HEADER
EFI_LIGHTBLUE
EFI_LIGHTCYAN
EFI_LIGHTGRAY
EFI_LIGHTGREEN
EFI_LIGHTMAGENTA
EFI_LIGHTRED
EFI_LOAD_ERROR
EFI_LOCATE_SEARCH_TYPE
EFI_MAC_ADDRESS
EFI_MAGENTA
EFI_MAX_ADDRESS
EFI_MAX_BIT
EFI_MEDIA_CHANGED
EFI_MEMORY_DESCRIPTOR
EFI_MEMORY_DESCRIPTOR_VERSION
EFI_MEMORY_RP
EFI_MEMORY_RUNTIME
EFI_MEMORY_TYPE
EFI_MEMORY_UC
EFI_MEMORY_UCE
EFI_MEMORY_WB
EFI_MEMORY_WC
EFI_MEMORY_WP
EFI_MEMORY_WT
EFI_MEMORY_XP
EFI_MENU_MODIFIER
EFI_NARROW_GLYPH
EFI_NETWORK_INTERFACE_IDENTIFIE
EFI_NETWORK_INTERFACE_IDENTIFIE
EFI_NETWORK_INTERFACE_IDENTIFIE
EFI_NETWORK_PROTOCOL_TYPE
EFI_NETWORK_STATISTICS
EFI_NO_MAPPING
EFI_NO_MEDIA
EFI_NO_RESPONSE
EFI_NOT_AVAILABLE_YET
EFI_NOT_COMPRESSED
EFI_NOT_FOUND
EFI_NOT_READY
EFI_NOT_STARTED
EFI_NS_KEY_DEPENDENCY_MODIFIER
EFI_NS_KEY_MODIFIER
EFI_NULL_MODIFIER
EFI_NUM_LOCK_MODIFIER
EFI_OPEN_PROTOCOL_BY_CHILD_CONT
EFI_OPEN_PROTOCOL_BY_DRIVER
EFI_OPEN_PROTOCOL_BY_HANDLE_PRO
EFI_OPEN_PROTOCOL_EXCLUSIVE
EFI_OPEN_PROTOCOL_GET_PROTOCOL
EFI_OPEN_PROTOCOL_INFORMATION_ENTRY
EFI_OPEN_PROTOCOL_TEST_PROTOCOL
EFI_OPTIONAL_POINTER
EFI_OPTIONAL_PTR
EFI_OUT_OF_RESOURCES
EFI_PAGE_DOWN_MODIFIER
EFI_PAGE_MASK
EFI_PAGE_SHIFT
EFI_PAGE_SIZE
EFI_PAGE_UP_MODIFIER
EFI_PAGES_TO_SIZE(a)
EFI_PARTITION_ENTRY
EFI_PARTITION_TABLE_HEADER
EFI_PAUSE_MODIFIER
EFI_PC_ANSI_GUID
efi_pci.c
efi_pci.h
EFI_PCI_ADDRESS(bus, dev, func, reg)
EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_
EFI_PCI_ATTRIBUTE_IDE_PRIMARY_I
EFI_PCI_ATTRIBUTE_IDE_SECONDARY
EFI_PCI_ATTRIBUTE_INVALID_FOR_A
EFI_PCI_ATTRIBUTE_ISA_IO
EFI_PCI_ATTRIBUTE_ISA_MOTHERBOA
EFI_PCI_ATTRIBUTE_MEMORY_CACHED
EFI_PCI_ATTRIBUTE_MEMORY_DISABL
EFI_PCI_ATTRIBUTE_MEMORY_WRITE_
EFI_PCI_ATTRIBUTE_VALID_FOR_ALL
EFI_PCI_ATTRIBUTE_VGA_IO
EFI_PCI_ATTRIBUTE_VGA_MEMORY
EFI_PCI_ATTRIBUTE_VGA_PALETTE_I
EFI_PCI_BRIDGE_CONTROL_DISCARD_	< 0x0800
EFI_PCI_BRIDGE_CONTROL_FAST_BAC	< 0x0080
EFI_PCI_BRIDGE_CONTROL_IREQINT_	< 0x0080
EFI_PCI_BRIDGE_CONTROL_ISA	< 0x0004
EFI_PCI_BRIDGE_CONTROL_MASTER_A	< 0x0020
EFI_PCI_BRIDGE_CONTROL_PARITY_E	< 0x0001
EFI_PCI_BRIDGE_CONTROL_PRIMARY_	< 0x0100
EFI_PCI_BRIDGE_CONTROL_RANGE0_M	< 0x0100
EFI_PCI_BRIDGE_CONTROL_RANGE1_M	< 0x0200
EFI_PCI_BRIDGE_CONTROL_RESET_SE	< 0x0040
EFI_PCI_BRIDGE_CONTROL_SECONDAR	< 0x0200
EFI_PCI_BRIDGE_CONTROL_SERR	< 0x0002
EFI_PCI_BRIDGE_CONTROL_TIMER_ST	< 0x0400
EFI_PCI_BRIDGE_CONTROL_VGA	< 0x0008
EFI_PCI_BRIDGE_CONTROL_VGA_16	< 0x0010
EFI_PCI_BRIDGE_CONTROL_WRITE_PO	< 0x0400
EFI_PCI_CAPABILITY_AGP
EFI_PCI_CAPABILITY_HDR
EFI_PCI_CAPABILITY_HOTPLUG
EFI_PCI_CAPABILITY_ID_AGP
EFI_PCI_CAPABILITY_ID_HOTPLUG
EFI_PCI_CAPABILITY_ID_MSI
EFI_PCI_CAPABILITY_ID_PMI
EFI_PCI_CAPABILITY_ID_SLOTID
EFI_PCI_CAPABILITY_ID_VPD
EFI_PCI_CAPABILITY_MSI32
EFI_PCI_CAPABILITY_MSI64
EFI_PCI_CAPABILITY_PMI
EFI_PCI_CAPABILITY_SLOTID
EFI_PCI_CAPABILITY_VPD
EFI_PCI_CARDBUS_BRIDGE_CAPABILI
EFI_PCI_COMMAND_BUS_MASTER	< 0x0004
EFI_PCI_COMMAND_FAST_BACK_TO_BA	< 0x0200
EFI_PCI_COMMAND_IO_SPACE	< 0x0001
EFI_PCI_COMMAND_MEMORY_SPACE	< 0x0002
EFI_PCI_COMMAND_MEMORY_WRITE_AN	< 0x0010
EFI_PCI_COMMAND_PARITY_ERROR_RE	< 0x0040
EFI_PCI_COMMAND_SERR	< 0x0100
EFI_PCI_COMMAND_SPECIAL_CYCLE	< 0x0008
EFI_PCI_COMMAND_STEPPING_CONTRO	< 0x0080
EFI_PCI_COMMAND_VGA_PALETTE_SNO	< 0x0020
EFI_PCI_DEVICE_ENABLE
EFI_PCI_EXPANSION_ROM_HEADER
EFI_PCI_EXPANSION_ROM_HEADER_CO	<defined in UEFI spec.
EFI_PCI_EXPANSION_ROM_HEADER_EF	< defined in UEFI Spec.
EFI_PCI_FAST_BACK_TO_BACK_CAPAB	< 0x0080
EFI_PCI_IO_ATTRIBUTE_BUS_MASTER	< Enable the DMA bit in the PCI Config Header
EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRE	< Clear for PCI controllers that can not genrate a DAC
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_D	< Clear for an add-in PCI Device
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_R	< Clear for a physical PCI Option ROM accessed through ROM BAR
EFI_PCI_IO_ATTRIBUTE_IDE_PRIMAR	< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)
EFI_PCI_IO_ATTRIBUTE_IDE_SECOND	< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)
EFI_PCI_IO_ATTRIBUTE_IO	< Enable the I/O decode bit in the PCI Config Header
EFI_PCI_IO_ATTRIBUTE_ISA_IO	< I/O cycles 0x0100-0x03FF or greater (10 bit decode)
EFI_PCI_IO_ATTRIBUTE_ISA_IO_16	< I/O cycles 0x0100-0x03FF or greater (16 bit decode)
EFI_PCI_IO_ATTRIBUTE_ISA_MOTHER	< I/O cycles 0x0000-0x00FF (10 bit decode)
EFI_PCI_IO_ATTRIBUTE_MASK	< All the following I/O and Memory cycles
EFI_PCI_IO_ATTRIBUTE_MEMORY	< Enable the Memory decode bit in the PCI Config Header
EFI_PCI_IO_ATTRIBUTE_MEMORY_CAC	< Map a memory range so all r/w accesses are cached
EFI_PCI_IO_ATTRIBUTE_MEMORY_DIS	< Disable a memory range
EFI_PCI_IO_ATTRIBUTE_MEMORY_WRI	< Map a memory range so write are combined
EFI_PCI_IO_ATTRIBUTE_VGA_IO	< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)
EFI_PCI_IO_ATTRIBUTE_VGA_IO_16	< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)
EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY	< MEM cycles 0xA0000-0xBFFFF (24 bit decode)
EFI_PCI_IO_ATTRIBUTE_VGA_PALETT	< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)
EFI_PCI_IO_ATTRIBUTE_VGA_PALETT	< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)
EFI_PCI_IO_PASS_THROUGH_BAR	< Special BAR that passes a memory or I/O cycle through unchanged
EFI_PCI_IO_PROTOCOL_ACCESS
EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION
EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS
EFI_PCI_IO_PROTOCOL_GUID
EFI_PCI_IO_PROTOCOL_OPERATION
EFI_PCI_IO_PROTOCOL_WIDTH
EFI_PCI_MASTER_DATA_PARITY_ERRO	< 0x0100
EFI_PCI_ROM_HEADER
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
EFI_PCI_STATUS_66MZ_CAPABLE	< 0x0020
EFI_PCI_STATUS_CAPABILITY	< 0x0010
EFI_PEI_HOB_POINTERS
EFI_PNP_ID(_PNPId)
EFI_PRINT_MODIFIER
EFI_PROGRESS_CODE
efi_protocol
EFI_PROTOCOL_ERROR
EFI_PROTOCOLS
EFI_PTAB_HEADER_ID
efi_putchar	Print a character to EFI console
EFI_QF_DATE_DAY_SUPPRESS
EFI_QF_DATE_MONTH_SUPPRESS
EFI_QF_DATE_STORAGE
EFI_QF_DATE_YEAR_SUPPRESS
EFI_RED
EFI_REMOVABLE_MEDIA_FILE_NAME
EFI_REMOVABLE_MEDIA_FILE_NAME
EFI_REMOVABLE_MEDIA_FILE_NAME
EFI_REMOVABLE_MEDIA_FILE_NAME_I
EFI_REMOVABLE_MEDIA_FILE_NAME_I
EFI_REMOVABLE_MEDIA_FILE_NAME_X
EFI_REQUIRE_PROTOCOL( _protocol, _ptr )
EFI_RESET_TYPE
EFI_RESOURCE_ATTRIBUTE_16_BIT_I
EFI_RESOURCE_ATTRIBUTE_32_BIT_I
EFI_RESOURCE_ATTRIBUTE_64_BIT_I
EFI_RESOURCE_ATTRIBUTE_ECC_RESE
EFI_RESOURCE_ATTRIBUTE_ECC_RESE
EFI_RESOURCE_ATTRIBUTE_EXECUTIO
EFI_RESOURCE_ATTRIBUTE_INITIALI
EFI_RESOURCE_ATTRIBUTE_MULTIPLE
EFI_RESOURCE_ATTRIBUTE_PRESENT
EFI_RESOURCE_ATTRIBUTE_READ_PRO
EFI_RESOURCE_ATTRIBUTE_SINGLE_B
EFI_RESOURCE_ATTRIBUTE_TESTED
EFI_RESOURCE_ATTRIBUTE_UNCACHEA
EFI_RESOURCE_ATTRIBUTE_UNCACHED
EFI_RESOURCE_ATTRIBUTE_WRITE_BA
EFI_RESOURCE_ATTRIBUTE_WRITE_CO
EFI_RESOURCE_ATTRIBUTE_WRITE_PR
EFI_RESOURCE_ATTRIBUTE_WRITE_TH
EFI_RESOURCE_FIRMWARE_DEVICE
EFI_RESOURCE_IO
EFI_RESOURCE_IO_RESERVED
EFI_RESOURCE_MAX_MEMORY_TYPE
EFI_RESOURCE_MEMORY_MAPPED_IO
EFI_RESOURCE_MEMORY_MAPPED_IO_P
EFI_RESOURCE_MEMORY_RESERVED
EFI_RESOURCE_SYSTEM_MEMORY
EFI_RIGHT_ALT_MODIFIER
EFI_RIGHT_ARROW_MODIFIER
EFI_RIGHT_CONTROL_MODIFIER
EFI_RIGHT_LOGO_MODIFIER
EFI_RIGHT_SHIFT_MODIFIER
EFI_ROOT_BRIDGE_LIST
EFI_RUNTIME_SERVICES
EFI_RUNTIME_SERVICES_REVISION
EFI_RUNTIME_SERVICES_SIGNATURE
EFI_SAS_DEVICE_PATH_GUID
EFI_SCROLL_LOCK_MODIFIER
EFI_SECTION_ALL
EFI_SECTION_COMPATIBILITY16
EFI_SECTION_COMPRESSION
EFI_SECTION_DXE_DEPEX
EFI_SECTION_FIRMWARE_VOLUME_IMA
EFI_SECTION_FREEFORM_SUBTYPE_GU
EFI_SECTION_GUID_DEFINED
EFI_SECTION_PE32
EFI_SECTION_PEI_DEPEX
EFI_SECTION_PIC
EFI_SECTION_RAW
EFI_SECTION_TE
EFI_SECTION_USER_INTERFACE
EFI_SECTION_VERSION
EFI_SECURITY_VIOLATION
EFI_SIGNATURE_16(A, B)
EFI_SIGNATURE_32(A, B, C, D)
EFI_SIGNATURE_64(A, B, C, D, E, F, G, H)
EFI_SIMPLE_NETWORK_COMMAND_INTE
EFI_SIMPLE_NETWORK_INTERFACE_RE
EFI_SIMPLE_NETWORK_MODE
EFI_SIMPLE_NETWORK_PROTOCOL_GUI
EFI_SIMPLE_NETWORK_PROTOCOL_REV
EFI_SIMPLE_NETWORK_RECEIVE_BROA
EFI_SIMPLE_NETWORK_RECEIVE_INTE
EFI_SIMPLE_NETWORK_RECEIVE_MULT
EFI_SIMPLE_NETWORK_RECEIVE_PROM
EFI_SIMPLE_NETWORK_RECEIVE_PROM
EFI_SIMPLE_NETWORK_RECEIVE_UNIC
EFI_SIMPLE_NETWORK_SOFTWARE_INT
EFI_SIMPLE_NETWORK_STATE
EFI_SIMPLE_NETWORK_TRANSMIT_INT
EFI_SIMPLE_TEXT_INPUT_PROTOCOL_
EFI_SIMPLE_TEXT_OUTPUT_MODE
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL
EFI_SIZE_TO_PAGES(a)
efi_smbios.c
efi_smbios.h
EFI_SMBIOS_TABLE_GUID
efi_snp.c
efi_snp_device
efi_snp_driver_start	Attach driver to device
efi_snp_driver_stop	Detach driver from device
efi_snp_driver_supported	Check to see if driver supports a device
efi_snp_get_controller_name	Look up controller name
efi_snp_get_driver_name	Look up driver name
efi_snp_get_status	Read interrupt status and TX recycled buffer status
efi_snp_initialize	Open the network device
efi_snp_install	Install EFI SNP driver
efi_snp_mcast_ip_to_mac	Convert multicast IP address to MAC address
efi_snp_netdev	Locate net device corresponding to EFI device
efi_snp_nvdata	Read or write non-volatile storage
efi_snp_poll	Poll net device and count received packets
efi_snp_receive	Receive packet
efi_snp_receive_filters	Manage receive filters
efi_snp_reset	Reset the network device
efi_snp_set_mode	Set EFI SNP mode based on gPXE net device parameters
efi_snp_shutdown	Shut down the network device
efi_snp_snpdev	Locate SNP corresponding to EFI device
efi_snp_start	Change SNP state from "stopped" to "started"
efi_snp_station_address	Set station address
efi_snp_statistics	Get (or reset) statistics
efi_snp_stop	Change SNP state from "started" to "stopped"
efi_snp_transmit	Start packet transmission
efi_snp_wait_for_packet	Poll event
EFI_STANDARD_COMPRESSION
EFI_STATUS_CODE_CLASS_MASK
EFI_STATUS_CODE_DATA
EFI_STATUS_CODE_OPERATION_MASK
EFI_STATUS_CODE_RESERVED_MASK
EFI_STATUS_CODE_SEVERITY_MASK
EFI_STATUS_CODE_SUBCLASS_MASK
EFI_STATUS_CODE_TYPE_MASK
efi_strerror	@file
efi_strerror.c
EFI_SUCCESS
EFI_SYS_REQUEST_MODIFIER
efi_systab
EFI_SYSTEM_CONTEXT
EFI_SYSTEM_CONTEXT_EBC
EFI_SYSTEM_CONTEXT_IA32
EFI_SYSTEM_CONTEXT_IPF
EFI_SYSTEM_CONTEXT_X64
EFI_SYSTEM_TABLE_REVISION
EFI_SYSTEM_TABLE_SIGNATURE
EFI_TABLE_HEADER
EFI_TE_IMAGE_DIRECTORY_ENTRY_BA
EFI_TE_IMAGE_DIRECTORY_ENTRY_DE
EFI_TE_IMAGE_HEADER
EFI_TE_IMAGE_HEADER_SIGNATURE
EFI_TEXT_ATTR(f, b)
EFI_TFTP_ERROR
efi_ticks_per_sec	Get number of ticks per second
EFI_TIME
EFI_TIME_ADJUST_DAYLIGHT
EFI_TIME_CAPABILITIES
EFI_TIME_IN_DAYLIGHT
EFI_TIMEOUT
efi_timer.c
efi_timer.h
EFI_TIMER_DELAY
EFI_TIMER0_SHIFT
efi_uaccess.c
efi_uaccess.h
EFI_UART_DEVICE_PATH_GUID
efi_udelay	Delay for a fixed number of microseconds
efi_umalloc.c
efi_umalloc.h
EFI_UNSPECIFIED_TIMEZONE
EFI_UNSUPPORTED
EFI_UP_ARROW_MODIFIER
efi_urealloc	Reallocate external memory
EFI_USE_TABLE( _table, _ptr, _required )
EFI_USER_INTERFACE_SECTION
EFI_VARIABLE_AUTHENTICATED_WRIT
EFI_VARIABLE_AUTHENTICATION
EFI_VARIABLE_BOOTSERVICE_ACCESS
EFI_VARIABLE_HARDWARE_ERROR_REC
EFI_VARIABLE_NON_VOLATILE
EFI_VARIABLE_RUNTIME_ACCESS
EFI_VERSION_SECTION
EFI_VGA_DEVICE_ENABLE
EFI_VOLUME_CORRUPTED
EFI_VOLUME_FULL
EFI_VT_100_GUID
EFI_VT_100_PLUS_GUID
EFI_VT_UTF8_GUID
EFI_WARN_BUFFER_TOO_SMALL
EFI_WARN_DELETE_FAILURE
EFI_WARN_UNKNOWN_GLYPH
EFI_WARN_WRITE_FAILURE
EFI_WHITE
EFI_WIDE_ATTRIBUTE
EFI_WIDE_GLYPH
efi_width	Determine EFI CPU I/O width code
EFI_WRITE_PROTECTED
EFI_YELLOW
EFIAPI
EFIAPI
EFIAPI
EFIAPI
efidrvprefix.c
EFIERR(_a)
efipci_address
EFIPCI_LOCATION( _offset, _width )
EFIPCI_OFFSET( _location )
efipci_read
EFIPCI_WIDTH( _location )
EFIPCI_WIDTH_BYTE
EFIPCI_WIDTH_DWORD
EFIPCI_WIDTH_WORD
efipci_write
efiprefix.c
EFIRC_TO_RC( efirc )
efirom.c
efix86_cpu_nap	@file
efix86_nap.c
efix86_nap.h
EhnMIIdataShift
EhnMIIdataShift
EhnMIInotDone
EhnMIInotDone
EhnMIIpmdShift	7016 only
EhnMIIpmdShift	7016 only
EhnMIIread
EhnMIIread
EhnMIIregShift
EhnMIIregShift
EhnMIIreq
EhnMIIreq
EhnMIIwrite
EhnMIIwrite
EHOSTUNREACH
EI_CLASS	File class byte index
EI_DATA	Data encodeing byte index
EI_MAG0
EI_MAG1
EI_MAG2
EI_MAG3
EI_NIDENT	Size of e_ident array.
EI_VERSION	File version byte index
EIDRM
EILSEQ
EINPROGRESS
EINPROGRESS_JOINING
EINTR
EINVAL
EINVAL
EINVAL
EINVAL
EINVAL_ACTIVE_SCAN
EINVAL_BYTE_STRING
EINVAL_BYTE_STRING_LEN
EINVAL_CRYPTO_REQUEST
EINVAL_INTEGER
EINVAL_PKT_LLC_HEADER
EINVAL_PKT_NOT_DATA
EINVAL_PKT_NOT_FROMDS
EINVAL_PKT_TOO_SHORT
EINVAL_PKT_VERSION
EINVAL_RP_TOO_SHORT
EIO
EIO
EIO
eisa.c
eisa.c
eisa.h
EISA_APROM	Ethernet Address PROM
EISA_APROM	Ethernet Address PROM
EISA_CMD_ENABLE
EISA_CMD_RESET
EISA_CR	EISA Control Register
EISA_CR	EISA Control Register
eisa_device
eisa_device_enabled	Reset and enable/disable an EISA device
eisa_device_enabled	Reset and enable/disable an EISA device
eisa_device_id
eisa_driver
EISA_DRIVER(_name,_ids)
EISA_DRIVERS
EISA_GLOBAL_CONFIG
EISA_ID	EISA ID Registers
EISA_ID	EISA ID Registers
EISA_ID(_Name, _Num)
EISA_ID_SIG	IBM
EISA_ID_SIG	PnP Vendor ID (same as chip id for Crystal board)
EISA_ID_SIG	IBM
EISA_ID_SIG	PnP Vendor ID (same as chip id for Crystal board)
EISA_ID_TO_NUM(_Id)
EISA_ID0	EISA ID Register 0
EISA_ID0	EISA ID Register 0
EISA_ID1	EISA ID Register 1
EISA_ID1	EISA ID Register 1
EISA_ID2	EISA ID Register 2
EISA_ID2	EISA ID Register 2
EISA_ID3	EISA ID Register 3
EISA_ID3	EISA ID Register 3
EISA_MAX_SLOT	Must be 2^n - 1
EISA_MIN_SLOT
EISA_PNP_ID(_PNPId)
eisa_probe	Probe an EISA device
eisa_probe	Probe an EISA device
EISA_PROD_ID
EISA_REG0	EISA Configuration Register 0
EISA_REG0	EISA Configuration Register 0
EISA_REG1	EISA Configuration Register 1
EISA_REG1	EISA Configuration Register 1
EISA_REG2	EISA Configuration Register 2
EISA_REG2	EISA Configuration Register 2
EISA_REG3	EISA Configuration Register 3
EISA_REG3	EISA Configuration Register 3
eisa_remove	Remove an EISA device
eisa_remove	Remove an EISA device
EISA_SLOT_BASE( n )
EISA_VENDOR( a, b, c )
EISA_VENDOR_ID
eisabus_probe	Probe EISA root bus
eisabus_probe	Probe EISA root bus
eisabus_remove	Remove EISA root bus
eisabus_remove	Remove EISA root bus
EISCONN
EISDIR
EL_PRESENT
EL_PRESENT
EL3_CMD
EL3_CMD
el3_eisa_disable
el3_eisa_disable
el3_eisa_probe
el3_eisa_probe
EL3_STATUS
EL3_STATUS
EL3WINDOW(win_num)
EL3WINDOW(win_num)
elf.c
elf.h
elf.h
ELF_EHDR
ELF_EHDR
elf_freebsd_boot
elf_freebsd_debug_loader
elf_freebsd_find_segment_end
elf_freebsd_fixup_segment
elf_freebsd_probe
elf_load	Load ELF image into memory
elf_load_segment	Load ELF segment into memory
ELF_PROGRAM_RETURNS_BIT	e_flags bit 31
ELF_SHDR
ELF_SHDR
elf2efi.c
elf2pe	Convert ELF to PE
Elf32_Ehdr
Elf32_Phdr
ELF32_PHDR_SIZE	Size of an elf program header
Elf64_Ehdr
Elf64_Phdr
elfboot.c
elfboot_exec	Execute ELF image
elfboot_load	Load ELF image into memory
ELFCLASS32	32-bit objects
ELFCLASS64	64-bit objects
ELFCLASSNONE	Invalid class
ELFDATA2LSB	2's complement little endian
ELFDATA2MSB	2's complement big endian
ELFDATANONE	Invalid data encoding
ELFMAG
ELFMAG0
ELFMAG1
ELFMAG2
ELFMAG3
ELOOP
eltorito.c
eltorito.h
eltorito_boot_entry
ELTORITO_BOOTABLE
eltorito_exec	Execute El Torito image
eltorito_load	Load El Torito image into memory
eltorito_load_disk	Load El Torito virtual disk image into memory
eltorito_media_type
ELTORITO_PLATFORM
eltorito_read_catalog	Read and verify El Torito Boot Catalog
eltorito_read_voldesc	Read and verify El Torito Boot Record Volume Descriptor
eltorito_validation_entry
eltorito_vol_desc
ELTORITO_VOL_DESC_OFFSET
EM_386	Intel 80386+
EM_486	Perhaps disused
EM_68HC05	Motorola MC68HC05 microcontroller
EM_68HC08	Motorola MC68HC08 microcontroller
EM_68HC11	Motorola MC68HC11 microcontroller
EM_68HC12	Motorola M68HC12
EM_68HC16	Motorola MC68HC16 microcontroller
EM_68K	Motorola m68k family
EM_860	Intel 80860
EM_88K	Motorola m88k family
EM_960	Intel 80960
EM_ALIGN
EM_ARC	Argonaut RISC Core
EM_ARC_A5	ARC Cores Tangent-A5
EM_ARM	ARM
EM_AT19	STMicroelectronics ST19 8 bit mc
EM_AVR	Atmel AVR 8-bit microcontroller
EM_COLDFIRE	Motorola Coldfire
EM_CRIS	Axis Communications 32-bit embedded processor
EM_D10V	Mitsubishi D10V
EM_D30V	Mitsubishi D30V
EM_E1	Magic number for Hyperstone. Big endian format
EM_FAKE_ALPHA	Digital Alpha
EM_FIREPATH	Element 14 64-bit DSP Processor
EM_FR20	Fujitsu FR20
EM_FR30	Fujitsu FR30
EM_FX66	Siemens FX66 microcontroller
EM_H8_300	Hitachi H8/300
EM_H8_300H	Hitachi H8/300H
EM_H8_500	Hitachi H8/500
EM_H8S	Hitachi H8S
EM_HUANY	Harvard University machine-independent object files
EM_IA_64	Intel Merced
EM_JAVELIN	Infineon Technologies 32-bit embedded processor
EM_M32	AT&T WE 32100
EM_M32R	Mitsubishi M32R
EM_ME16	Toyota ME16 processor
EM_MIPS	MIPS R3000 big-endian
EM_MIPS_RS3_LE	MIPS R3000 little-endian
EM_MIPS_X	Stanford MIPS-X
EM_MMA	Fujitsu MMA Multimedia Accelerator
EM_MMIX	Donald Knuth's educational 64-bit processor
EM_MN10200	Matsushita MN10200
EM_MN10300	Matsushita MN10300
EM_NCPU	Sony nCPU embeeded RISC
EM_NDR1	Denso NDR1 microprocessor
EM_NONE	No machine
EM_NUM
EM_OPENRISC	OpenRISC 32-bit embedded processor
EM_PARISC	HPPA
EM_PCP	Siemens PCP
EM_PDSP	Sony DSP Processor
EM_PJ	picoJava
EM_PPC	PowerPC
EM_PPC64	PowerPC 64-bit
EM_PRISM	SiTera Prism
EM_RCE	Motorola RCE
EM_RH32	TRW RH-32
EM_S370	IBM System/370
EM_S390	IBM S390
EM_SH	Hitachi SH
EM_SPARC	SUN SPARC
EM_SPARC32PLUS	Sun's "v8plus"
EM_SPARCV9	SPARC v9 64-bit
EM_ST100	STMicroelectronic ST100 processor
EM_ST7	STmicroelectronics ST7 8 bit mc
EM_ST9PLUS	STMicroelectronics ST9+ 8/16 mc
EM_STARCORE	Motorola Start*Core processor
EM_SVX	Silicon Graphics SVx
EM_TINYJ	Advanced Logic Corp. Tinyj emb.fam
EM_TRICORE	Siemens Tricore
EM_V800	NEC V800 series
EM_V850	NEC v850
EM_VAX	Digital VAX
EM_VPP500	Fujitsu VPP500
EM_X86_64	AMD x86-64 architecture
EM_XTENSA	Tensilica Xtensa Architecture
EM_ZSP	LSI Logic 16-bit DSP Processor
EMAC_INT_FLOW	Flow Control Interrupt
EMAC_INT_FLOW	Flow Control Interrupt
EMAC_INT_MIB	MIB Interrupt
EMAC_INT_MIB	MIB Interrupt
EMAC_INT_MII	MII MDIO Interrupt
EMAC_INT_MII	MII MDIO Interrupt
EMBA	Enable Modified Back-off Algorithm
EMBA	Enable Modified Back-off Algorithm
EMBCMD_EDONE
EMBCMD_EDONE
EMBCMD_ERD
EMBCMD_ERD
EMBCMD_EWDIS
EMBCMD_EWDIS
EMBCMD_EWEN
EMBCMD_EWEN
EMBCMD_EWR
EMBCMD_EWR
EMBED
EMBED( _index, _path, _name )
embedded.c
embedded_init	Register all embedded images
EMFILE
EMLINK
empty_8042	Drain keyboard controller
empty_line_buffer	Discard line buffer contents
empty_line_buffer	Discard line buffer contents
EMSGSIZE
EMULTIHOP
ENABLE_DRQ_IRQ
ENABLE_DRQ_IRQ
ENABLE_DRQ_IRQ
ENABLE_DRQ_IRQ
enable_flow_control_ability	enable_flow_control_ability - flow control
enable_flow_control_ability	enable_flow_control_ability - flow control
ENABLE_IRQ
ENABLE_IRQ
enable_irq(x)
enable_mii_autopoll	enable_mii_autopoll - turn on autopolling
enable_mii_autopoll	enable_mii_autopoll - turn on autopolling
enable_multicast	enable_multicast - Enable Multicast
enable_multicast	enable_multycast - Enable Multicast
enable_multicast	enable_multicast - Enable Multicast
enable_multicast	enable_multycast - Enable Multicast
ENABLE_UTP
ENABLE_UTP
ENABLE_UTP
ENABLE_UTP
ENAMETOOLONG
Encode
ENCODE_ERROR(a)
ENCODE_WARNING(a)
END_DEVICE_PATH_TYPE
END_ENTIRE_DEVICE_PATH_SUBTYPE
END_INSTANCE_DEVICE_PATH_SUBTYP
ENDEC_LOOPBACK
ENDEC_LOOPBACK
ENDIAN
endian.h
endian.h
endian.h
endian.h
endwin	Finalise console environment
ENET_CTRL_DISABLE	EMAC Disable
ENET_CTRL_DISABLE	EMAC Disable
ENET_CTRL_ENABLE	EMAC Enable
ENET_CTRL_ENABLE	EMAC Enable
ENET_CTRL_EPSEL	External PHY Select
ENET_CTRL_EPSEL	External PHY Select
ENET_CTRL_SRST	EMAC Soft Reset
ENET_CTRL_SRST	EMAC Soft Reset
ENET_HEADER_SIZE
ENET_HEADER_SIZE
ENETDOWN
ENETRESET
ENETUNREACH
ENFILE
ENOBUFS
ENODATA
ENODEV
ENODEV
ENODEV
ENOENT
ENOERR
ENOEXEC
ENOLCK
ENOLINK
ENOMEM
ENOMEM
ENOMEM
ENOMSG
ENOPROTOOPT
ENOSPC
ENOSR
ENOSTR
ENOSYS
ENOTCONN
ENOTDIR
ENOTEMPTY
ENOTSOCK
ENOTSUP
ENOTTY
ENXIO
EOPNOTSUPP
EOVERFLOW
EP_COMMAND	Write. BASE+0x0e is always a
EP_COMMAND	Write. BASE+0x0e is always a
EP_ID_PORT_END
EP_ID_PORT_END
EP_ID_PORT_INC
EP_ID_PORT_INC
EP_ID_PORT_START	avoid 0x100 to avoid conflict with SB16
EP_ID_PORT_START	avoid 0x100 to avoid conflict with SB16
EP_STATUS	Read. BASE+0x0e is always status
EP_STATUS	Read. BASE+0x0e is always status
EP_TAG_MAX	must be 2^n - 1
EP_TAG_MAX	must be 2^n - 1
EP_W0_ADDRESS_CFG
EP_W0_ADDRESS_CFG
EP_W0_CONFIG_CTRL
EP_W0_CONFIG_CTRL
EP_W0_EEPROM_COMMAND
EP_W0_EEPROM_COMMAND
EP_W0_EEPROM_DATA
EP_W0_EEPROM_DATA
EP_W0_MFG_ID
EP_W0_MFG_ID
EP_W0_PRODUCT_ID
EP_W0_PRODUCT_ID
EP_W0_RESOURCE_CFG
EP_W0_RESOURCE_CFG
EP_W1_FREE_TX
EP_W1_FREE_TX
EP_W1_RX_PIO_RD_1
EP_W1_RX_PIO_RD_1
EP_W1_RX_PIO_RD_2
EP_W1_RX_PIO_RD_2
EP_W1_RX_STATUS
EP_W1_RX_STATUS
EP_W1_TIMER	byte
EP_W1_TIMER	byte
EP_W1_TX_PIO_WR_1
EP_W1_TX_PIO_WR_1
EP_W1_TX_PIO_WR_2
EP_W1_TX_PIO_WR_2
EP_W1_TX_STATUS	byte
EP_W1_TX_STATUS	byte
EP_W2_ADDR_0
EP_W2_ADDR_0
EP_W2_ADDR_1
EP_W2_ADDR_1
EP_W2_ADDR_2
EP_W2_ADDR_2
EP_W2_ADDR_3
EP_W2_ADDR_3
EP_W2_ADDR_4
EP_W2_ADDR_4
EP_W2_ADDR_5
EP_W2_ADDR_5
EP_W3_FREE_RX
EP_W3_FREE_RX
EP_W3_FREE_TX
EP_W3_FREE_TX
EP_W4_CTRLR_STATUS
EP_W4_CTRLR_STATUS
EP_W4_FIFO_DIAG
EP_W4_FIFO_DIAG
EP_W4_HOST_DIAG
EP_W4_HOST_DIAG
EP_W4_MEDIA_TYPE
EP_W4_MEDIA_TYPE
EP_W4_NET_DIAG
EP_W4_NET_DIAG
EP_W4_TX_DIAG
EP_W4_TX_DIAG
EP_W5_INTR_MASK
EP_W5_INTR_MASK
EP_W5_READ_0_MASK
EP_W5_READ_0_MASK
EP_W5_RX_EARLY_THRESH
EP_W5_RX_EARLY_THRESH
EP_W5_RX_FILTER
EP_W5_RX_FILTER
EP_W5_TX_AVAIL_THRESH
EP_W5_TX_AVAIL_THRESH
EP_W5_TX_START_THRESH
EP_W5_TX_START_THRESH
EP_WINDOW	Read. BASE+0x0f is always window
EP_WINDOW	Read. BASE+0x0f is always window
EPERM
EPH_STATUS
EPH_STATUS
ephy_info
ephy_info
EPIC_DEBUG	debug level
EPIC_DEBUG	debug level
epic_rx_desc
epic_rx_desc
epic_tx_desc
epic_tx_desc
epic100.c
epic100.c
epic100.h
epic100.h
epic100_bufs __shared
epic100_bufs __shared
epic100_disable
epic100_disable
epic100_init_ring
epic100_init_ring
epic100_irq
epic100_irq
epic100_open
epic100_open
epic100_poll
epic100_poll
epic100_probe	Externally visible functions
epic100_probe	Externally visible functions
epic100_registers
epic100_registers
epic100_transmit
epic100_transmit
EPIPE
eprintf(...)
eprintf(...)
eprintf(...)
EPROTO
EPROTONOSUPPORT
EPROTOTYPE
ERANGE
ERCV
ERCV
EROFS
ERR	Error summary
ERR
ERR	Error summary
ERR_ALIGNMENT
ERR_ALIGNMENT
ERR_CRC
ERR_CRC
ERR_DRIBBLE
ERR_DRIBBLE
ERR_INCOMPLETE
ERR_INCOMPLETE
ERR_MASK
ERR_MASK
ERR_OVERRUN
ERR_OVERRUN
ERR_OVERSIZE
ERR_OVERSIZE
ERR_RUNT
ERR_RUNT
ERR_RX
ERR_RX
ERR_RX
ERR_RX
ERR_RX_ALIGN
ERR_RX_ALIGN
ERR_RX_CRC
ERR_RX_CRC
ERR_RX_DRIBBLE
ERR_RX_DRIBBLE
ERR_RX_INCOMPLETE
ERR_RX_INCOMPLETE
ERR_RX_OVERRUN
ERR_RX_OVERRUN
ERR_RX_OVERSIZE
ERR_RX_OVERSIZE
ERR_RX_RUN_PKT
ERR_RX_RUN_PKT
ERRFILE
ERRFILE
ERRFILE
ERRFILE
ERRFILE
ERRFILE
errfile.h
errfile.h
errfile.h
errfile.h
ERRFILE_3c509
ERRFILE_3c509_eisa
ERRFILE_3c515
ERRFILE_3c529
ERRFILE_3c595
ERRFILE_3c5x9
ERRFILE_3c90x
ERRFILE_amd8111e
ERRFILE_aoe
ERRFILE_aoeboot
ERRFILE_arbel
ERRFILE_ARCH
ERRFILE_arp
ERRFILE_asn1
ERRFILE_asprintf
ERRFILE_ata
ERRFILE_ath5k
ERRFILE_atl1e
ERRFILE_autoboot
ERRFILE_axtls_aes
ERRFILE_b44
ERRFILE_bios_smbios
ERRFILE_biosint
ERRFILE_bitmap
ERRFILE_bnx2
ERRFILE_bootsector
ERRFILE_bzimage
ERRFILE_chap
ERRFILE_cipher
ERRFILE_com32
ERRFILE_comboot
ERRFILE_comboot_call
ERRFILE_comboot_resolv
ERRFILE_CORE	*< Core code
ERRFILE_cs89x0
ERRFILE_davicom
ERRFILE_depca
ERRFILE_dhcp
ERRFILE_dhcpmgmt
ERRFILE_dhcpopts
ERRFILE_dhcppkt
ERRFILE_dmfe
ERRFILE_dns
ERRFILE_downloader
ERRFILE_DRIVER	*< Driver code
ERRFILE_e1000
ERRFILE_e1000_hw
ERRFILE_eepro
ERRFILE_eepro100
ERRFILE_efi_image
ERRFILE_efi_pci
ERRFILE_efi_smbios
ERRFILE_efi_snp
ERRFILE_eisa
ERRFILE_elf
ERRFILE_elfboot
ERRFILE_eltorito
ERRFILE_embedded
ERRFILE_epic100
ERRFILE_etherfabric
ERRFILE_ethernet
ERRFILE_exec
ERRFILE_forcedeth
ERRFILE_ftp
ERRFILE_hermon
ERRFILE_http
ERRFILE_hw
ERRFILE_i2c_bit
ERRFILE_ib_cm
ERRFILE_ib_cmrc
ERRFILE_ib_gma
ERRFILE_ib_mcast
ERRFILE_ib_mi
ERRFILE_ib_packet
ERRFILE_ib_pathrec
ERRFILE_ib_qset
ERRFILE_ib_sma
ERRFILE_ib_srp
ERRFILE_ib_srpboot
ERRFILE_ibft
ERRFILE_icmp
ERRFILE_icmpv6
ERRFILE_ifmgmt
ERRFILE_image
ERRFILE_IMAGE	*< Image code
ERRFILE_image_cmd
ERRFILE_imgmgmt
ERRFILE_infiniband
ERRFILE_int13
ERRFILE_iobuf
ERRFILE_ipoib
ERRFILE_ipv4
ERRFILE_ipv6
ERRFILE_isa
ERRFILE_isapnp
ERRFILE_iscsi
ERRFILE_iscsiboot
ERRFILE_job
ERRFILE_legacy
ERRFILE_linda
ERRFILE_linebuf
ERRFILE_login_ui
ERRFILE_mca
ERRFILE_memmap
ERRFILE_memtop_umalloc
ERRFILE_monojob
ERRFILE_mtd80x
ERRFILE_mtnic
ERRFILE_multiboot
ERRFILE_natsemi
ERRFILE_nbi
ERRFILE_ndp
ERRFILE_ne2k_isa
ERRFILE_NET	*< Networking code
ERRFILE_net80211
ERRFILE_netdev_settings
ERRFILE_netdevice
ERRFILE_ns83820
ERRFILE_ns8390
ERRFILE_nullnet
ERRFILE_nvo
ERRFILE_nvs
ERRFILE_open
ERRFILE_OTHER	*< Any other code
ERRFILE_pci
ERRFILE_pcnet32
ERRFILE_phantom
ERRFILE_pnic
ERRFILE_pnpbios
ERRFILE_posix_io
ERRFILE_prism2_pci
ERRFILE_prism2_plx
ERRFILE_pxe_image
ERRFILE_pxe_tftp
ERRFILE_pxe_udp
ERRFILE_pxemenu
ERRFILE_pxeparent
ERRFILE_r8169
ERRFILE_resolv
ERRFILE_rtl8139
ERRFILE_rtl818x
ERRFILE_script
ERRFILE_scsi
ERRFILE_segment
ERRFILE_settings
ERRFILE_sis190
ERRFILE_sis900
ERRFILE_sky2
ERRFILE_slam
ERRFILE_smbios
ERRFILE_smbios_settings
ERRFILE_smc9000
ERRFILE_spi
ERRFILE_spi_bit
ERRFILE_srp
ERRFILE_sundance
ERRFILE_tcp
ERRFILE_tcpip
ERRFILE_tftp
ERRFILE_tg3
ERRFILE_timer_bios
ERRFILE_timer_rdtsc
ERRFILE_tlan
ERRFILE_tls
ERRFILE_tulip
ERRFILE_udp
ERRFILE_undi
ERRFILE_undiload
ERRFILE_undinet
ERRFILE_undionly
ERRFILE_undirom
ERRFILE_uri_test
ERRFILE_via_rhine
ERRFILE_via_velocity
ERRFILE_vsprintf
ERRFILE_w89c840
ERRFILE_x509